KR950009247B1 - Error correction method - Google Patents

Abstract

The method comprises the first step of generating code words by adding parity bit and transferring, the second step of receiving the code words, the third step of decoding the received code words and detecting syndrome, the fourth step of reading error position data with the address of syndrome, and the fifth step of correcting errors by doing exclusive OR operation of the error position data and the code words.

Description

How to fix error

1 is a conventional receiving side error correction circuit diagram.

2 is a code word diagram.

3 is a data coding / decoding circuit diagram to which the present invention is applied.

4 is an error correction flowchart of the present invention.

5 is another error correction flowchart of the present invention.

6 is an exemplary diagram of a table stored in the ROM.

The present invention relates to a data transmission error correction method in a digital data communication system, and more particularly, to a method for restoring original data by correcting an error with an error correction code at a receiving end.

In general, in transmitting and receiving digital data, an error may occur in the reception data depending on the transmission path or the surrounding conditions of the transmission path.

Therefore, in order to effectively remove the error occurring in the coded digital data during decoding and restore the original data, a circuit as shown in FIG. 1 is used in the conventional case. In FIG. 1, when data of the data buffer DAB and the error correction DC are simultaneously inputted in synchronization with a clock, an error is generated for each bit of data input by the error correction EC. Check the grant. If the error occurs as a result of the check, it outputs '1', and if it is normal, it outputs '0' and exclusively ORs the data output from the data buffer DAB with the adder AD5 to correct the original data whose error is corrected. Restored.

However, detecting and correcting an error by decoding in hardware as described above has not only a complicated circuit configuration, but also requires a lot of execution time and a small error correction capability of a use code.

It is therefore an object of the present invention to provide a method of avoiding complex hardware decoding and simply correcting data transmission errors by table look up.

Another object of the present invention is to provide a method of reducing error correction time.

Another object of the present invention is to provide a method for improving the error correction capability of the use code.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

In a digital data communication system, a transmitter is configured with a coder for coding original data, and a receiver is configured with a decoder for detecting an error by decoding the received data and a part for correcting an error. The present invention has a data coding / decoding circuit as shown in FIG.

In addition, an error correction code used in the present invention is a BCH (15, 7) code. The BCH represents each first letter of Base Chaudhuri Hocguenghem.

This code has the following characteristics:

Code word length: 15 bits

Data length: 7 bits

Length of parity bits: 8 bits

Error correction capability: 2 bits (some 3 bits) per code word

One codeword is constructed as shown in FIG. 1. The codeword is coded every 7 bits, and 8 bits of parity data are added to create a total of 15 bits. The side receiving this codeword performs decoding on 15 bits to detect an error and corrects the error if found.

Coding and decoding use the polynomial of the formula (1).

G (X) = X ⁸ + X ⁷ + X ⁶ + X ⁴ +1... … … (One)

3 is a circuit for performing coding and decoding according to Equation (1). In coding, 8 bits of contents of R7-R0 become parity bits after input of 7 bits of data, and 15 bits of data are input after decoding. The contents of R7-R0 become a syndrome for determining whether an error has occurred.

If the syndrome is 0, the received data is received without an error. If the syndrome is not 0, an error has occurred.

6 is a table for error correction and stored in the memory. The syndrome is an offset address and the data means an error location. The bit of data 1 of the 'ROM data' indicates the error location. Therefore, an exclusive logical OR of 7 bits of data and the 'ROM data' is inverted to correct the error.

If any data is assumed to be "100100", the exclusive OR of D7 and R7 (D-R7), and R7... The state of R0 is shown in Table 1 below.

TABLE 1

* D R7 is fed back to indicate an exclusive OR register. R7 on the first line,… The state of R0 is shown to be initialized.

If the next first data 0 is entered, D R7 becomes 0, so it can be seen that it is simply shifted.

If 1 is entered (D R7) = 1 As a result, R0, R4, R6, and R7 can be represented as in the following formulas (2) to (5).

R0 ← D R7... … … … … (2)

R4 ← (D R7) R3... … … … (3)

R6 ← (D R7) R5... … … … (4)

R7 ← (D R7) R6... … … … (5)

The values to the right of ← are the values one clock ahead of the newly entered values.

In the same way, inputting all 7 bits of data yields (R7, ..., R0) = (10010010).

Add this to the data to make a block of 15 bits:

Data parity

0 1 0 0 1 0 0 1 0 0 1 0 0 1 0

If there is no error as a result of decoding the 15-bit data on the receiving side, it is as follows (Table 2).

TABLE 2

Since up to seven bits are the same as the transmitting side, no specific details are described. The dashed horizontal line (-----) immediately above is the input of the seventh bit.

Assuming that there is no error as described above and all other things are the same and an error occurs in the last 15th bit, the received data will be (0100100 100 10011).

TABLE 3

Up to the fourteenth bit is the same as in the case of no error described above, and the data input becomes l in the fifteenth bit. Therefore, as shown in Table 3 below, the syndrome (R7 ... R0) is 1101001 in binary, which is D1 _{16 when} expressed by the hexadecimal method.

When data is read from the ROM table shown in FIG. 6 using D1 ₁₆ as an address, it is zero. That is, since no error occurred in the 7-bit data, the valid data part does not change even if it is exclusive OR, and only the parity part may be discarded.

However, if two errors occur in the second and sixth bits of the transmitted data and the actual received data is (00 001 10 100 100 10), the result of decoding by the error correction unit shown in FIG. Table 4 shows.

TABLE 4

Syndrome (R7… R0) is 01000100 in binary and 44 ₁₆ in hexadecimal notation. If data is found in the ROM table shown in FIG. 6 using the address 44 ₁₆ , (010010) is obtained. The exclusive OR of the data and the valid data (00 00 110) of the received data yields the same data (0100 100) as the valid data transmitted.

As described above, the present invention provides an error correction table on a memory, finds the corresponding data using a syndrome as an address, and obtains the same data as the valid data transmitted by exclusive OR of the received data and the received valid data. There is an advantage that can be corrected.

Claims (1)

1. A digital data transmission method having an error correction table on a memory, the method comprising: a first process of coding a transmission data in predetermined bit units and adding a parity bit to generate and transmit a code word; and a second process of receiving the code word. And a third step of decoding the received codeword to detect a syndrome, and a fourth step of reading error location data having the syndrome as an address from the error correction table, and exclusively the error location data and the codeword. And a fifth step of correcting the error by OR.