KR19980066078A - Circuits and Methods for Detecting Errors in Received Data - Google Patents

Abstract

end. The technical field to which the invention described in the claims belongs

Wireless transmitter

I. The technical problem that the invention is trying to solve

Detect and correct errors in the received data.

All. Summary of the Solution of the Invention

A syndrome generation unit for receiving information bits and parity bits to generate and output syndrome bits, a reliability determination unit for determining reliability of received data using the information bits and outputting a corresponding signal, and receiving the syndrome bits An error detector which detects whether an error of data occurs and outputs a signal corresponding thereto, and an error correction unit correcting an error of the received data detected according to a signal output from the reliability determination unit and a signal output from the error detection unit. It consists of.

la. Important uses of the invention

As the error of the received data is detected and the error is corrected, the code gain can be improved.

Description

Circuits and Methods for Detecting Errors in Received Data

The present invention relates to a circuit and a method for detecting an error generated during data transmission and reception in a wireless transmission apparatus, and more particularly, to a circuit and a method for detecting an error of received data during a decoding process.

In general, when data is transmitted and received using a digital wireless transmission device, errors in transmission data and reception data are generated due to white noise in free space.

In the conventional threshold decoding method, a parity of (nk) as an n-bit code with respect to k-bit information bits by a generation polynomial that satisfies a Convolution Self Orthogonal Code in a coding unit of a transmitting end. Add a bit. The conventional threshold decoding method detects the position of the parity bits added by the encoder of the transmitter through frame synchronization of the data received by the decoder of the receiver, and implements the parity in the same circuit implementation as the generated polynomial used by the encoder. Regenerate the bit. In the conventional threshold decoding method, a syndrome is generated by an exclusive logical OR of the received parity bit and the parity bit regenerated by the received information bit. In the conventional method of detecting an error of received data by threshold decoding, when the syndrome bit is 0, it is determined that the received data has no error, and when the syndrome bit is 1, it is determined that an error occurs in the received data.

The conventional error detection method by majority logic decoding delays a syndrome by a shift register by a delay size of a polynomial, and detects an error generated in received data using the syndrome bit. Decryption method. According to the conventional majority logic decoding method, if there are n-bit code and k-bit information bits, k majority logic decoders are required. The majority logic decoder receives a syndrome generated by the generated polynomial. In the error detection by the majority logic decoding process, if the sum of the syndromes inputted to the majority logic code exceeds a majority, it is determined that an error occurs in the corresponding received data, and if the sum of the input syndromes does not exceed the majority, It is determined that no error occurs in the received data. In addition, the conventional method for correcting an error detected in a majority logic decoding process may generate an exclusive logical OR of an error information bit detected by the majority logic decoder and the received data and generate the received data. Corrected errors.

The conventional method of detecting an error by multiple logic decoding is easy to implement the circuit, but when received data having a large number of errors that cannot be judged in the majority logic decoding process, the decoder inputs the received information signal. Even if there is an error, there is a problem that cannot be detected. In addition, the conventional error detection method of the received data by the majority logic decoding generates an error in the case of properly received data, thereby generating an error in the majority logic decoding process, thereby increasing reliability of error detection. There is a problem of deterioration.

Accordingly, an object of the present invention is to provide a circuit and a method for detecting an error of received data in a wireless transmission device.

Another object of the present invention is to provide a circuit and a method for detecting an error in a process of decoding received data at a receiving end of a wireless transmission apparatus.

It is still another object of the present invention to provide a circuit and a method for detecting an error generated in received data by determining the reliability of a corresponding received signal with an error information signal generated in a multiple logic decoder.

It is still another object of the present invention to provide an error detection circuit and a method of receiving data for minimizing an error that can be generated in a demodulator of a wireless transmission device.

It is still another object of the present invention to provide a circuit and a method for detecting an error of received data and correcting the error of the received data.

The present invention for achieving the above object is a syndrome generating unit for generating a syndrome bit by receiving information bits and parity bits, a reliability determination unit for determining the reliability of the received data with the information bits, and receiving the syndrome bits to receive the received And an error detection unit for detecting an error occurrence of data, and an error correction unit for correcting an error generated in the received data according to a control signal output from the reliability determination unit and the error detection unit.

1 is a diagram showing a configuration of a parity bit generation circuit to which the present invention is applied.

2 is a diagram showing a configuration of a circuit for detecting an error of received data according to an embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings according to a specific embodiment of the present invention will be described in detail.

1 is a diagram illustrating a configuration of a parity bit generation circuit to which the present invention is applied and is a parity bit generation circuit according to a (2,1,6) convolutional self orthogonal code scheme.

Referring to Fig. 1, (2, 1, 6) shows that the code bit n is 2 bits, the information bit k is 1 bit, and the number m of delay elements is six. Data input to the parit bit generation circuit is input to the parity bit generation unit 100. The data is also transmitted as information bits. Parity bit generator 100 generates a polynomial The circuit is configured according to the present invention, and receives data and generates and outputs a parity bit according to the generation polynomial.

2 is a diagram illustrating a configuration of a circuit for detecting an error of received data and correcting the error according to an embodiment of the present invention. The syndrome generating unit 200, the reliability determining unit 210, the syndrome delay unit 220, and the majority decision logic unit 230 are shown. AND gate 240, delay unit 250 and error correction unit 260.

Referring to FIG. 2, the received signals are separated into information bits and parity bits through frame synchronization, and are input to a circuit for detecting an error of received data according to an embodiment of the present invention. The syndrome generator 200 includes an encoder 202 and a combiner 204 to generate a syndrome by receiving the information bits and the parity bits. The encoder 202 receives an information bit in which data input from the parity bit generation circuit shown in FIG. 1 is transmitted as it is. The encoder 202 generates a polynomial as shown in FIG. The circuit is implemented according to the present invention, and receives the information bits to generate a parity bit by the generated polynomial to output to the combiner 204. The combiner 204 receives the parity bit generated by the encoder 202 and the parity bit transmitted from the parity bit generation circuit of FIG. 1, generates an exclusive OR, and generates and outputs a predetermined syndrome bit.

Although not shown in FIG. 2, the received data output from the analog / digital converter is composed of hard bits and soft bits. The hard bit represents recovered data, and the soft bit represents reliability of received data. The reliability determining unit 210 compares the soft bit with an arbitrary reference threshold to determine the reliability of the received data. The reliability determining unit 210 determines that an error does not occur in the received data when the received data is within the reference threshold range. In contrast, if the received data is out of the range of the reference threshold, the reliability determination unit 210 determines that an error occurs in the received data.

The syndrome delay unit 220 implements a circuit according to the generated polynomial. The syndrome delay unit 220 receives the syndrome bit, delays it, and outputs it to the majority decision logic unit 230. Syndrome Delay 220 Generates Polynomial As a result, the syndrome bit is delayed and output to the majority decision logic unit 230.

The majority decision logic unit 230 receives the syndrome bit output from the syndrome generating unit 200 and the signal output from the node P1 of the syndrome delay unit 220 and the signal output from the node P2 of the syndrome delay unit 220 and the signal output from the syndrome delay unit 220. The output signal according to majority logic is output to the AND gate 240.

The AND gate 240 receives the signal output from the reliability determination unit 210 and the signal output from the majority decision logic unit 230 and outputs an error correction bit that is a control signal for determining whether to correct an error generated in the received data according to a logical product. .

The delay unit 250 delays the input information bits and outputs them to the error correcting unit 260 in the same manner as the syndrome delay unit 220 delays the syndrome bits.

The error correction unit 260 is implemented with an exclusive OR, and corrects and outputs data output from the delay unit 250 according to the error correction bit output from the AND gate 240.

As described above, the present invention has an advantage of improving code gain by accurately detecting whether an error occurs in the received data and correcting an error generated in the received data.

Claims (5)

A circuit for detecting an error of received data in a wireless transmission apparatus, comprising: a syndrome generator for receiving and transmitting syndrome bits and generating and outputting syndrome bits; and determining the reliability of received data by receiving the information bits. A reliability determination unit for outputting a signal corresponding thereto, an error detection unit for receiving the syndrome bit, detecting an error occurring in the received data, and outputting a signal corresponding thereto, and outputting the reliability determination unit and the error detection unit And error correction means for correcting an error of the received data according to a signal. The received data error of claim 1, wherein the error correcting unit logically multiplies the signal output from the reliability determining unit with the signal output from the error detecting unit, and corrects the error of the received data according to the result. Circuit for detecting. A method for detecting an error of received data in a wireless transmission device, the method comprising: determining the reliability of the received data by comparing the received data with a predetermined reference threshold and determining whether an error occurs in the received data according to a majority decision logic; And detecting an error occurring in the received data according to a result of the reliability determination process of the received data and an error occurrence determination process of the received data. 4. The method of claim 3, wherein when the received data falls within the reference threshold range in the process of determining reliability of the received data, it is determined that no error occurs in the received data. And determining that an error has occurred in the received data if the received data is out of the reference threshold range. 4. The method of claim 3, wherein if the error occurrence of the received data is detected in both the reliability determination process of the received data and the error occurrence detection process, the error of the received data is corrected. How to detect.