KR100407131B1 - Reed solomon decoder using combinational circuits - Google Patents

Abstract

The present invention is a reed-solomon decoder that decodes an error symbol obtained by syndrome test of input data, and comprises a plurality of AND gates for input processing the input symbols and a plurality of OGs for logical operation of output signals of the AND gates. A reciprocal calculation combining circuit unit for obtaining the reciprocal c of the pidget number a during the calculation of b / a; The present invention provides a Reed-Solomon decoder using a combination circuit including a multiplication operation circuit unit configured to multiply the output signal (b) and the output signal (c) by the inverse calculation combination circuit unit and combine a plurality of XOR gates and an AND gate.

As described above, the present invention provides a limited number of reciprocals by patterning the inverse (c) of the error weights (a) that may occur so that an inverse (c) corresponding thereto is output when an arbitrary error weight (a) is input. This makes the implementation cost cheaper and improves the processing speed.

Description

Reed-Solomon Decoder Using Combination Circuits {REED SOLOMON DECODER USING COMBINATIONAL CIRCUITS}

The present invention relates to a Reed Solomon decoder applied to a receiving end of a digital communication system. More specifically, the present invention relates to a combination of arbitrary division operations performed in a Reed-Solomon decoder without a separate processor. The present invention relates to a Reed-Solomon decoder using a combination circuit composed of a circuit and processed by inverse and multiplication.

In a highly developed information society, an efficient, fast and reliable information delivery system is absolutely required. To realize this, there must be a reorganization of the improved communication system based on various communication means involving computers and breakthrough technological innovation. However, one of the inevitable problems in the communication system is the occurrence of an error due to noise on a channel, which makes it difficult to accurately transmit information.

In order to overcome this problem and efficiently perform information delivery, the transmitting side should encode information so that the receiving side can efficiently correct an error occurring on the transmission path.

In order to perform error correction effectively, various codes have emerged, which are largely divided into block code and convolution code. The main difference between the encoders for these two types of codes is that the former does not contain memory, whereas the latter does contain memory.

The block code can be divided into linear code and cyclic code. The BCH (Bose-Chaudhuri Hocquenghem) code, which is a representative example of the cyclic code, is relatively simple in structure and can correct multiple errors. There is an advantage.

These BSI codes can be divided into binary BSI codes and non-binary BSI codes. Codes applied to the Solomon decoder are non-binary BSI codes. It is known to be the best at correcting burst errors.

The Reed-Solomon code is represented by RS (n, k) and can correct (nk) / 2 symbol errors. Reed-Solomon code is Is a polynomial that is generated by dividing k serial symbol inputs by g (x) and sending the remainder (nk symbol) that occurs. The receiver divides the n input symbols into g (x) again. If there is an error in the input symbol, the syndrome test value does not become '0' and determines the position and weight of the error symbol.

In the case of the Reed-Solomon code, RS (17, 15) code transmits two overhead symbols when transmitting 15 symbols. One symbol consists of five bits. Accordingly, one symbol can be corrected and a maximum of five bit errors can be corrected. 1 shows an encoding part of a Reed-Solomon code.

In the drawing Is composed of 5 parallel registers (symbols), and the generation function of the encoding circuit is to be. When all 15 symbols have passed Wow The remaining value remains in error correction parity. One symbol of the two error correction parities represents the weighting of the error and the other symbol represents the location of the error. In the galoa field of Use

The decoding operation by the Reed-Solomon decoder is performed in the following manner.

First, a syndrome is obtained from the input data, and the error locator polynomial and the error evaluator polynomial are calculated using the syndrome. Error location polynomial and error estimation The error correction is performed by finding the location and value of the error from the polynomial and correcting the error in the input data.

Above, a method for calculating the syndrome of input data has been disclosed in Lin Costello's Error control coding.

On the other hand, if the code encoded by the Reed-Solomon encoder of the transmitter has too many errors, that is, if the error correction capability of the Reed-Solomon decoder of the receiver is exceeded, the error cannot be corrected. Whether or not there is an error in the data can be important information in the signal processing part connected after the receiving end.

Figure 1 shows the structure of a conventional Reed-Solomon decoder.

As shown in the figure, a gate 1 for distinguishing between using an error correction function of a received signal and a case where the error correction function is not used and a signal received through the gate 1 are syndrome-tested to determine the error weight a and the position of the error. An error position and an error value from the output of the syndrome test unit 2 for outputting a value b that can be deduced, a division operation unit 3 for performing the operation of b / a, and an output of the division operation unit 3 An error detector 4 for detecting a signal, an n-stage buffer 5 for storing a signal received through the gate 1, an error position and an error value of the error detector 4, and receiving n- and a summer 6 for receiving and adding the output data signal of the stage buffer 5 to correct the error and outputting the error.

The syndrome test unit 2 includes a parity (weighting) check block for obtaining an error weight a and a block for calculating a value b for inferring an error occurrence position.

3 shows the parity (weight) check block. As shown in the parity check block, the received signal is If Calculate

4 shows a block for calculating the position of occurrence of an error. As shown Calculate the value.

In the division calculating section 3, obtained from the parity check block. Obtained from a block that calculates the occurrence of Using By calculating, you can find out where the error occurred.

In the case of the RS (17, 15) code, the operation and effect of the conventional Reed-Solomon decoder will be described.

RS (17,15) code transmits a total of 17 symbols by adding two overhead symbols to 15 symbols. Then, the error symbol of (17-5) / 2 = 1 can be corrected. Produce polynomials This expression is also used for the syndrome test at the receiving end. The syndrome test is carried out by the syndrome test section 2 and the 15 symbols inputted are medium Divide by to obtain the weight symbol a of the error symbol (in FIG. )). And input symbol Divide by to get the value (b) from which the location of the error symbol can be inferred (in FIG. 4). )). The division calculating section 3 executes b / a, and the error detecting section 4 uses the result to find the position and value of the error symbol accurately. The error correction unit 6 receives the position and the value of the error symbol thus obtained, receives the received data stored in the n-stage buffer 5 for error correction, and corrects the error using the XOR gate.

In this case, a CPU or DSP chip is used in the division calculating section 3, and the calculation of b / a is calculated by the shift register, so that too much time is required and error correction cannot be performed.

As described above, since the Reed-Solomon code is a non-binary signal, a random division operation is required in the syndrome test. So we need a processor that can handle division operations at high speed. Therefore, many problems arise in cost and processing speed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and includes a reed-solomon decoder using a combination circuit configured to perform an inverse operation and a multiplication operation by forming a combination circuit without any processor. To provide that purpose.

In order to achieve the above object, the present invention provides a logic method for performing logical operation on a plurality of AND gates for processing the input symbols and the output signals of the AND gates in a Reed-Solomon decoder which decodes an error symbol obtained by syndrome testing input data. A reciprocal calculation combining circuit portion composed of a plurality of oragates, for obtaining the reciprocal number c of the pidget number a during the calculation of b / a; The present invention provides a Reed-Solomon decoder using a combination circuit including a multiplication operation circuit unit configured to multiply the output signal (b) and the output signal (c) by the inverse calculation combination circuit unit and combine a plurality of XOR gates and an AND gate.

1 is a structural diagram of a conventional Reed-Solomon decoder,

2 is an encoding block diagram of a typical Reed-Solomon code,

3 is a parity check block diagram of a general syndrome test unit;

4 is a block diagram for calculating an error occurrence position of a general syndrome test unit;

5 is a structural diagram of a Reed-Solomon decoder according to an embodiment of the present invention;

6 is a detailed circuit diagram of a reciprocal calculation combining unit according to an embodiment of the present invention;

7 is a detailed circuit diagram of a multiplication operation unit according to an embodiment of the present invention;

Explanation of symbols on the main parts of the drawings

10: gate 20: syndrome test unit

30: inverse calculation combination circuit unit 40: multiplication calculation circuit unit

50: error detection unit 60: n-stage buffer

70: summer

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

5 shows a structure of a Reed-Solomon decoder according to an embodiment of the present invention.

As shown in the figure, the gate 10 for distinguishing between the case of using the error correction function of the received signal and the other case and the syndrome received by the signal received through the gate 10 are syndrome-tested and the position of the error weight a and the error. Syndrome test unit 20 for outputting a value (b) that can be deduced, reciprocal calculation combination circuit unit 30 for calculating the inverse (c) of the pidget number a during the calculation of the b / a, and b and a multiplication operation circuit unit 40 for performing a multiplication of c, an error detection unit 50 for detecting an error position and an error value from an output of the multiplication operation circuit unit 40, and a signal received through the gate 10 Receives the n-stage buffer (60) and the error position and the error value of the error detection unit 50, and receives and sums the output data signal of the n-stage buffer (60) to correct the error and output Is composed of a summer 70.

The operation of the Reed-Solomon decoder configured as described above is as follows.

The present invention has been improved in performing the division operation performed in the division operation unit 3 of the conventional Reed-Solomon decoder.

In other words, the syndrome test unit 20 may syndrome test the received signal to know a weight a of the error and a value b multiplied by a position of the weight a of the error. Then, the b / a operation is performed. In the present invention, the pidget portion (b / a to a) is changed without using the shift register. That is, b / a was changed to b * 1 / a.

This is a multiplication operation The distribution law of is true, but in division operation Is not true.

Accordingly, in performing the operation of b / a, the syndrome test unit 20 in the reciprocal calculation combining circuit 30 uses b / a = b * 1 / a = b * c (c is an inverse of a). A value obtained from a) is obtained, and the inverse c is obtained. The multiplication operation unit 40 performs b * c operation using the c to perform b * (1 / a) to extract only the position value of the error. Serve The error detection unit 50 uses this value to detect the position and value of the error symbol.

The summer 70 corrects the error by performing an XOR operation on the weight of the error at the position of the symbol in which the error occurred among the received signals passing through the n-stage buffer 60 by using the position and the value of the error symbol thus obtained. Then reinitialize the syndrome test unit 20 to prepare to receive the next received signal.

6 shows a specific circuit of the reciprocal calculation combining unit.

In the figure, SO_1 to SO_5 are five bits representing the weight a of the error obtained through the syndrome test, and DIV1 to DIV5 represent five bits representing the inverse c of a. The combination circuit shown in FIG. 5 provides a limited number of inverses by inversely patterning the inverse number c of the error weights a that can occur so that a corresponding inverse number c is outputted when an arbitrary error weight value a is input. To be combined.

To design such a combination circuit, a mathematical concept called a galoa field is used as described above. In Reed-Solomon code, one symbol is 5 bits. to be. to be. Since the symbol consists of 5 bits, Has the number of cases. Therefore, the required reciprocal has 32 cases, and each of the 32 reciprocals is obtained in advance to form a table. A canoe map is used to optimize the table obtained here. Thus, the combination circuit shown in FIG. 6 is a circuit combined to obtain the inverse by optimizing using a canoe map or a table method. Since only a reciprocal of the number 32 of binary values consisting of 5 bits representing the error weight a needs to be generated, a simple combination circuit as shown is designed to provide a conventional CPU or DSP chip and a shift register according to its operation. It was not necessary.

7 shows a specific circuit of the multiplication operation unit. In the drawings, A1 to A5, B1 to B5, C1 to C5, D1 to D5, and E1 to E5 are values obtained by performing b * c. Using these values, the error detector 50 obtains the position and value of the error. DS1_1 to DS1_5 represent one clock delay values of b obtained from the syndrome test section 20, and DIV_Y1 to DIV_Y5 represent values obtained by one clock delay of c (DIV1 to DIV5) obtained from the inverse calculation combination section 30. The reason why the multiplication operation circuit portion is composed of multiple AND gates and XOR gates is because of the uniqueness of the GF (galoa field).

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common knowledge in the art that various substitutions, conversions, and changes can be made without departing from the technical spirit of the present invention. It will be apparent to those who have

As described above, when the arbitrary division circuit is implemented in a combination form according to the present invention, the time delay of the register is reduced for the division operation, compared to the conventional operation using the shift register, thereby reducing the implementation cost and improving the processing speed. You can do it.

In particular, a conventional commercially available RS code chip has to be used for the Reed-Solomon code. However, in order to implement the reciprocal calculation combination circuit of the present invention, an optimum combination circuit is output through a canoe map. The configuration provides an effect that can replace the conventional RS code chip.

Claims (3)

A Reed-Solomon decoder for decoding an error symbol obtained by syndrome test of input data, A reciprocal calculation combination for calculating an inverse (c) of the number of pidgets a when calculating b / a, comprising a plurality of AND gates for input processing the input symbols and a plurality of OA gates for logical operation of output signals of the AND gates. A circuit section; Reed-Solomon decoder using a combination circuit characterized in that the multiplication operation of the output signal (b) and the output signal (c) of the inverse calculation combination circuit unit and a combination of a plurality of XOR gate and the end gate . delete According to claim 1, wherein the reciprocal calculation combination circuit unit is inverse of the error weight (a) that can be generated so that the corresponding reciprocal (c) when a certain error weight (a) is input canoe-map Reed-Solomon decoder using a combination circuit, characterized in that the combination circuit is patterned through to provide a limited number of inverse.