KR950009242Y1 - Control circuit for lcd - Google Patents
Control circuit for lcd Download PDFInfo
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- KR950009242Y1 KR950009242Y1 KR2019890016322U KR890016322U KR950009242Y1 KR 950009242 Y1 KR950009242 Y1 KR 950009242Y1 KR 2019890016322 U KR2019890016322 U KR 2019890016322U KR 890016322 U KR890016322 U KR 890016322U KR 950009242 Y1 KR950009242 Y1 KR 950009242Y1
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- South Korea
- Prior art keywords
- liquid crystal
- register
- signal
- control circuit
- integer
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
내용 없음.No content.
Description
제1도는 종래의 액정표시장치의 블럭도.1 is a block diagram of a conventional liquid crystal display device.
제2도는 븐 고안에 의한 액정표시장치의 블럭도.2 is a block diagram of a liquid crystal display device according to the invention.
제3도는 본 고안에 의한 M신호 발생에 관한 일 실시프로그램의 플로챠트.3 is a flowchart of an exemplary program for generating M signals according to the present invention.
제4도는 제3도의 타이머 서브루틴의 플로챠트.4 is a flowchart of the timer subroutine of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 액정 모듈 20 : 액정 구동회로10: liquid crystal module 20: liquid crystal drive circuit
30 : 제어회로 31 : 프로세서30: control circuit 31: processor
32 : 카운터32: counter
본 고안은 액정표시제어장치에 관한 것으로, 특히 액정구동 출력파형을 교류로 변환하기 위한 제어신호의 발생에 관한 것이다.The present invention relates to a liquid crystal display control device, and more particularly to the generation of a control signal for converting the liquid crystal drive output waveform to an alternating current.
액정표시장치는 직류로 구동할 경우 액정 셀의 내부에 전기화학반응이 유발되기 때문에 수명이 현저히 감소한다. 따라서 통상 액정구동출력은 일정진폭의 위상이 서로 어긋난 교류진압을 인가한다. 이 경우 액정의 평균전압은 "0"이 되어 액정의 열화가 방지되게 된다.When the liquid crystal display is driven by direct current, its life is significantly reduced because electrochemical reactions are induced inside the liquid crystal cell. Therefore, the liquid crystal drive output normally applies AC suppression in which phases of constant amplitude are shifted from each other. In this case, the average voltage of the liquid crystal becomes " 0 " to prevent deterioration of the liquid crystal.
통상의 액정모듈(10)은 제1도에 도시한 바와같이 제어회로(30)로부터 제어신호를 공급받아 액정구동출력 신호를 발생하는 액정구동회로(20)에 연결되어 구동된다. 액정구동회로(20)는 제어회로(30)로부터 제어신호, 즉 데이타, 데이타 전송출력, 래치클럭, 액정구동출력파형을 교류로 변환하기 위한 신호(통상 M신호라 칭한다)를 공급받는다. 종래의 제어회로(30)에서는 M신호를 발생하기 위해 프로세서(31)로부터 어드레스래치 인에이블 신호를 2진 카운터(32)에 공급하고 이에 2진 카운터(32)로 데이타 전송클럭을 분주하여 소정 주기의 M신호를 발생하였다. 이 방식에서는 하드웨어적으로 M신호를 발생하므로 부품수가 증가되고 한편, 이들 부품에 의한 노이즈등으로 인한 신뢰성이 떨어진다. 또한, 이러한 하드웨어 구성은 M신호의 시방변경을 어렵게 한다.The conventional liquid crystal module 10 is connected to and driven by the liquid crystal drive circuit 20 that receives the control signal from the control circuit 30 and generates the liquid crystal drive output signal as shown in FIG. 1. The liquid crystal drive circuit 20 receives a control signal from the control circuit 30, that is, a signal (commonly referred to as M signal) for converting data, data transfer output, latch clock, and liquid crystal drive output waveform into alternating current. In the conventional control circuit 30, an address latch enable signal is supplied from the processor 31 to the binary counter 32 in order to generate an M signal, and the data transfer clock is divided into the binary counter 32 so as to generate a predetermined period. Generated an M signal. In this system, since the M signal is generated in hardware, the number of parts is increased, while reliability due to noise by these parts is lowered. This hardware configuration also makes it difficult to change the specification of the M signal.
따라서, 본 고안의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 소프트웨어적으로 M신호를 발생할 수 있는 액정표시 제어장치를 제공하는데 있다.Accordingly, an object of the present invention is to provide a liquid crystal display control device capable of generating M signals in software in order to solve the above problems of the prior art.
상기 목적을 달성하기 위하여 본 고아은 내부 타이머에 의해 주기를 설정하고 이설정된 주기에 따라 M신호 출력포트의 출력상태반전을 제어하는 프로세서를 구비한 것을 특징으로 한다.In order to achieve the above object, the orphan has a processor which sets a period by an internal timer and controls an output state inversion of the M signal output port according to the set period.
첨부한 도면을 통하여 본 고안을 보다 상세히 설명하면 다음과 같다.Referring to the present invention in more detail through the accompanying drawings as follows.
제2도는 본 고안에 의한 액정표시장치의 블럭도이다. 제1도에서 액정모듈(10)은 액정구동회로(20)에 의해 구동신호를 공급받고 이 액정구동회로(20)는 본 고안에 의한 프로세서(31)로 부터 M신호를 공급받기 위해 프로세서(31)의 출력포트 M에 연결되어서 이루어 진다. 여기서 프로세서(31)와 액정구동회로(20)간의 단 신호연결구성은 생략한 것이다. 상기 프로세서(31)는 제3도 및 제4도의 플로챠트에 의해 일정 주기의 M신호를 출력포트 M를 통해 발생하게 된다. 제3 및 제4도를 통하여 본 고안의 M신호 발생을 설명하기로 한다.2 is a block diagram of a liquid crystal display device according to the present invention. In FIG. 1, the liquid crystal module 10 receives a driving signal by the liquid crystal driving circuit 20, and the liquid crystal driving circuit 20 receives the M signal from the processor 31 according to the present invention. It is connected to the output port M of). Here, the short signal connection configuration between the processor 31 and the liquid crystal driver circuit 20 is omitted. The processor 31 generates M signals of a predetermined period through the output port M according to the flowcharts of FIGS. 3 and 4. 3 and 4 will be described in the generation of the M signal of the present invention.
제3도에 있어서, 제어 프로그램이 시작되면 시스템을 초기화하고 (제100단계) A 레지스터에 M신호의 초기레벨을 세트한다(제101단계). 상기 101단계에서 세트된 초기레벨, 예컨대 하이레벨이면 출력포트 M의 출력상태를 하이상태로 한다(102단계). 출력포트 M의 상태를 하이상태로 한 연후에 이 하이상태 시간을 미리 설정된 시간만큼 유지하기 위해 시간체크를 수행한다(제103단계). 상기 103단계에서 소정의 설정시간이 되면 A레지스터의 내용을 반전시키고(제104단계) 상기 102단계로 되돌아 간다. 그러므로 출력포트 M의 출력상태는 로우상태로 전환되고 이어서, 103단계를 수행하여 이번에는 로우상태 시간을 미리 설정된 시간만큼 유지하기 위해 시간체크를 수행하게 된다. 이와 같이 102단계, 103단계, 104단계를 순차 반복함으로써 출력포트 M의 출력상태는 일정주기로 하여, 로우상태를 반복하게 되어 듀티 50%의 구형파를 M신호로 발생할 수 있다.In FIG. 3, when the control program starts, the system is initialized (step 100) and the initial level of the M signal is set in the A register (step 101). If the initial level set in step 101, for example, a high level, the output state of the output port M is set to a high state (step 102). After the state of the output port M is set to the high state, a time check is performed to maintain the high state time for a predetermined time (step 103). When the predetermined time is reached in step 103, the contents of the A register are inverted (step 104), and the process returns to step 102. Therefore, the output state of the output port M is changed to the low state, and then, in step 103, a time check is performed to maintain the low state time for a predetermined time. By repeating steps 102, 103, and 104 in this manner, the output state of the output port M may be repeated at a constant period, and the low state may be repeated to generate a square wave having a duty of 50% as the M signal.
상기 M신호의 주기는 제4도에 도시한 플로챠트에 의해 설정된다. 즉 상술한 103단계에서 제4도의 타이머서브루틴이 호출되고 이에, 타이머 서브루틴은 D레지스터에 제1정수를 세트시키고(111 단계), E레지스터에 제2정수를 세트시킨다(112 단계). 그런 연후에 E레지스터의 제2정수를 1씩 감산하고(113 단계) 이를 되풀이하여 E레지스터의 내용이 "0"이 되었는가를 체크한다(114단계). 상기 114 단계에서 E레지스터의 내용이 "0"이면 D레지스터의 제1정수를 1씩 감산하고 (115 단계), 이후에 D레지스터의 내용이 "0"가 되었는가를 체크한다(116단계). 만약 116 단계에서 "0"이 아니면 상기 112단계를 다시 수행하고 "0"이면 리턴하여 제3도의 104단계를 수행하게 되는 것이다.The period of the M signal is set by the flowchart shown in FIG. That is, in step 103, the timer subroutine of FIG. 4 is called, and the timer subroutine sets the first integer in the D register (step 111) and the second integer in the E register (step 112). After that, the second integer of the E register is subtracted by one (step 113), and it is checked repeatedly whether the contents of the E register become "0" (step 114). If the content of the E register is "0" in step 114, the first integer of the D register is subtracted by one (step 115), and then it is checked whether the content of the D register becomes "0" (step 116). If step 116 is not "0", step 112 is performed again, and if "0" is returned, step 104 of FIG. 3 is performed.
따라서, M신호의 하이상태 또는 로우상태 시간은 상기 D, F 레지스터의 제1정수와 제2정수의 곱으로 설정되게 된다. 그러므로 M신호의 주파수 fM은로 주어지게 된다.Therefore, the high state or low state time of the M signal is set as the product of the first and second integers of the D and F registers. Therefore, the frequency fM of the M signal is Is given by.
이와같이 본 고안에서는 프로세서의 내부 레지스터를 이용하여 소프트웨어적으로 M신호의 주파수를 임의로 설정할 수 있으므로 시방변경이 자유롭다. 또한 종래의 하드웨어적인 M신호 발생 방식에 비하여 부품수를 줄일 수 있어 회로구성이 간단하게 되고 신뢰성을 향상시킬 수 있다.Thus, in the present invention, since the frequency of the M signal can be arbitrarily set by software using the internal register of the processor, the specification can be freely changed. In addition, since the number of parts can be reduced as compared with the conventional M signal generation method, the circuit configuration can be simplified and the reliability can be improved.
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KR2019890016322U KR950009242Y1 (en) | 1989-11-04 | 1989-11-04 | Control circuit for lcd |
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KR2019890016322U KR950009242Y1 (en) | 1989-11-04 | 1989-11-04 | Control circuit for lcd |
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KR910009677U KR910009677U (en) | 1991-06-29 |
KR950009242Y1 true KR950009242Y1 (en) | 1995-10-23 |
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KR2019890016322U KR950009242Y1 (en) | 1989-11-04 | 1989-11-04 | Control circuit for lcd |
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