KR950009242Y1 - Control circuit for lcd - Google Patents

Abstract

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Description

Control circuit of liquid crystal display

1 is a block diagram of a conventional liquid crystal display device.

2 is a block diagram of a liquid crystal display device according to the invention.

3 is a flowchart of an exemplary program for generating M signals according to the present invention.

4 is a flowchart of the timer subroutine of FIG.

* Explanation of symbols for main parts of the drawings

10: liquid crystal module 20: liquid crystal drive circuit

30: control circuit 31: processor

32: counter

The present invention relates to a liquid crystal display control device, and more particularly to the generation of a control signal for converting the liquid crystal drive output waveform to an alternating current.

When the liquid crystal display is driven by direct current, its life is significantly reduced because electrochemical reactions are induced inside the liquid crystal cell. Therefore, the liquid crystal drive output normally applies AC suppression in which phases of constant amplitude are shifted from each other. In this case, the average voltage of the liquid crystal becomes " 0 " to prevent deterioration of the liquid crystal.

The conventional liquid crystal module 10 is connected to and driven by the liquid crystal drive circuit 20 that receives the control signal from the control circuit 30 and generates the liquid crystal drive output signal as shown in FIG. 1. The liquid crystal drive circuit 20 receives a control signal from the control circuit 30, that is, a signal (commonly referred to as M signal) for converting data, data transfer output, latch clock, and liquid crystal drive output waveform into alternating current. In the conventional control circuit 30, an address latch enable signal is supplied from the processor 31 to the binary counter 32 in order to generate an M signal, and the data transfer clock is divided into the binary counter 32 so as to generate a predetermined period. Generated an M signal. In this system, since the M signal is generated in hardware, the number of parts is increased, while reliability due to noise by these parts is lowered. This hardware configuration also makes it difficult to change the specification of the M signal.

Accordingly, an object of the present invention is to provide a liquid crystal display control device capable of generating M signals in software in order to solve the above problems of the prior art.

In order to achieve the above object, the orphan has a processor which sets a period by an internal timer and controls an output state inversion of the M signal output port according to the set period.

Referring to the present invention in more detail through the accompanying drawings as follows.

2 is a block diagram of a liquid crystal display device according to the present invention. In FIG. 1, the liquid crystal module 10 receives a driving signal by the liquid crystal driving circuit 20, and the liquid crystal driving circuit 20 receives the M signal from the processor 31 according to the present invention. It is connected to the output port M of). Here, the short signal connection configuration between the processor 31 and the liquid crystal driver circuit 20 is omitted. The processor 31 generates M signals of a predetermined period through the output port M according to the flowcharts of FIGS. 3 and 4. 3 and 4 will be described in the generation of the M signal of the present invention.

In FIG. 3, when the control program starts, the system is initialized (step 100) and the initial level of the M signal is set in the A register (step 101). If the initial level set in step 101, for example, a high level, the output state of the output port M is set to a high state (step 102). After the state of the output port M is set to the high state, a time check is performed to maintain the high state time for a predetermined time (step 103). When the predetermined time is reached in step 103, the contents of the A register are inverted (step 104), and the process returns to step 102. Therefore, the output state of the output port M is changed to the low state, and then, in step 103, a time check is performed to maintain the low state time for a predetermined time. By repeating steps 102, 103, and 104 in this manner, the output state of the output port M may be repeated at a constant period, and the low state may be repeated to generate a square wave having a duty of 50% as the M signal.

The period of the M signal is set by the flowchart shown in FIG. That is, in step 103, the timer subroutine of FIG. 4 is called, and the timer subroutine sets the first integer in the D register (step 111) and the second integer in the E register (step 112). After that, the second integer of the E register is subtracted by one (step 113), and it is checked repeatedly whether the contents of the E register become "0" (step 114). If the content of the E register is "0" in step 114, the first integer of the D register is subtracted by one (step 115), and then it is checked whether the content of the D register becomes "0" (step 116). If step 116 is not "0", step 112 is performed again, and if "0" is returned, step 104 of FIG. 3 is performed.

Therefore, the high state or low state time of the M signal is set as the product of the first and second integers of the D and F registers. Therefore, the frequency fM of the M signal is Is given by.

Thus, in the present invention, since the frequency of the M signal can be arbitrarily set by software using the internal register of the processor, the specification can be freely changed. In addition, since the number of parts can be reduced as compared with the conventional M signal generation method, the circuit configuration can be simplified and the reliability can be improved.

Claims (1)

The liquid crystal drive circuit 20 generating an AC voltage applied to the liquid crystal module 10 in response to the control signal M, and the control circuit 30 generating the control signal M applied to the liquid crystal drive circuit. A liquid crystal display device comprising: an output port for outputting the control signal M; A first register for setting an initial level of the control signal output from the output port; And a second register having a first integer set therein and a third register having a second integer set thereon, subtracting the second integer of the third register by 1 and subtracting the first integer of the second register by 1 And a processor for inverting the initial level of the first register when the value is 0.