KR900001529Y1 - Double character generator of terminal display device - Google Patents

Abstract

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Description

Double Size Character Generation Circuit in Terminal Display

1 is a block diagram of a signal generator for a terminal of the present invention.

2 is a circuit diagram of a double width (DW) generation unit of the present invention.

3 is an output waveform diagram showing a signal generator for a terminal of the present invention.

* Explanation of symbols for main parts of the drawings

A: COLUMN selector B: Basic signal generator

C: Double width (DW) generating part 10: Logic circuit part

20: Binary coefficient (COUNTER) circuit part 30, 40: Multiplex (MUX1, MUX2)

AND ~ AND9: AND gate OR1, OR2: OA gate

I ₁ ~ I ₃ : Inverter circuit FF ₁ ~ FF ₃ : Flip-flop

The present invention relates to a double-character generation circuit in a terminal display device for displaying the character code by doubling (DOUBLE-WIDTH) when displaying the character (CHARACTER) in the computer terminal device.

Conventionally, the character clock (in the circuit for displaying the double size letters by changing the dot clock (DOT-CLK ₂ ) and the terminal control (TC) signal with the configuration of the basic signals (DOT-CLK, CCLK, TC) of the terminal). In order to make CCLK) signal and terminal control (TC) signal, hardware counter circuit was added separately.

The present invention was devised to solve the above-mentioned drawbacks. In order to double the dot clock (DOT-CLK2) and the terminal control (TC) signal at the double width (COUBLE-WIDTH), the dot clock (DOT-CLK2) ) And the terminal control (TC) signal are input to the binary (MODULUS-2) counting circuit (COUNTER) to generate a new dot clock (DOT-CLK2) and terminal control (TC) signal to improve the processing speed. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 1, one of clock 1 clock 2 is selected by a column selection signal COL-SE by receiving a clock signal CLOCK1.CLOCK2 for displaying 132 and 80 characters per line. A signal used for outputting the basic signals A to D and the character pattern output of the terminal using the column selector a and the dot clock DOT-CLK1 that generates the dot clock DOT-CLK1 as a reference clock ( The basic signal generator (b) and the double-width signal (DW), the basic signal (A ~ D), the dot clock (DOT-CLK1), which receive these three signals, receive the normal size, the letters, and the double sized letters. It consists of a double-width signal generator (C) that generates a terminal control (TC) signal and another dot clock (DOT-CLK2) signal for display, and the clock (CLOCK1) and the clock (CLOCK2) are column selection (COL-). According to the signal of SE), 132 letters and 80 letters per line are displayed on the screen through the column selector (a), and the basic signal generator (b) receives the output signal (DOT-CLK1) of the column selector (a). As shown in Fig. 3, a basic signal of A to D is generated to enter the input of the double width DW generating unit c.

The double width (DW) generation unit (C) includes the basic signals A to D and the double width ( Signal is generated to generate terminal control (TC) signal and dot clock (DOT-CLK2) through appropriate logic.

FIG. 2 is a detailed circuit diagram of the double-width generating unit (C) of FIG. _{1. The} logic unit 10 and the AND gate AND ₄ , which are composed of an AND gate AND ₁ to AND ₃ flip-flop FF ₁ inverter I ₁ , are illustrated in FIG. AND ₅ ) Flip-flop (FF ₂ ) Binary coefficient (COUNTER) circuit part consisting of inverters (I ₂ , I ₃ ) 20 End gate (AND ₆ , AND ₇ ) and Oa gate (OR ₁ ) Terminal control Multiplexer (MUX1: 30) that generates a (TC) signal is composed of an AND gate (AND ₉ and AND ₉ ) and an OR gate (OR ₂ ) to generate a dot clock (DOT-CLK2) signal and to the multiplexer (MUX2: 40). The column selector (A) composed of the double-width (DW) generating circuit (C) configured to receive the signals CLOCK1 and CLOCK2 receives the dot clock (DOT-) according to the column selection (132, 80) signals (COL-SE). When the CLK1) signal is generated, the basic signal generator (b) generates the basic signal waveforms A to D as shown in FIG.

The basic signals A and D generate an output waveform diagram of the signal S ₁ shown in FIG. 3 through the AND gate AND ₁ , and the basic signals A and C generate the AND gate AND2. Through this, the waveform of the signal S ₂ shown in FIG. 3 is generated. Thus, the flip-flop FF ₁ receives the signal in which the basic signal B is inverted through the inverter I ₁ and the locus signal of the flip-flop FF ₁ , and thus the waveform of the signal S ₃ shown in FIG. 3. The signal S ₁ waveform and the signal S ₃ waveform generate a signal S ₄ waveform diagram shown in FIG. 3 through an AND gate AND ₃ . Then, the AND gate (AND _6, AND ₇₎ and outputs a terminal control (TC) signals over the Iowa gate (OR ₁₎ its output signal to the input of the signal wave (S ₁₎ and a signal wave (S ₄₎ .

In addition, the signal inverted through the inverter I ₂ and the signal S _{2 in the} dot clock DOT-CLK1 generate the signal waveform S ₅ shown in FIG. 3 through the AND gate AND ₄ . The flip flop FF ₂ generates the signal waveform S ₆ shown in FIG. 3 according to the state of the signal S ₅ .

The signal S ₆ and the double width ( Signal generates the signal waveform S ₇ shown in FIG. 3 through the AND gate AND ₅ , and the AND gates AND ₈ and AND _{9 form} the signal S ₈ and the dot clock DOT-CLK1. ), The dot clock signal DOT-CLK2 is output through the OR gate OR ₂ .

Steady state ( = ψ), as shown in the waveform diagram shown in FIG. When the waveform is at the lower level, the output signals S ₁ , S ₂ , S ₄ and S _{5 of} the basic input signals A to D and the dot clock (DOT-CLK1) signal and gate (AND ₁ to AND ₄ ) are Regardless, when the output signals S ₃ and S ₆ of the flip-flop FF ₁ and FF ₂ and the signal S ₇ of the AND gate AND ₅ are low level, the dot clock DOT-CLK2 displays normal characters. Indicates.

Double width (DW) signal is high level (HIGH LEVEL: = 1), that is, in the double-sized character mode, the initialization CLEAR of the flip flops FF ₁ and FF ₂ is released and the output signal S ₃ of the flip flop FF _{1 is} shown in FIG. 3. As shown. High level (HiGH LEVEL) and the AND gate (AND ₂₎ the output signal (S ₂₎ and a flip-flop output signal (S ₃₎ is an AND gate (AND ₃₎ via an output signal (S ₄₎ of (FF ₁₎ is of As shown in FIG. 3 through the multiplexer (MUX1: 30), the terminal control (TC) signal is twice as large as the normal state.

Here, the dot clock (DOT-CLK2) signal has to change the terminal control signal from the lower level (TC = ψ to the higher level (DOT-CLK2 = 1).

Therefore, it is important to clear the initializing CLEAR of the flip-flop FF _{3 in the} DOT-CLK2 signal in the binary counter circuit. As shown in FIG. ₃ , the initialization of the flip flop FF ₃ is performed by the output signal S ₇ of the AND gate AND ₅ , and the dot clock DOT-CLK2 input signal S ₈ From the falling point (FALLING EDGE) of the dot clock (DOT-CLK1) to operate the binary count (COUNTER) circuit generates a dot clock (DOT-CLK2) signal of twice the size compared to the normal state.

In the above operation, the character clock (in the normal state and the double size state) The signal indicates the normal period, and the terminal control (TC) signal and the dot clock (DOT-CLK2) are changed into a waveform of 2 times size. Therefore, double width ( According to the signal, letters of normal size and double size can be output. As described above, when displaying the normal state and the double sized characters on the terminal display device, the CUSTOM IC is processed by using a logical binary count circuit without adding a hardware circuit. When manufacturing a terminal display device, the double width (DOUBLE-WIDTH) function can be added, so that the processing speed is not only increased but also highly functionalized.

Claims (1)

The column selector (A) which receives the clocks (CLOCK1, CLOCK2) as inputs and specifies the column selection, and the basic signal generator (B) which generates the basic signals (A ~ D) by inputting the dot clock (DOT-CLK1). In the logic circuit unit 10 and the AND gate composed of the AND gate (AND ₁ ~ AND ₃ ), the inverter (I ₁ ) and flip-flop (FF ₂ , FF ₃ ) to receive the basic signal (A ~ D) as an input aND and Iowa gate ₄ ~ aND ₅₎ and the inverter (I _2, I ₃₎ and a flip flop (FF _2, FF _{3) 2} binary coefficient (COUNTER) circuit 20, the aND gate (aND _6, aND ₇ consisting of a) ( OR ₁ ) consists of a multiplexer 30 composed of a multiplexer 30 composed of an AND gate (AND ₈ , AND ₉ ) and an oragate (OR ₂ ) configured to provide a double width ( The double-size character generation circuit in the terminal display device, characterized in that for displaying the normal size characters and double size characters on the screen according to the signal.