KR900002793B1 - Video pattern selecting circuit for crt display of picture and character - Google Patents

Abstract

The circuit using a gate array for high-integrating the circuit includes 4-bit registers (10,20) receiving colour data (GC1-GC3) and frame signal (DISF), EXOR gates (50,51) receiving invert signal (REV) of character colour and character colour data (CD1-CD3), an OR gate (53) receiving a picture selection signal (GS), OR gates (57-59) providing 3-bit signals (VS1-VS3) as video colour data to the CRT, a multiplexer (30) for 2-bit data output, and a multiplexer (40) for 1- bit data output. The outputs of the multiplexers are summed with the frame signal synchnoronised with the dot signal; then the video colour signal are provided through the OR gates (57-59).

Description

Picture and Character Video Pattern Selection Circuit of CRT Display

1 is a schematic diagram showing a circuit for generating video color data of a conventional CRT display.

2 is a drawing and character video pattern selection circuit diagram of the present invention.

3 is a signal waveform diagram input and output to the circuit of FIG.

* Explanation of symbols for main parts of the drawings

10,20: Register 30,40: Multiplexer

50-59: Logic Gate

The present invention relates to a circuit for outputting a video pattern selection new circuit of pictures and characters in an interface circuit of a CRT display.

In a typical CRT display, a circuit for selecting and outputting a color signal of a video pattern of pictures and characters is schematically shown in FIG.

In FIG. 1, the pattern generator and the picture character video pattern selector input the road clock CLK and the reset signal RESET, and the picture color data includes information indicating the color of the displayed picture among the signals output from the pattern generator. (GD ₁ -GD ₃ ) is inputted to the picture color data conversion unit and the picture data conversion unit, and the character color data (CD _1- CD ₃ ), which is information indicating the color of the displayed character, and information inverted and displayed in the color of the characters. A character color reversal signal REV and a screen display period signal DISP, which is information indicating a displayed picture and a screen display period of a character, are input to a picture character video pattern selection unit.

The picture color data conversion unit in the picture input color data (GD ₁ -GD ₃₎ for converting a color to a desired color by processing means of its own data (GD ₁ -GD ₃₎ to provide an output portion picture character video pattern selection In addition, the picture data recognition unit recognizes picture color data (GD ₁ -GD ₃ ) and outputs a picture selection signal (GS) for determining whether to output picture data by its own processing means to select a picture character video pattern. Provide wealth.

Accordingly, the picture character video pattern selection unit includes color data (GC ₁ -GC ₃ ), picture selection signal (GS), character color data (CD ₁ -CD ₃ ), character color inversion signal (REV), and screen display section signal ( Finally, the video color data is outputted.

In the above picture color data conversion unit and picture data recognition unit, although not shown in the drawing, a drawback that cannot be highly integrated is required because a pull-up resistor is required to eliminate tri-state due to integration. there was.

Accordingly, the present invention provides a high-density pictorial video pattern circuit of a CRT display by reconfiguring the pictorial video pattern selection unit with a gate array, thereby eliminating the pull-up conversion required by the pictorial color data conversion unit and the pictorial data recognition unit. There is a purpose.

Next, an embodiment according to the present invention will be described in detail with reference to FIGS. 2 and 3.

2 is a pictorial video pattern selection circuit of the present invention, and FIG. 3 is a waveform diagram of signals input and output to the pictorial video pattern selection circuit of the present invention.

In FIG. 2, the 4-bit registers 10 and 20 are synchronized by the dot clock CLK and cleared by the reset signal RESET. The 4-bit registers 10 are output from the picture color data converter. Inputted color data (GC ₁ -GC ₃ ) and the screen display interval signal (DISF) output from the pattern generator, and the other four-bit register 20 includes an exclusive orient (50-52) and an orient ( Input the output of 53).

In the exclusive OA gate 50-51, a character color inversion signal REV is input to one input terminal of each of the two input terminals, and character color data CD _{1 to} CD ₃ are input to the other input terminal, and each output signal is input. Is also input to the noah gate 54.

The output of the picture selection signal GS and the noar gate 54 are input to two input terminals of the ora gate 53.

The outputs of QA and QB among the 4-bit registers (Q4-QD) of the 4-bit register 10 are input to the input terminals Al and Bl of the multiplexer 30, and the output of the QC is input to the input terminal A of the multiplexer 40. The input of the QD is commonly inputted to the other input terminal of the NOA gate 55 and the ORA gate 56 for inputting the output terminal QD signal of the 4-bit register 20 in common, and at the same time, each OA gate ( 57-59) are commonly input.

The output terminals QA and QB of the 4-bit register 20 are input to the input terminals A2 and B2 of the multiplexer 30, and the outputs of the noar gate 55 and the oragate 56 are respectively multiplexer 30 ( It is commonly input to the input terminals XS1, 52 of 40, and the other input terminals of each of the orifices 57, 58, and 59 are connected to the two output terminals X0, X1 of the multiplexer 30 and the multiplexer 40. Output terminal (X) signals are input respectively.

In this way, the 3-bit signals VS1-VS3 outputted from the connected audio patterns 57-59 of the picture character video pattern selection unit are transmitted to the CRT display as video color data.

In FIG. 2, the output terminal signal of the noah gate 54 is input to the oragate 53 together with the picture selection signal GS output from the pattern generator as a signal indicating whether or not the character color data is displayed.

In this way, when the signal for determining whether or not the character display input to the oracle 53 and the signal for determining whether or not the picture display is X ₁ and X ₂ , respectively, it is possible to select a picture or a character to be displayed as shown in the following table.

TABLE 1

=(REV

D₁)+(REV

D₂)+(REV

D₃)의 논리식을 산출할 수 있다.X ₁ for determining whether the character is displayed is determined by the eye color inversion signal (REV) and the eye color data (CD _{1 to} CD ₃ ).

= (REV

D ₁ ) + (REV

D ₂ ) + (REV

D ₃ ) can be calculated.

Therefore, the color data GC _{1 to} GC ₃ output from the picture color data conversion unit and the screen display interval signal DISP output from the pattern generation unit are synchronized to the dot clock CLK in the 4-bit register 10. The character section signal output from the exclusive oragate 50-52 and the signal output from the oragate 53 are synchronized in the 4 bit register 20.

Subsequently, a selection operation between the picture section data and the text color data occurs by the 4-bit registers 10 and 20, wherein the selected signal is a function of the signal output from the oragate 53.

In this way, the signal selected and output from the multiplexers 30 and 40 is logically combined with the screen display section signal DISP synchronized with the dot clock to finally output video color data VS ₁ -VS _W.

이 되고, 두 번째 패턴에서는 그림선택신호(GS)가 하이레벨이므로 그림데이터가 선택되며, 세 번째 패턴에서는 A₃의 데이터가 "0"이므로 그림 데이터가 출력되며, 네 번째 패턴에서는 A₄의 데이터가"0"이 아니고 그림 선택신호가 로우레벨이므로 글자데이터가 선택되어야 하나 문자출력유무신호가 하이레벨이 되어 그림데이터가 선택된다.That is, referring to the waveform diagram of FIG. 3, in the first pattern of the character color data, since the data of A ₁ is not "0" and the picture selection signal GS is low level, the video color data VS _1- VS ₃ ) Is in the picture selection signal (GC ₁ -GC ₃ ).

In the second pattern, the picture data is selected because the picture selection signal GS is high level, and in the third pattern, picture data is output because the data of A ₃ is "0", and the data of A _{4 in} the fourth pattern. Since the character selection signal is low level and the picture selection signal is low level, the character data should be selected, but the character output presence signal becomes the high level so that the image data is selected.

As described above, according to the present invention, the gate array is used to form the pictogram video pattern circuit of the CRT display, thereby making it highly integrated, thereby improving reliability and reducing costs.

Claims (1)

In the interface circuit of the CRT display including a pattern generator, a picture color data converter, and a picture data recognizer, the color data (GC ₁ -GC ₃ ) of the picture color data converter and the screen display interval signal (DIS) of the pattern generator Exclusive OA gate (50-52) and Noa gate (54), to which the 4-bit register 10 for inputting (), the character color phase inversion signal (REV) of the pattern generator, and the character color data (CD _{1 to} CD ₃ ) are input. Logical expression

And a 4-bit register 20 for inputting the output of the oragate 53 and the output of the exclusive oracle 50-52 that are ORed together with the output according to the logic equation and the picture selection signal GS. Is connected to be synchronized by the dot clock CLK and cleared with the reset signal, and the outputs of the noar gate 55 and the ora gate 56 which commonly input the input / output of the 4-bit registers 10 and 20 in common. And a 2-bit multiplexer 30 for inputting each 2-bit output of the 4-bit registers 10 and 20, each of the 1-bit outputs of the 4-bit registers 10 and 20, and the noar gate 55 and the OR. The 1-bit output multiplexer 40 for inputting the output of the gate 56 is connected to an oragate 57-59 which inputs a signal to be output as a select output and inputs and outputs of the register 10 to other terminals in common. the bidet autumnal data from the Iowa gate _{(57-59) (VS 1 -VS 3} ) CRE picture display, characterized in that the output connection so that characters and video pattern selector.

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