KR100510457B1 - Method and circuit for generating system clock signals in lcd driver - Google Patents

Abstract

A method and circuit for generating a system clock signal in a liquid crystal drive device are disclosed. In the method of generating a system clock signal of a liquid crystal driving apparatus according to the present invention, the method of generating a first system clock signal in accordance with a master clock signal, (b) determining whether to generate a system clock signal further, and a system clock signal To generate more, (c) generating a p (where p> 1) system clock signal according to the first system clock signal, (d) determining whether to generate a system clock signal further, and a system clock signal In order to further generate P, the system generates the (p + 1) th system clock signal according to the p th system clock signal, and (f) and (f) determine whether to generate the system clock signal further. In order to generate more clock signals, step (g) of increasing the value of p and proceeding to step (e) is performed. It is possible to produce the system clock signal has the effect of significantly reducing the current consumption in comparison with the prior art.

Description

Method and circuit for generating system clock signals in LCD driver

The present invention relates to the generation of a system clock signal of a liquid crystal display device, and more particularly, to a method and a circuit for generating a system clock signal of a liquid crystal display device by a low frequency master clock signal.

In general, the power consumption of the liquid crystal drive increases with the master clock frequency used to drive the liquid crystal drive. In addition, various system clock signals necessary for driving the liquid crystal driving apparatus using the master clock signal may be generated.

Hereinafter, a conventional system clock signal generation method will be described with reference to the accompanying drawings.

1 (a) to 1 (f) are waveform diagrams for explaining a conventional system clock signal generation method, and FIG. 1 (a) shows a master clock signal MCK for driving a liquid crystal driving apparatus. FIG. 1B illustrates a controller clock signal CCK for the operation of the controller (not shown), FIG. 1C illustrates a first system clock signal SCK1, and FIG. ) Denotes the second system clock signal SCK2, FIG. 1E illustrates the third system clock signal SCK3, and FIG. 1F illustrates the fourth system clock signal SCK4.

1 (a) to 1 (f) are diagrams for explaining a case of generating four system clock signals using the master clock signal MCK. FIG. 1B illustrates a controller clock signal CCK required for the operation of a controller (not shown) and divides the master clock signal MCK into five divisions. In the first section 100, the first system clock signal SCK1 shown in FIG. 1C is generated in synchronization with the rising edge of the master clock signal MCK shown in FIG. In the second section 110, the second system clock signal SCK1 shown in FIG. 1D is generated in synchronization with the falling edge of the master clock signal MCK shown in FIG. 1A. do. In the third section 120, the third system clock signal SCK3 shown in FIG. 1E is generated in synchronization with the falling edge of the master clock signal MCK shown in FIG. In the fifth section 140, the fourth system clock signal SCK4 shown in FIG. 1F is generated in synchronization with the rising edge of the master clock signal MCK shown in FIG. do. In addition, the controller (not shown) transmits the first, second, third and fourth system clock signals SCK1, SCK2, SCK3 and SCK4 in the fifth section 130, which is one period of the controller clock signal CCK. The first, second, third and fourth system clock signals SCK1, SCK2, SCK3 and SCK4 are generated in the fifth section 130 so as to scan all of them.

In the conventional system clock signal generating method as described above, each of the first, second, third and fourth system clock signals is generated in synchronization with the rising or falling edge of the master clock signal MCK, so that the controller clock signal of one cycle is generated. Several cycles (five cycles) of the master clock signal MCK are required. That is, the master clock signal MCK of a higher frequency (5 times) than the control unit clock signal CCK is required, which causes the consumption current of the liquid crystal driving apparatus to increase.

An object of the present invention is to provide a method for generating a system clock signal of a liquid crystal driving apparatus for generating various system clock signals using a low frequency master clock signal.

Another object of the present invention is to provide a system clock signal generator of a liquid crystal driving apparatus for generating various system clock signals using a low frequency master clock signal.

In order to achieve the above object, the system clock signal generation method of the liquid crystal drive device according to the present invention comprises the step (a) of generating a first system clock signal according to the master clock signal, it is determined whether to further generate a system clock signal (b Step (c) of generating a p (where p> 1) system clock signal according to the first system clock signal, and determining whether to generate more system clock signals (d). Step (e) of generating a (p + 1) th system clock signal according to the pth system clock signal, determining (f) whether to generate more system clock signals, and In order to further generate the system clock signal in step (f), it is preferable that step (g) is performed to increase the value of p by one and proceed to step (e).

In order to achieve the above another problem, the system clock signal generation circuit of the liquid crystal drive apparatus according to the present invention is configured to generate a "low" or "high" logic level signal input to an input terminal in response to the first set signal and the master clock signal. A first flip-flop output as a first system clock signal and a first delay means for delaying the first system clock signal for a first predetermined time and for outputting the first system clock signal delayed for the first predetermined time as a first set signal; It is preferable.

Hereinafter, a method of generating a system clock signal of a liquid crystal driving apparatus according to the present invention will be described with reference to the accompanying drawings.

2 is a flowchart illustrating a method of generating a system clock signal of a liquid crystal driving apparatus according to the present invention, the method comprising generating a first system clock signal SCK1 according to a master clock signal MCK (step 600); In order to determine whether to generate more system clock signals, and to generate more system clock signals, generating the p-th system clock signal according to the first system clock signal SCK1 (operation 605 to 610), and further adding the system clock signal. And generating a system clock signal (steps 615 to 620) and generating a system clock signal according to the p system clock signal. In order to further generate a system clock signal, the value of p is increased by one and the process proceeds to step 620 (steps 630 to 640).

3A to 3D are waveform diagrams showing examples of system clock signals that may be generated by the method shown in FIG. 2, and FIG. 3A is a master clock signal MCK. 3 (b) shows the first system clock signal SCK1 generated in step 600 and FIG. 3 (c) shows the second system clock signal SCK2 generated in step 610. 3D illustrates the p-th system clock signal SCKp generated in operation 620.

Referring to FIGS. 2 and 3A-3D, a signal inverted to a "low" logic level according to the falling edge of the master clock signal MCK shown in FIG. And a first system clock signal SCK1 shown in FIG. 3 (b) is generated since it is delayed for a first predetermined time 300 and then set to a “high” logic level (step 600). After operation 600, it is determined whether to generate a system clock signal (operation 605). After the step 605, in order to generate the system clock signal, the signal is inverted to the "low" logic level according to the rising edge of the first system clock signal SCK1. The p-th system clock signal SCKp is generated because the logic level is set (operation 610). In this case, initially, p = 2, in step 610, as shown in the waveform diagram of FIG. 3C, during the second predetermined time 310 according to the rising edge of the first system clock signal SCK1, the " low " A second system clock signal SCK2 is generated which is set after generating the logic level signal. That is, the second system clock signal SCK2 may be generated using the first system clock signal SCK1 regardless of the master clock signal MCK. After operation 610, it is determined whether to generate a system clock signal (operation 615). After step 615, to generate the system clock signal, a signal inverted to a "low" logic level according to the rising edge of the p-th system clock signal SCKp is generated and delayed for a predetermined time (p + 1). Then, since the signal is set to the "high" logic level, a (p + 1) th system clock signal is generated (step 620). On the other hand, since it is assumed that p = 2 initially in operation 610, the third system clock signal SCK3 is generated in operation 620. That is, the third system clock signal SCK3 may be generated according to the rising edge of the second system clock signal SCK2 regardless of the master clock signal MCK. After operation 620, it is determined whether the system clock signal is further generated (operation 630). After operation 630, to further generate a system clock signal, the process proceeds to operation 620 by increasing the value of p by one (operation 640). That is, since initially p = 2, increasing the value of p by one in step 640 increases p = 3 to proceed to step 620 again.

That is, conventionally, since the system clock signals required by the liquid crystal driving apparatus are generated in response to every rising or falling edge of the master clock signal MCK, a master clock signal MCK having a high frequency is required. However, in the method of generating a system clock signal of the liquid crystal driving apparatus according to the present invention, when the first system clock signal SCK1 is generated according to the master clock signal MCK, the first system clock is independent of the master clock signal MCK. The second system clock signal SCK2 may be generated using the signal SCK1. In addition, the (p + 1) th system clock signal may be generated using the pth system clock signal. That is, since the necessary system clock signals can be generated using the system clock signals that have been generated regardless of the master clock signal MCK, various system clock signals required by the liquid crystal driving apparatus even as the master clock signal MCK having a low frequency can be generated. Can occur.

Hereinafter, a system clock signal generating circuit of a liquid crystal driving apparatus according to a system clock signal generating method of a liquid crystal driving apparatus according to the present invention will be described with reference to the accompanying drawings.

FIG. 4 is a circuit diagram illustrating an example of a system clock signal generation circuit of a liquid crystal driving apparatus according to the present invention, and includes a first system clock signal generator including a first flip-flop 200 and a first delay unit 210. And a second system clock signal generator 250 having a second flip-flop 230 and a second delay unit 240, a p-th flip-flop 260, and a p-th delay unit 270. The p-th system clock signal generator 280 is configured.

In order to explain the circuit shown in FIG. 4 with reference to FIGS. 3A to 3D, the first to pth flip-flops 200 to 260 illustrated in FIG. 4 may include input terminals IN1 to INp. Assume that you input a signal of "low" logic level. The first flip-flop 200 of the first system clock signal generator 220 transmits the signal of the "low" logic level input to the input terminal IN1 to the positive output terminal Q1 in response to the falling edge of the master clock signal MCK. Output At this time, the master clock signal MCK is the same frequency as the controller clock signal CCK for the operation of the controller (not shown) and has a low frequency. The first delay unit 210 delays the signal output from the positive output terminal Q1 of the first flip-flop 200 by a first predetermined time 300 to generate the first set signal S1 enabled at the falling edge. . That is, when a signal having a "low" logic level is input to the set signal input terminal S1 of the first flip-flop 200 after the first predetermined time 300 delay, the first flip-flop 200 is set to FIG. 3. The first system clock signal SCK1 shown in (b) is output to the output terminal OUT1. In addition, the first system clock signal inverted to the negative output terminal QB1 of the first flip-flop 200 ( ) Is output to the clock signal input terminal CK2 of the second flip-flop 230.

The second flip-flop 230 outputs a signal of the "low" logic level input to the input terminal IN2 to the positive output terminal Q2 in response to the falling edge of the first clock signal SCK1. The second delay unit 240 delays the signal output from the positive output terminal Q2 of the second flip-flop 230 for a second predetermined time 310 to generate a second set signal S2 enabled at the falling edge. . That is, when a signal having a "low" logic level is input to the set signal input terminal S2 of the second flip-flop 230 after the delay of the second predetermined time 310, the second flip-flop 230 is set to FIG. 3. The second system clock signal SCK2 shown in (c) is output to the output terminal OUT2. In addition, the second system clock signal inverted to the negative output terminal QB2 of the second flip-flop 230 ( ) Is output to the clock signal input terminal of the third flip-flop (not shown). As a result, the second system clock signal generator (eg, the first system clock signal SCK1) generated by the first system clock signal generator 220 is input to the clock signal input terminal CK2 of the second flip-flop 230. Since 250 is serially connected to the first system clock signal generator 220, the second system clock signal SCK2 is generated in response to the first system clock signal SCK1 regardless of the master clock signal MCK.

In the same manner as described above, the p-th flip-flop 260 outputs a "low" logic level signal input to the input terminal INp from the (p-1) flip-flop (not shown). Outputs to the constant output terminal Qp in response to the falling edge of the system clock signal. The p-th delay unit 270 delays the signal output from the positive output terminal Qp of the p-th flip-flop 260 by the p predetermined time 320 to generate the p-th set signal Sp, which is enabled at the falling edge. . That is, when a signal of "low" logic level is input to the set signal input terminal Sp of the p-th flip-flop 260 after the p-th predetermined time 320 delay, the p-th flip-flop 260 is set to FIG. 3. The p-th system clock signal SCKp shown in (d) is outputted to the output terminal OUTp. As a result, the p-th system clock signal generated by the (p-1) th system clock signal generator (not shown) is input to the clock signal input terminal CKp of the p-th flip-flop 260. Since the system clock signal generator 280 is connected in series with the (p-1) system clock signal generator (not shown), the system clock signal generator 280 may be connected in response to the (p-1) system clock signal regardless of the master clock signal MCK. The p system clock signal SCKp is generated. As a result, since the first to p th system clock signal generators 220 to 280 are connected in series, the second to p th system clock signals SCK2 to SCKp may be generated regardless of the master clock signal MCK. .

As described above, the method and circuit for generating the system clock signal of the liquid crystal driving apparatus according to the present invention can generate various system clock signals required by the liquid crystal driving apparatus using a low frequency master clock signal. There is an effect that can be significantly reduced.

1A to 1F are waveform diagrams for explaining a conventional system clock signal generation method.

2 is a flowchart illustrating a system clock signal generation method of a liquid crystal drive according to the present invention.

3A to 3D are waveform diagrams showing examples of system clock signals that may be generated by the method shown in FIG.

4 is a circuit diagram of an exemplary embodiment for explaining a system clock signal generation circuit of a liquid crystal driving apparatus according to the present invention.

Claims (3)

(a) receiving a master clock signal, delaying a signal generated in response to a falling edge of the master clock signal by a predetermined time, and generating a first system clock signal having a pulse duration during the delay time; (b) determining whether to generate a system clock signal further; (c) To further generate the system clock signal, receive the first system clock signal, delay the signal generated in response to the falling edge of the first system clock signal for the predetermined time, and pulse duration for the delay time. Generating a p (where p > 1 and p is a natural number) system clock signal having < RTI ID = 0.0 > (d) determining whether to generate the system clock signal further; (e) further generating the system clock signal, receiving the p-th system clock signal, delaying the signal generated in response to the falling edge of the p-th system clock signal for the predetermined time, and performing a pulse duration during the delay time. Generating a (p + 1) system clock signal having a; (f) determining whether to generate the system clock signal further; And (g) In order to further generate the system clock signal in the step (f), the method of generating a system clock signal of the liquid crystal drive device comprising increasing the value of p by one and proceeding to the step (e). . In the system clock generator of the liquid crystal drive device, A master clock signal is input to an input terminal and a clock terminal, and a signal having a “low” or “high” logic level is input to a set terminal, and a first low level signal is input to a logic low level in response to a falling edge of the master clock signal. A first flip-flop for outputting a first system clock signal of an output terminal and setting the first system clock signal to a logic high level in response to the first set signal; First delay means for delaying the first system clock signal for a first predetermined time and outputting the first system clock signal for delayed first predetermined time as the first set signal; The first system clock signal is input to an input terminal, the inversion signal of the first system clock signal is input to a clock terminal, and the second set signal is input to a signal having a low or high logic level to a set terminal. Outputting a second system clock signal having a logic low level to an output terminal in response to a falling edge of the inverted first system clock signal and bringing the second system clock signal to a logic high level in response to the second set signal; Setting a second flip-flop; And A first delay means for delaying said second system clock signal for a second predetermined time and for outputting said second system clock signal delayed for said second predetermined time as said second set signal; Circuit. The system clock signal generator of claim 2, further comprising p system clock signal generators in series, wherein 3 ≦ p and p is a natural number. Inputting the (p-1) system clock signal to an input terminal, an inverting signal of the (p-1) system clock signal to a clock terminal, and having a low or high logic level as a set terminal; Inputs a signal to a p set signal, outputs a logic low level p system clock signal to an output terminal in response to a falling edge of the inverted (p-1) system clock signal and responds to the p set signal A p-th flip-flop to set the p-th system clock signal to a logic high level; And And p-th delay means for delaying the p-th system clock signal by a p-th predetermined time and outputting the p-th system clock signal delayed by the p-th predetermined time as the p-th set signal. System clock signal generation circuit.