JP2001223567A - Noise removing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of elements in a noise removing circuit. SOLUTION: An input signal is applied to the respective data terminals D1 and D2 of a first delay flip flop 51 and second delay flip flop 52. A clock CLK is applied to the first delay flip flop 51 and an inverted clock *CLK is applied to the second delay flip flop 52. An AND gate 54 conducts the AND operation of the output Q1 of the first delay flip flop 51 and the output Q2 of the second delay flip flop 52. An AND gate 55 conducts the AND operation of the inverted output *Q1 of the first delay flip flop 51 and the inverted output *Q2 of the second delay flip flop 52. The output A of the AND gate 54 and the output B of the AND gate 55 are inputted to an RS flip flop 56.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise elimination circuit, and more particularly to an FG (Frequenc
y Generator) related to a noise removing circuit for removing a short time scale noise pulse superimposed on a signal.

[0002]

2. Description of the Related Art In a motor speed control circuit, a rotation speed of a motor is determined by an FG signal generated in synchronization with the rotation of the motor, and a feedback command for instructing the drive circuit of the motor to accelerate or decelerate based on the determination result. Has a loop.

[0003] Here, the FG signal is easily affected by external noise and noise generated by rotation of the motor due to the high impedance of the source. Therefore, in order to reduce the influence of such noise, a Schmitt amplifier having a predetermined hysteresis width is used. However, the superimposed noise exceeding the hysteresis width of the Schmitt amplifier cannot be completely removed. For example, an L level noise pulse appears during the output of the Schmitt amplifier which must be at the H level. Then, the cycle of the square wave of the Schmitt amplifier becomes shorter than the cycle of the original FG signal, and it is determined that the rotation speed of the motor is higher than the actual one, and there is a possibility that the speed control may not be performed accurately.

[0004] The noise elimination circuit is for eliminating a noise pulse appearing at the output of the Schmitt amplifier. FIG. 6 is a circuit diagram showing a configuration of a conventional noise elimination circuit. FIG. 7 is a timing chart for explaining the basic operation of the noise removal circuit.

Hereinafter, a conventional noise elimination circuit will be described with reference to FIGS. 6 and 7. FIG. A conventional noise elimination circuit is a first delay flip-flop (DFF) connected in series.
It includes groups 40-1 and 40-2, second delay flip-flop (DFF) groups 42-1 and 42-2, and AND gates (logical AND circuits) 44 and 46. The output of the Schmitt amplifier is applied to the data terminal (D1) of the first delay flip-flop 40-1. Then, the AND gate 46 becomes the output OUT of the noise removal circuit.

Next, the operation of the noise elimination circuit will be briefly described. In FIG. 7, it is assumed that the output of the Schmitt amplifier shown in FIG. 7B includes noise pulses 60 and 62 having a shorter time width than the period of the FG signal. This noise pulse is latched by the delay flip-flop 40-1 at the falling timing of the clock CLK. The time width of the pulses 70 and 72 appearing at the output Q1 of the delay flip-flop 40-1 is the clock period τ.

The second stage delay flip-flop 40
-2 outputs pulses 80 and 82 obtained by delaying the pulses 70 and 72 by the time τ. Therefore, the AND gate 44 performs a logical product operation of the outputs Q1 and Q2, thereby generating a noise pulse 60 generated during a period that should be at the L level.
62 can be eliminated. On the other hand, AND gate 46
Are the inverted outputs -Q1 ', -Q of the second delay flip-flop.
By calculating the logical product of 2 ', it is possible to remove a noise pulse generated during a period that should be at the H level.

The above-described noise elimination circuit is described in, for example, Japanese Patent Application Laid-Open No. H11-252962.

[0009]

However, as described above, the conventional noise elimination circuit requires four stages of delay flip-flops, and has a drawback that the number of elements is large.

Accordingly, an object of the present invention is to provide a noise elimination circuit capable of eliminating a noise pulse with a smaller number of elements.

[0011]

A noise elimination circuit according to the present invention comprises a first delay flip-flop in which an input signal including a noise pulse is applied to an input terminal and a clock is applied to a clock terminal; A first logical product of performing a logical product operation of a second delay flop flop to which an input signal including the input signal is applied and an inverted clock of the clock applied to a clock terminal, and outputs of the first and second delay flip-flops A circuit, a second AND circuit for performing an AND operation of the inverted outputs of the first and second delay flip-flops, and an RS flip-flop to which the outputs of the first and second AND circuits are applied. In addition, a signal from which a noise pulse has been removed is output from an RS flip-flop.

[0012]

FIG. 1 is a block diagram showing an embodiment of the present invention.
This will be described with reference to FIGS. FIG. 1 is a circuit diagram of a noise removing circuit according to an embodiment of the present invention. Input terminal I
An input signal including a noise pulse is applied to N. The input signal is subjected to waveform shaping by the waveform shaping circuit 50 from the two inverters, and then the data terminals D1 and D2 of the first delay flip-flop 51 and the second delay flip-flop 52.
Are applied in parallel. The clock CLK is applied to the clock terminal CL1 of the first delay flip-flop 51, and the inverted clock * CLK inverted by the inverter 52 is applied to the clock terminal CL2 of the second delay flip-flop 52.

Reference numeral 54 denotes an output Q1 of the first delay flip-flop 51 and an output Q2 of the second delay flip-flop 52.
AND gate which performs a logical product operation with. Also, 5
5 is an inverted output of the first delay flip-flop 51 * Q1
And an AND gate for performing an AND operation on the inverted output * Q2 of the second delay flip-flop 52. The output A of the AND gate 54 and the output B of the AND gate 55 are input to the RS flip-flop 56 via the respective inverters.
The output of the noise removal circuit is obtained from the RS flip-flop 56.

FIG. 2 is a timing chart for explaining the basic operation of the noise elimination circuit having the above configuration. It is assumed that the signal applied to the input terminal IN includes noise pulses 65 and 66 having a time width shorter than a half cycle (τ / 2) of the clock CLK as shown in FIG. This noise pulse 6
5, 66 are latched by the first delay flip-flop 51 at the falling timing of the clock CLK.
The time width of the pulses 75 and 76 appearing at the output Q1 of the first delay flip-flop 51 is the clock period τ. That is, the noise pulses 65 and 66 are normalized by being shifted by a half cycle of the clock CLK.

On the other hand, the first delay flip-flop 52 to which the inverted clock * CLK is applied latches the input signal at the falling timing of the clock CLK. Therefore, the noise pulses 65 and 66 have been removed from the output Q2.

Therefore, the outputs A and AN of the AND gate 54 are
The output B of the D gate 55 has a waveform as shown in FIGS. Then, when these outputs A and B are inverted and input to the RS-flip-flop 56, a signal from which noise pulses have been removed as shown in FIG. That is, according to the noise elimination circuit having the above configuration, a half cycle (τ /
2) Noise pulses having a shorter time width can be removed.

FIG. 3 is a circuit diagram showing a noise elimination circuit according to another embodiment. This noise removal circuit is realized by a bipolar device. After an input signal including a noise pulse is applied to the input terminal IN and the waveform is shaped by the waveform shaping circuit 101 from the two inverters, the data terminals D1 and D2 of the first delay flip-flop 103 and the second delay flip-flop 104 Are applied in parallel. The clock CLK is applied to the clock terminal CL1 of the first delay flip-flop 103, and the clock terminal CL2 of the second delay flip-flop 103 is
Inverted clock * C inverted by inverter 105
LK is applied.

The inverter 102 constituting the waveform shaping circuit 101 is configured as shown in FIG. 4 using the IIL technology. That is, the current source 110 and the NPN transistor T
r1 and Tr2, and the collectors C1 and C2 are output. Thereby, the data terminal D of the flip-flop is
1, the same input signal is applied to D2.

The output Q1 and the inverted output * Q1 of the first flip-flop 103 are connected to the second flip-flop 10
4 is directly connected to the output Q2 and the inverted output * Q2. That is, the wired and method is used. Also in the RS flip-flop 106, the inverter 107
The circuit shown in FIG. The operation of this noise elimination circuit is the same as the operation of the noise elimination circuit shown in FIG.

Next, an example in which the noise elimination circuit having the above configuration is applied to a motor speed control circuit will be described. FIG. 5 is a block diagram of the motor speed control circuit. A hall output waveform is obtained by the rotation of the motor 2, and these are amplified by the hall amplifier 4 and then shaped by the hall logic circuit 6. The drive circuit 8 includes a Hall logic circuit 6
A drive signal is generated based on the output of the motor 2 to rotate the motor 2. This loop is the drive system of the motor 2.

The speed control system outputs F
Speed control is performed based on the G signal. The FG signal is supplied to the FG amplifier 20, the Schmitt amplifier 22, the noise removal circuit 16
Is converted into a square wave having a period corresponding to the FG signal. The noise elimination circuit of the present invention is applied to the noise elimination circuit 16.

The comparison circuit 18 compares the length of the square wave included in the predetermined cycle with a reference value, and determines whether the rotation speed of the motor is high or low based on the comparison. The comparison circuit 18 responds to the case where the speed is determined to be fast and the case where the speed is determined to be slow, respectively. An acceleration signal (negative pulse) for decelerating to a number is output. These acceleration and deceleration signals are
The signal is integrated by the integration amplifier 24 and fed back to the drive circuit 8.

The frequency dividing circuit 12 divides the frequency of the oscillation clock output from the oscillation circuit 10 and supplies it as the clock CLK of the noise removing circuit 16. The predetermined period in the comparison circuit 18 is determined by a reference signal generated by the frequency dividing circuit 14 further dividing the output of the frequency dividing circuit 12.

When the FG amplifier rises to the threshold voltage which is the upper limit level of the hysteresis width, the Schmitt amplifier 22 changes its output to the H level, while the FG amplifier shifts to the threshold voltage which is the lower limit level of the hysteresis width. Falls, the output is transited to the L level. As described above, by performing the state transition at different thresholds, the Schmitt amplifier 22 avoids the influence of the superimposed noise pulse having an amplitude within the hysteresis width.

However, the FG signal is transmitted to the Schmidt amplifier 22
When a noise having a larger amplitude than the hysteresis width of the threshold is superimposed at a value near the threshold of, the signal voltage crosses the upper or lower threshold voltage due to the noise, and the time width shorter than the FG signal Is generated. As a result, the length of the square wave output from the Schmitt amplifier 22 becomes shorter than the length of the period of the FG signal, the rotation speed of the motor 2 is determined to be higher than the actual speed, and the speed control may not be performed accurately. .

Therefore, the noise removal circuit 16 of the present invention
A noise pulse which mainly exceeds the hysteresis width of the Schmitt amplifier 22 and cannot be removed by the Schmitt amplifier 22 is removed, and the motor speed control is made accurate. In addition, since the noise elimination circuit of the present invention has a small number of elements,
By applying the present invention to a motor speed control circuit, it is possible to contribute to reduction in the number of elements in the entire circuit and cost.

[0027]

As described above, according to the present invention, it is possible to remove a noise pulse having a small time width and to form a noise removing circuit with a smaller number of elements.

In particular, by applying the present invention to a motor speed control circuit, a noise pulse exceeding the threshold of the Schmitt circuit can be effectively removed, and the speed of the motor can be accurately controlled.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a noise removing circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart illustrating an operation of the noise removal circuit according to the embodiment of the present invention.

FIG. 3 is a circuit diagram showing a noise removing circuit according to another embodiment of the present invention.

FIG. 4 is a circuit diagram of an inverter.

FIG. 5 is a block diagram of a motor speed control circuit.

FIG. 6 is a circuit diagram of a noise removal circuit according to a conventional example.

FIG. 7 is a timing chart for explaining the operation of the noise removal circuit according to the conventional example.

[Explanation of symbols]

 Reference Signs List 50 waveform shaping circuit 51 first delay flip-flop 52 second delay flip-flop 53 inverter 54 AND gate 55 AND gate 56 RS flip-flop

Claims (1)

[Claims] A first delay flip-flop to which an input signal including a noise pulse is applied to an input terminal and a clock is applied to a clock terminal; and a first delay flip-flop to which an input signal including the noise pulse is applied and a clock terminal is applied. A first AND circuit that performs a logical AND operation on a second delay flop to which the inverted clock of the clock is applied, and an output of the first and second delay flip-flops; A second AND circuit for performing an AND operation on the inverted output of the delay flip-flop; and RS to which the outputs of the first and second AND circuits are applied.
And a flip-flop, wherein a signal from which a noise pulse has been removed is output from the RS flip-flop.