JP2998899B2 - Pulse generator - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a pulse generator for obtaining a pulse width modulated output pulse signal for controlling a discharge lamp lighting device.

[Prior Art] Conventionally, this kind of pulse generator for obtaining a pulse width modulated output pulse signal for controlling a discharge lamp lighting circuit is formed by using a microprocessor, and is formed by software by a program. Predetermined on / off duty (predetermined “H” section, “L” section) by internal counter
Was obtained.

[Problems to be Solved by the Invention] However, in the above-described conventional example, the setting accuracy of the on / off duty is regulated by the machine cycle of the microprocessor, and the machine cycle is generally several μsec. There is a problem that the on / off duty cannot be set with an accuracy of less than μsec, and there is a problem when the discharge lamp is used as a frequency generating circuit of a discharge lamp lighting device for lighting a high frequency.

The present invention has been made in view of the above points, and an object of the present invention is to provide a pulse generator capable of increasing the setting accuracy of on / off duty.

[Means for Solving the Problems] A pulse generating apparatus according to the present invention includes a data latch circuit for latching "H" section setting data and "L" section setting data of an output pulse signal, and counting a clock of a fixed cycle, and A pulse which comprises a presettable counter circuit in which both section setting data are alternately set, and a toggle flip-flop circuit which uses a ripple carry signal from the counter circuit as a trigger clock, and independently changes both section setting data. By providing the width control means, a pulse width modulated output pulse signal is obtained from the toggle flip-flop circuit.

[Operation] The present invention is configured as described above. The "H" section setting data and the "L" section setting data of the output pulse signal are latched in the data latch circuit, and a clock of a fixed cycle is counted. A ripple carry signal from a presettable counter circuit in which section setting data is alternately set is used as a trigger clock of a toggle flip-flop circuit,
Since the pulse width modulated output pulse signal is obtained from the toggle flip-flop circuit, the microprocessor uses an internal counter to set the "H" section and "L" section as in the conventional microprocessor. The setting accuracy of ON / OFF duty is not regulated in the machine cycle of, and the “H” section and “L” section can be set arbitrarily regardless of the machine cycle.
The setting accuracy of the off-duty can be increased.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 to 7.

In this embodiment, as shown in FIG. 1, given from a microprocessor (not shown) to the input terminal IN ₁ ~IN ₁₂ "H"
The output pulse signal sOUT output from the counter / output circuit 5 according to the section setting data and the “L” section setting data.
The “H” section and the “L” section are set.
Here, the “H” section setting data and the “L” section setting data are 12-bit data sDT _{1 to} sDT ₁₂ provided from the microprocessor to the input terminals IN _{1 to} IN ₁₂ , and the “H” section setting data And the "L" section setting data are sequentially supplied from the microprocessor, whereby the on-duty, off-duty, and cycle of the output pulse signal sOUT are set.
The “H” section setting data and the “L” section setting data are latched by the data latch circuit 1 in accordance with a timing signal (eg, latch signals sLATCH _A and sLATCH _B described later) output from the timing control circuit 4. In the counter / output circuit 5,
The "H" section setting data and the "L" section setting data latched by the data latch circuit 1 are alternately set in the presettable counter circuit 2 (see FIG. 4), and supplied to the terminal CLK from the microprocessor. An output pulse signal sOUT which becomes “H” during a period in which the clock signal sCLK of a fixed cycle is counted by the number of “H” section setting data and becomes “L” during a period in which the number of “L” section setting data is counted is output.

That is, in this embodiment, the pulse width modulated output pulse signal sOUT is obtained by providing the pulse width control means (not shown) for independently changing the “H” section setting data and the “L” section setting data. It is like that. Here, the pulse width control means is formed by the microprocessor, and “H” section setting data and “L” section setting data output from the microprocessor are:
As described above, the data is input to the input terminals IN _{1 to} IN ₁₂ of the data latch circuit 1 shown in FIG. 1 and latched by the data latch circuit 1 by the timing signal output from the timing control circuit 4. I have.

 Hereinafter, each circuit will be specifically described.

The data latch circuit 1 is formed by a primary buffer 1a and a secondary buffer 1b as shown in FIG. 1. The primary buffer 1a shown in FIG. 2 and the secondary buffer 1b shown in FIG. And a three-state buffer (hereinafter, referred to as a T buffer) TBUF. In primary buffer 1a shown in FIGS. 1 and 2, at the time of rise of the section data set signal sHL inputted to the terminal HL from the microprocessor, the 12-bit input via the input terminal IN ₁ to IN ₁₂ data sDT ₁ ~sDT _12, the latch signal SLATCH _a is a timing signal input to the terminal LTCK ₁ from the timing control circuit 4, the left column of FIG. 2 as a setting above the "H" section data sDA ₁ ~sDA ₁₂ Is latched in the flip-flop FF. At the time of falling of the section data set signal sHL input from the microprocessor to the terminal HL, the input terminals IN _{1 to} IN ₁
A latch signal SLATCH _B is a timing signal input 12-bit data sDT ₁ ~sDT ₁₂ inputted through the ₁₂ from the timing control circuit 4 to terminal LTCK _2, the above "L" section setting data sdb ₁ ~ The sDB ₁₂ is latched in the flip-flop FF in the right column of FIG.

Figure 1 and the third secondary buffer 1b shown in FIG., The primary buffer 1a latched in "H" section setting data SDA ₁ to SD
A ₁₂ and “L” section setting data sDB _{1 to} sDB ₁₂ are respectively connected to terminals DA _{1 to} DA of the primary buffer 1 a and the secondary buffer 1 b by the latch signal sLTCH output from the terminal LTCK of the counter / output circuit 5. capturing through _12, DB _{1 ~DB 12.} The “H” section setting data sDA _{1 to} sDA ₁₂ are taken into the flip-flop FF in the left example of FIG. “L” section setting data sDB _{1 to} sDB
₁₂ is taken into the flip-flop FF in the right column of FIG. Also, the “H” section setting data sDA _{1 is} set by the enable signals sEN _A and sEN _B from the terminals EN _A and EN _B of the toggle flip-flop circuit 3 (see FIG. 4) of the counter / output circuit 5.
～SDA ₁₂ and "L" is output from the section setting data sDB ₁ ~sDB ₁₂ while selected and an output terminal OUT ₁ to OUT ₁₂ of the. In the secondary buffer 1b, as shown in FIG. 3, the half clock control signal sHLE from the microprocessor is also temporarily latched by the latch signal sLTCH and output as the half clock control signal sHALF.

As shown in FIG. 4, the counter / output circuit 5 sets the "H" both section setting data and the "L" section setting data alternately, and outputs a clock of a fixed period inputted from the microprocessor to the CLK terminal. a presettable counter circuit 2 counts the signal SCLK, a half clock control circuit 6 for outputting a signal srcY 'described later by using a ripple carry signal srcY ₁ from the counter circuit 2,
A toggle flip-flop circuit 3 using the signal sRCY 'as a trigger clock. Counter / output circuit 5, the preset data sD ₁ to SD ₁₂ output from the output terminal OUT ₁ to OUT ₁₂ of the secondary buffer 1b is set to the input terminal IN ₁ to IN _12.

The counter circuit 2 is a 12-bit counter circuit using _three 4-bit presettable counters CO _{1 to} CO ₃ . The ripple carry signal sRCY ₁ from the presettable counter CO ₃ on the upper side of the counter circuit 2 is input to the half clock control circuit 6, and the trigger clock signal sRCY ′ output from the half clock control circuit 6 is input to the toggle flip-flop circuit 3. Is to be entered.
The toggle flip-flop circuit 3 outputs the above-described output pulse signal sOUT from the output terminal OUT when the trigger clock signal sRCY 'is input, and at the same time, an enable signal for reading preset data from the secondary buffer 1b of the data latch circuit 1. sEN _A and sEN _B are output from terminals EN _A and EN _B. The enable signal sEN _A has an inverted waveform of the output pulse signal sOUT, and the enable signal sEN _B
Has the same waveform as the output pulse signal sOUT. Here, the half clock control circuit 6 includes a set type data flip-flop (hereinafter, referred to as a D flip-flop) FF ₁₁ , a reset type D flip-flop FF ₁₂ , FF ₁₃ , NAND elements NA ₁₁ , NA ₁₂ , and a NOR element NR. ₁₁ and the inverter INV ₁₁ and INV
₁₂ , INV ₁₃ , INV ₁₄ , and INV ₁₅ are used to shift the rising edge of the ripple carry signal sRCY _{1 to} the right by a half clock when the half clock control signal sHALF from the secondary buffer 1 b is “H”. And enables control of the “H” section and the “L” section with the accuracy of a half clock of the clock signal sCLK output from the microprocessor. Note that the half clock control circuit 6 uses the trigger clock signal sR
It also outputs a ripple carry signal sRCY obtained by inverting CY '.

The timing control circuit 4 shown in FIG. 1 includes a latch control circuit 4a for generating the latch signals sLATCH, sLATCH _A and sLATCH _B as shown in FIG. 5, and a clear signal sCLEAR,
Load signal sload, are formed by the counter control circuit 4b shown in FIG. 6 for generating a latch signal sLTCH _1, a clock signal sCL outputted from the microprocessor
A predetermined timing signal is output based on K, the start signal sSTART, the section data set signal sHL, and the latch signals sLTCH and sLATCH to control the operation timing of each circuit.

In the embodiment, as shown in FIG. 1, a two-phase clock generation circuit 7 for generating two-phase clock signals sOUT ₁ and sOUT ₂ based on the output pulse signal sOUT output from the counter / output circuit 5, The output pulse signal sOUT described above is output as an output signal for controlling the switching transistor of the light lighting device 10, or the two-phase clock signals sOUT ₁ and sO are output.
An output switching circuit 8 for switching whether to output UT ₂ by a switching signal sSE / HB is provided, and is a single-ended type (1 right inverter type in which a switching transistor is controlled by an output pulse signal sOUT) or a half-bridge type ( A two-phase clock signal sOUT ₁ , sOUT ₂ is used to obtain a switching control signal of a discharge lamp lighting device 10 of a two-inverter type in which a pair of switching transistors connected in series is controlled.

Here, as shown in FIG. 7, the two-phase clock generation circuit 7 generates a clock signal output from the microprocessor.
A presettable counter circuit 7a that counts sCLK via a terminal CLK and sets a non-overlapping section (a section where the two-phase clock signals sOUT ₁ and sOUT ₂ are both at a low level).
And a gate control circuit 7b for controlling the gate circuit 7c based on the ripple carry signal sRCY ₂ ′ output from the presettable counter circuit 7a, and the terminal set by an 8-bit setting switch to the presettable counter circuit 7a. so that the non-overlapping interval and outputs the 2-phase clock signal sOUT ₁ ~sOUT ₂ which is set on the basis of the non-overlap interval setting data sHB ₁ ~sHB ₈ inputted through the HB ₁ ~HB ₈ .

Hereinafter, the operation of the embodiment will be described with reference to time charts shown in FIGS. FIG. 8 is a waveform diagram showing the basic operation of this embodiment. First, when the start signal sSTART output from the microprocessor rises, a system reset is performed. Then, after the data sDT ₁ ~sDT ₁₂ of 12 bits corresponding to the setting above "H" section data sDA ₁ ~sDA ₁₂ is input from the microprocessor, section data set signal from the microprocessor sH
When L rises, one pulse of the latch signal sLATCH _A is output from the latch control circuit 4a via the terminal LOK ₁ and input to the terminal LTCK ₁ of the primary buffer 1a of the data latch circuit 1 and
"H" section setting data sDA ₁ ~sDA ₁₂ is latched to the next buffer 1a. Next, "L" after the section setting data sdb ₁ corresponding to ~sDB _{12 12-bit} data sDT ₁ ~sDT ₁₂ is input from the microprocessor, pin from the latch control circuit 4a at the fall of the section data set signal sHL One pulse of the latch signal sLATCH _B is output via LOK ₂ and input to the terminal LTCK ₂ of the primary buffer 1a of the data latch circuit 1, and the “L” section setting data sDB _{1 to} sDB ₁₂ are latched in the primary buffer 1a. You.

Next, the clear signal sCLEAR output from the terminal CLP of the counter control circuit 4b of the timing control circuit 4 becomes “L”, and the latch signal sL is output from the terminal LTCK of the counter / output circuit 5.
When one pulse of TCH is output and the latch signal sLTCH is input to the terminal LTCK of the secondary buffer 1b, the data of both sections is set.
sDA _{1 to} sDA ₁₂ and sDB _{1 to} sDB ₁₂ are latched in the secondary buffer 1 b of the data latch circuit 1. At this time, since the counter / enable signal SEN _A output from the toggle flip-flop circuit 3 of the output circuit 5 is in the "H", "H" section setting data from the secondary buffer 1b sDA ₁ ~sDA ₁₂ to read When a load signal sLOAD for setting preset data is output from the terminal LD of the counter control circuit 4b to the counter circuit 2 of the counter / output circuit 5 (see FIG. 4), an "H" section is set in the counter circuit 2. data sDA ₁ ~sDA ₁₂ is set, the count of the clock signal sCLK from the microprocessor is started. Then, when the output terminal Q _A to Q _D of the fourth each presettable counter CO ₁ to CO ₃ counter circuit 2 shown in FIG respectively becomes all "H", the ripple carry signal sRCY from presettable counter CO _{3 1} is output,
This ripple carry signal srcY _1, the enable signal SEN _B is output from the terminal EN _B become "H", the will be "H" output pulse signal sOUT outputted simultaneously from the terminal OUT of the counter / output circuit 5. Then, "L" section setting data
When sDB _{1 to} sDB ₁₂ are preset in the counter circuit 2 and start counting the clock signal sCLK from the microprocessor, when the ripple carry signal sRCY ₁ is obtained,
Output pulse signal sOUT becomes "L" with becomes the enable signal sEN _A "H", so that the above-described operation is repeated. Thus, both the section setting data sDA ₁ ~sDA _12, s
The “H” section and “L” section of the output pulse signal sOUT can be set arbitrarily (within 12 bits) based on DB _{1 to} sDB ₁₂ ,
ON and OFF duty can be set.
To change the on / off duty, set the “H” section setting data sDA _{1 to} sDA ₁₂ , set the section data set signal sHL to “H”, and set the “L” section setting data sDB _{1 to} s
After setting DB ₁₂ , set the section data set signal sHL to “L”.
You can do it. Also, the output terminals OUT ₁ to OUT ₁ of the secondary buffer 1b
The preset data sD _{1 to} sD ₁₂ output from OUT ₁₂ are switched by the enable signals sEN _A and sEN _B as described above.

For example, as shown in FIG.
"H" to set the "H" section of the output pulse signal sOUT output from 161 pulses and the "L" section to 164 pulses
8 bit interval setting data sDA ₁ ~sDA ₁₂ and the sixth bit is set to "1", "L" section setting data sDB ₁ ~sDB ₁₂
The 8th, 6th, 2nd, and 1st bits of "1" may be set to "1". In this case, the cycle of the output pulse signal sOUT is 325 pulses of the clock signal sCLK, and if the frequency of the clock signal sCLK output from the microprocessor is 16 MHz (62.5 nsec), it is 20.2 μsec. The frequency is 49.2kHz. Also, the width of the “H” section or “L” section of the output pulse signal sOUT is set to 1
If the width is widened by the pulse (62.5 nsec), the cycle becomes 326 pulses of the clock signal sCLK, and the frequency becomes 49.1 kHz. Therefore, in the embodiment, the "H" section or "L" section of the output pulse signal sOUT can be set at intervals of 62.5 nsec, and the frequency can be controlled at intervals of 0.1 kHz. This setting accuracy is based on the conventional microprocessor. This setting accuracy cannot be achieved with a pulse generator using a soft internal counter, and when used as a switching control signal of the discharge lamp lighting device 10, fine lighting control can be performed. Note that it goes without saying that the setting accuracy can be further increased by increasing the frequency of the clock signal sCLK counted by the counter circuit 2 of the counter / output circuit 5.

Next, the operation of the half clock control circuit 6 will be described with reference to FIG.

Incidentally, since the D flip-flop FF ₁₁ is set types as described above, when the system reset, output the output terminal Q is indefinite, when the "H" to the set terminal S is inputted, from an output terminal Q "H" is output, and thereafter, the input ("H" or "L") applied to the input terminal D is output from the output terminal Q in synchronization with the rise of the clock signal applied to the input terminal T (FIG. Not shown).

On the other hand, since the D flip-flops FF ₁₂ and FF ₁₃ and the D flip-flop FF ₁₄ of the toggle flip-flop circuit 3 are reset types, at the time of the system reset,
Although the output of the output terminal Q is undefined, when “H” is input to the reset terminal R, “L” is output from the output terminal Q, and thereafter, the input (“H”) applied to the input terminal D is applied. Alternatively, “L”) is output from the output terminal Q in synchronization with the rise of the clock signal applied to the input terminal T (not shown). Further, the ripple carry signal srcY ₁ inputted from the counter circuit 2 has a signal synchronized with the rising edge of the clock signal SCLK.

Now, the half clock control signal sHLE output from the microprocessor (that is, the data latch circuit 1)
The half clock control signal (sHALF) output from the
In the case of the output of the NAND element NA ₁₁ becomes "H". Accordingly, since the D flip-flop FF ₁₁ is the "H" to the set terminal S is input, the output of the output terminal Q becomes the "H", NAND
Since "H" is input to one input terminal of the element NA _12, signal equal to the output of the two one to the output terminal Q of the D flip-flop FF ₁₂ inputs of the NOR element NR ₁₁ through an inverter INV ₁₅ is is input, the output of the output terminal Q of the two to the other input terminal D flip-flop FF ₁₃ of the NOR element NR ₁₁ is input. Here, the D flip-flop FF ₁₁ is
Since the ripple carry signal sRCY ₁ output from the counter circuit 2 is input to the input terminal T through the two inverters INV ₁₃ and INV ₁₄ , a signal having the same phase as the ripple carry signal sRCY ₁ is output from the output terminal Q. . Further, D flip-flop FF ₁₂ is the input terminal T, the clock signal sCLK given from the microprocessor to the terminal CLK is input through two inverters INV _11, INV _12, the ripple carry signal from the output terminal Q srcY ₁ Is output. Further, D flip-flop FF ₁₃ is the input terminal T, the clock signal sCLK one inverter IN
Since input through V ₁₁ (i.e., the clock signal sCL
Since an inverted signal of K is input to the input terminal T), a signal whose phase is delayed by half a clock from the ripple carry sRCY ₁ is output from the output terminal Q. The input of the input terminal T of the D flip-flop FF ₁₄ of the toggle flip-flop circuit 3 is connected to the D flip-flop FF ₁₂
Since the the OR output of the output of the output terminal Q of the output terminal Q of the output and the D flip-flop FF _13, D flip-flop
From the output terminal Q of the FF ₁₄ the ripple carry signal srcY ₁ and phase signal is output. Thus, the ripple carry signal sRCY ₁ output from the counter circuit 2 is directly used as the trigger clock signal sRCY of the toggle flip-flop circuit 3.
Y ', and as shown in FIG. 9 (b), the ripple carry signal synchronized with the rise of the clock signal sCLK.
Since sRCY is input to the input terminal T of the D flip-flop, the output pulse signal sOUT is inverted in synchronization with the rise of the ripple carry signal sRCY output from the inverter of the toggle flip-flop circuit 3. in short,
The output pulse sOUT is inverted in synchronization with the rise of the clock signal sCLK.

On the other hand, when the half clock control signal sHLE becomes “H”,
The output of the NAND element NA ₁₂ becomes “L”. Accordingly, since the D flip-flop FF ₁₁ is the "L" to the set terminal S is input, the output terminal Q becomes the "L", since "L" to one input terminal of the NAND element NA ₁₂ is inputted, NAND element NA ₁₂ will output a "H" regardless of the output of the D flip-flop FF _12. Therefore, it means that one to "L" of the two input terminals of the NOR element NR ₁₁ is input, to the input terminal T of the D flip-flop FF ₁₄ and the output of the output terminal Q of the D flip-flop FF ₁₃ The same signal will be input. That is, since the ripple carry signal sRCY synchronized with falling edge of the clock signal sCLK is input to the input terminal T of the D flip-flop FF ₁₄ shown in Figure No. 9 (a),
Than the ripple carry signal srcY ₁ from the output terminal Q of the D flip-flop FF ₁₄ phase by a half clock is output signal delayed. In short, the output pulse signal sOUT is inverted in synchronization with the falling of the clock signal sCLK.
Thus, as shown in FIG. 9 (a), the rise of the ripple carry signal sRCY shifts to the right by a half clock,
The shifted ripple carry signal sRCY serves as a trigger signal for the toggle flip-flop circuit 3 to invert the output pulse signal sOUT.

Therefore, when the half clock control signal sHLE is “H”, the “H” section or “L” section is set to the section setting data sDA ₁
SsDA ₁₂ , sDB ₁ 〜sDB ₁₂ can be wider by half a clock signal sCLK than in the case of FIG. 9B (ie, when the half clock control signal sHLE is “L”). The setting accuracy of the “H” section and the “L” section can be doubled without increasing the frequency of the clock signal sCLK. Further, by synchronizing the half clock control signal sHLE with the section data set signal sHL, the half clock control can be automatically performed. That is, by inputting the half clock control signal sHLE at the time of inputting both section setting data sDA _{1 to} sDA ₁₂ and sDB _{1 to} sDB ₁₂ , the frequency f of the output pulse signal sOUT as shown in FIG.
Can be changed at regular intervals to soft start the lighting operation of the discharge lamp. In addition,
FIG. 10 (a) shows an example of a change in the frequency f in the case where the discharge lamp lighting is soft-started without performing the half clock control, and FIG. 10 (b) starts the discharge lamp lighting by performing the half clock control. The example of the change of the frequency f in the case where the frequency is changed is shown, and when the half clock control is performed, the change width of the frequency f can be reduced to half compared with the case where the half clock control is not performed, and the smoother can be achieved. It can be seen that soft start can be performed.

Next, in the two-phase clock generation circuit 7 shown in FIGS. 1 and 7, the non-overlapping section setting data sHB _{1 to} sHB
Counting the clock signal sCLK from the macro Gray processor B ₈ is at a preset presettable counter circuit 7a adapted to set the non-overlapping interval, as shown in FIG. 11, the presettable counter A gate control signal for controlling the gate circuit 7c based on the ripple carry signal sRCY ₂ ′ output from the circuit 7a is formed in the gate control circuit 7b, and the output pulse signal is output by the gate circuit 7c controlled by the gate control signal. Two-phase clock signal sOUT ₁ , with non-overlap section added to sOUT
sOUT ₂ is formed.

The output pulse signal sOUT and the two-phase clock signals sOUT ₁ and sOUT ₂ generated as described above are output via the output switching circuit 8 shown in FIG. ₁ , and the switching signal sSE / HB Is "H", the output pulse signal sOUT is output. When the switching signal sSE / HB is "L", the two-phase clock signal is output.
sOUT ₁ and sOUT ₂ are output. Therefore, the switching signal sSE / H
By appropriately setting B, a pulse generator that can support the single-end type or half-bridge type discharge lamp lighting device 10 can be obtained.

In the above embodiment, the pulse generator including the half clock control circuit 6 is exemplified.
It is not always necessary to provide the half clock control circuit 6, and even when the half clock control circuit 6 is not provided, the "H" section and the "L" section of the output signal sOUT are set in the same manner as in the above embodiment. Can be set arbitrarily, on duty,
Of course, the off duty can be set. This is because even when the half clock control circuit 6 is provided, the half clock control signal sHLE output from the microprocessor as described above (that is, the half clock control sHALF output from the data latch circuit 1).
In the case of but "L", the ripple carry signal srcY ₁ output from the counter circuit 2 becomes as trigger clock signal of the toggle flip-flop circuit 3 srcY ', in the case of half the clock control signal sHLE is "L" Is apparent from the fact that the half clock control circuit 6 can be regarded as absent.

[Effects of the Invention] The present invention is configured as described above, and latches "H" section setting data and "L" section setting data of an output pulse signal in a data latch circuit, counts a clock of a fixed cycle, and A ripple carry signal from a presettable counter circuit in which both section setting data are alternately set is used as a trigger clock of a toggle flip-flop circuit,
Since the pulse width modulated output pulse signal is obtained from the toggle flip-flop circuit, the microprocessor uses an internal counter to set the "H" section and "L" section as in the conventional microprocessor. The setting accuracy of ON / OFF duty is not regulated in the machine cycle of, and the “H” section and “L” section can be set arbitrarily regardless of the machine cycle.
There is an effect that the setting accuracy of the off-duty can be increased.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of one embodiment of the present invention, FIGS. 2 to 7 are main part circuit diagrams of the same, and FIGS. 8 to 11 are operation explanatory diagrams of the same. 1 is a data latch circuit, 2 is a counter circuit, 3 is a toggle flip-flop circuit, and 4 is a timing control circuit.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Minoru Kuroda 1048 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Works, Ltd. 56) References Japanese Utility Model 60-129748 (JP, U)

Claims (1)

(57) [Claims] 1. A data latch circuit for latching "H" section setting data and "L" section setting data of an output pulse signal, and a presettable which counts a clock of a fixed period and sets both the section setting data alternately. A counter circuit, and a toggle flip-flop circuit using a ripple carry signal from the counter circuit as a trigger clock. The pulse width control means for independently changing both section setting data is provided. A pulse generator, wherein a pulse width modulated output pulse signal is obtained from a circuit.