JP3342044B2 - Pulse generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse generation circuit for generating a control pulse in an inverter circuit or the like controlled by a PWM method.

[0002]

2. Description of the Related Art Heretofore, there has been provided a pulse generating circuit capable of setting an ON period and an OFF period of an output pulse with reference to a clock signal. For example, as shown in FIG. 8, this type of pulse generating circuit converts data Dt in an ON period and an OFF period output from a data generator 1 such as a microcomputer into timing signals ta and ta, respectively.
There are provided latch circuits 2a and 2b which take in in synchronization with tb. The count-up set values of the counters 3a and 3b, which are presettable counters, are set by the data Dt of the ON period and the OFF period taken into the latch circuits 2a and 2b, and the counters 3a and 3b correspond to the set values. The number of clock signals clk to be counted is counted. Each of the counters 3a and 3b inverts the carry signal output from the carry terminal CY at the time of overflow by the inverting circuits 4a and 4b and inputs the inverted signal to the load terminal LOAD.
When the carry signal rises after counting is completed, the input to the load terminal LOAD falls, and the data Dt for the next ON period or OFF period is captured.

The carry signal of the counter 3a is input to the J terminal of an output circuit 5 composed of a JK flip-flop, and the carry signal of the counter 3b is input to the K terminal of the output circuit 5. Therefore, the output circuit 5 sets the output of the non-inverting output terminal to the H level when the input from the counter 3a is at the H level, and sets the output of the non-inverting output terminal when the input from the counter 3b is at the H level. Is set to L level. The non-inverting output terminal of the output circuit 5 is a counter 3b.
And the inverted output terminal of the output circuit 5 is connected to the enable terminal EP of the counter 3a.
As a result, the output from the non-inverting output terminal of the output circuit 5 becomes H
During the period when the level is at the level, the counter 3b outputs the clock signal clk.
And the length of the period during which the output from the non-inverting output terminal is at the H level is determined.
During the period when the level is at the level, the counter 3a outputs the clock signal clk.
To determine the length of the period during which the output from the non-inverting output terminal is at the L level.

With the above-described configuration, the latch circuits 2a,
If the data Dt of the ON period and the OFF period is set in 2b, the ON period and the OFF period of the output pulse can be arbitrarily set within a range that is an integral multiple of the clock signal clk.

[0005]

In the case where an inverter circuit controlled by a PWM method is used in a discharge lamp lighting circuit, a motor control circuit, or the like, the control form of the pulse generation circuit is changed according to the type of load. Need arises.
For example, a control method that adjusts both the on-period and the off-period of the output pulse, a control method that regulates only the on-duty by keeping the period of the output pulse constant, a start point of the on-period based on a timing signal input from the outside And a control format in which the start point of the off period is determined. The above-described conventional configuration has a problem that it can only cope with a control format in which both the ON period and the OFF period are set, and cannot cope with a case where control in another control format is required.

That is, in the conventional configuration, it is necessary to configure a separate circuit for each control type. Even though a similar circuit is configured, various types of components are managed during assembly, and component management is performed. Is troublesome. SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described problems, and it is possible to operate in a plurality of types of control formats according to types of external signals and external data, and to share one circuit for a plurality of functions. It is an object of the present invention to provide a pulse generating circuit as described above.

[0007]

In the present invention, there is provided a means for solving], in order to achieve the above object, of the number corresponding to the data fetches data from the outside in synchronization with the signal that will be input to the load terminal with the load terminal Two counters for outputting a carry signal when the clock signal is counted, and an output having two input terminals for setting the output signal to H level by one input signal and setting the output signal to L level by the other input signal a circuit, the input source of the input source and the input signal to the <br/> output destination and an output circuit for providing a carry signal of each counter for inputting a signal to the load terminal of each counter from the outside
A binary load signal generated by the instruction of
And a selection circuit for selecting the combination of the carry signals of the respective counters with the load terminals of the other counters. a first operating state of the other input signal of the signal output circuit for inputting to the counter load terminal of the one input signal of the output circuit of the carry signal of one of the counters is generated at appropriate intervals the load signal and for The load signal , a signal for inputting the carry signal of one counter to one input signal of the output circuit and the carry signal of the other counter to the load terminals of both counters, and the other of the output circuit. The third operation state as an input signal is selected alternatively.

[0008]

According to the above configuration, in the first operating state, respectively, by the incorporated Lud over data in each counter, will be the ON period and OFF period of the output signal of the output circuit is determined, also the In the second operation state, the load signal generation interval becomes the cycle of the output signal of the output circuit, and the data taken into the counter sets the ON period or the OFF period of the output signal. In this state, the period of the output signal of the output circuit is determined by the data captured by one counter, and the ON period or the OFF period of the output signal is set by the data captured by the other counter. As described above, by sharing the counter and the output circuit and selecting the operation state by the selection circuit, three types of operations can be performed, and one circuit can be shared by three different types of control.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 1, basically, a latch circuit 2 capable of holding two data, a pair of counters 3a and 3b, and an output circuit 5 comprising a D flip-flop are provided. . Each counter 3a, 3b has a load terminal
When the signal input to LOAD falls, the data input to the D terminal is fetched, and the preset value of the number of clocks up to the overflow can be set so that the clock signal clk is counted from the fetched data value. Consists of a counter. Each of the counters 3a and 3b counts the number of clock signals clk corresponding to the set value and, when it overflows, raises the carry signal output from the carry terminal CY to the H level. When the reset signal rst input to the clear terminal CLR becomes L level, the set value and the output value are released. One counter 3a receives a set value from the latch circuit 2, and the other counter 3b
, A set value is alternatively input from one of the latch circuit 2 and the data setting unit 6 in which the internal data is set. Whether the set value input to the counter 3b is input from the latch circuit 2 or the data setting unit 6 is selected by a selection circuit 7a composed of a logic circuit.

The selection circuit 7a includes a pair of AND circuits A
N₁₁, AN₁₂And both AND circuits AN₁₁, AN₁₂Output of
OR circuit OR that outputs logical sum₁And one of the AND circuits
AN₁₁Circuit NT for inverting one input of₁And from
Become. The other AND circuit AN₁₂One input terminal of the
Road NT₁And the selection signal sel is
Is entered. Therefore, the selection signal sel is at L level.
AND circuit AN ₁₁Can be passed, and
When signal sel is at H level, AND circuit AN₁₂Through
It will be possible. That is, one of the signals is selected according to the selection signal sel.
AND circuit AN₁₁, AN₁₂Can be passed through alternatively
It is. Here, AND circuit AN₁₁Has a latch circuit 2
Connected AND circuit AN₁₂Is connected to the data setting unit 6
The output of the OR circuit OR is input to the counter 3b.
The setting value of the counter 3a by the selection signal sel
Is input from either the latch circuit 2 or the data setting unit 6.
Or you can choose.

A carry signal output from the carry terminal CY of each of the counters 3a and 3b is alternatively input to a clock terminal of the output circuit 5 through a selection circuit 7b, and is supplied to a NAND circuit NA and an exclusive NOR circuit through a selection circuit 7c. X
Input to OR. In the output circuit 5, since the power supply voltage is applied to the D terminal, when the input to the clock terminal, which is the output of the selection circuit 7b, rises, the output of the non-inverting output terminal is set to H level.

The selection circuits 7b and 7c have the same configuration as the selection circuit 7a, and each of the selection circuits 7b and 7c has a pair of AND circuits AN.
_{21, AN 22, AN 31,} AN 32, OR circuit OR _2, O
R ₃ and inverting circuits NT ₂ and NT ₃ . The selection circuit 7b inputs the carry signal of the counter 3b to the output circuit 5 when the selection signal sel is at the L level,
When sel is at H level, the carry signal of the counter 3a is input to the output circuit 5. The selection circuit 7c outputs a carry signal of the counter 3a when the selection signal sel is at the L level, and outputs a carry signal of the counter 3b when the selection signal sel is at the H level. Further, the carry signal of the counter 3b is input to the load terminal LOAD of the counter 3a, and the counter 3b passes through the OR circuit OR.
b is input to the load terminal LOAD.

The reset signal rst is input to the NAND circuit NA together with the output of the selection circuit 7c.
Is input to the reset terminal R of the output circuit 5 through the AND circuit AN. The load signal ld from the load signal generator 8 is also input to the AND circuit AN. The load signal generator 8 generates a load signal ld whose output is kept at L level for a certain period according to a load request signal from the outside. The activation signal st is input to the exclusive NOR circuit XOR together with the output of the selection circuit 7c. Carry signal of counter 3b, output signal of exclusive NOR circuit XOR, load signal
ld is the load terminal LO of the counter 3b through the OR circuit OR.
Input to AD.

The circuit shown in FIG. 1 can be configured as an integrated circuit and can be handled as one component. In addition, by the combination of the selection signal sel and the load request signal, it is possible to operate in the following three types of control formats. That is, the mutual load format in which the selection signal sel is at the L level and the load request signal keeps the output of the load signal generator 8 at the H level,
Is an L level, an external load format in which the load signal ld is output from the load signal generator 8 at a desired timing in response to the load request signal, and the selection signal sel is at an H level and the load request signal is 8 can be selected from among three types of self-loading type in which the output of H is maintained at H level.

In the mutual load format, the connection relationship is as shown in FIG. That is, the data from the latch circuit 2 is input to each of the counters 3a and 3b, and the carry signal output from the carry terminal CY is input to the other load terminal LOAD. The output pulse out from the output circuit 5 goes high when the carry signal of the counter 3a rises, and goes low when the carry signal of the counter 3a rises.

FIG. 3 shows the timings of the signals of the respective sections. That is, when the reset signal rst rises as shown in FIG. 3B at the time of starting, the set values of the counters 3a and 3b are released, and the output pulse out of the output circuit 5 becomes L level. In this state, two data are sequentially input to the latch circuit 2. That is, data (10, 01) is sequentially generated as shown in FIG.
The timing signals ta and tb are sequentially generated as shown in FIG.
Each data is taken into the latch circuit 2.

When a start signal st is generated as shown in FIG. 3 (e) in a state where data is set in the latch circuit 2, the data is taken into the counter 3b and counting is started as shown in FIG. 3 (f). Is done. When the counter 3b overflows, the carry signal of the counter 3b rises as shown in FIG. 3 (g), and the output pulse out of the output circuit 5 goes high. Also, since the carry signal of the counter 3b falls immediately, the input to the load terminal LOAD of the counter 3a falls as shown in FIG. 3 (h), and the counter 3a takes in data from the latch circuit 2 and starts counting. I do. Thereafter, when the counter 3a overflows, FIG.
The carry signal becomes H level as shown in FIG.
, The output pulse out of the output circuit 5 becomes L level. Further, the falling edge of the carry signal of the counter 3a causes the counter 3b to take in the data of the latch circuit 2 and start counting. In this way, the counters 3a and 3b alternately repeat the counting operation, and output pulses
The ON period and the OFF period of out are determined by the two data held in the latch circuit 2. FIG. 3 (k) shows the clock signal clk.

In the external load format, the connection relationship is as shown in FIG. In this configuration, when a load request signal is generated at a desired time, the counter 3b starts counting, and after counting the number of clock signals corresponding to the data set in the latch circuit 2, the carry signal of the counter 3b is output. The output pulse out of the output circuit 5 rises to the H level and rises to the H level, and the output pulse out falls to the L level when a load request signal is next input. In other words, the cycle of the output pulse out can be set by the generation interval of the load request signal, and the off period of the output pulse out can be set by external data set in the latch circuit 2.

FIG. 5 shows the timings of the signals of the respective parts. That is, when the reset signal rst rises as shown in FIG. 5B at the time of starting, the set value of the counter 3b is released, and the output pulse out of the output circuit 5 becomes L level as shown in FIG. 5G. In this state, the latch circuit 2
Input one piece of data. That is, the data (01) is generated as shown in FIG. 5A, and the timing signal tb is generated as shown in FIG.
Take in.

When the load signal ld is generated as shown in FIG. 5D with the data set in the latch circuit 2,
Data is taken into the counter 3b and counting is started as shown in FIG. When the time of the counter 3b is up, the carry signal of the counter 3b rises as shown in FIG. 5 (f), and the output pulse out of the output circuit 5 becomes H level as shown in FIG. 5 (g). Thereafter, the output pulse out of the output circuit 5 is maintained at the H level. On the other hand, when the next load signal ld is generated from the load signal generator 8 as shown in FIG.
Is reset to the L level and the counter 3
The next data is input to b. By repeating the above operation, the period of the output pulse out is determined by the generation interval of the load signal ld based on the external load request signal, and the off period of the output pulse out is determined by the data held in the latch circuit 2. Will be.
FIG. 5H shows the clock signal clk.

In the self-load type, the connection relationship is as shown in FIG. In this configuration, one counter 3a receives data from the latch circuit 2 and the other counter 3b receives data from the data setting unit 6. The carry terminal CY of one counter 3a is connected to the clock terminal of the output circuit 5, and the carry terminal CY of the other counter 3b is connected to the load terminal LOAD of the counter 3a. The carry signal of the counter 3b is the load terminal of the counter 3b.
Exclusive OR circuit XOR with start signal st for LOAD
Is entered through Therefore, when only one of the start signal st and the carry signal of the counter 3b becomes H level, the input to the load terminal LOAD falls and data is taken in from the data setting unit 6 to the counter 3b. When the carry signal of the counter 3b falls, the counter 3a
The data from the latch circuit 2 is fetched. further,
The carry signal of the counter 3b is input to the reset terminal R of the output circuit 5 through the NAND circuit NA together with the reset signal rst. That is, since the reset signal rst is at the H level after activation, when the carry signal of the counter 3b rises, the output circuit 5 is reset, and the output pulse out from the output circuit 5 goes to the L level. Also,
The output pulse out from the output circuit 5 goes high when the carry signal of the counter 3a rises. After all, the cycle of the output pulse out is determined by the data from the data generator 6 which is taken into the counter 3b.
The off-period is determined by the data from the latch circuit 2 which is taken into the memory.

FIG. 7 shows the timing of the signals of the respective parts. Here, it is assumed that data (10) is set in the latch circuit 2 as shown in FIG. 7A, and data (01) is set in the data setting unit 6 as shown in FIG. 7F. At the start, the reset signal rst as shown in FIG.
Rises, the output circuit 5 is reset as shown in FIG. After the reset, the start signal st rises as shown in FIG. 7 (g), the data (01) is taken into the counter 3b from the data setting unit 6, and the timing signal ta as shown in FIG. 7 (c). , The data (10) is taken into the latch circuit 2. The counter 3b is (01)
The clock signal clk is counted from
(That is, when three clock signals are counted), the carry signal rises as shown in FIG. 7 (i).
At this time, the counter 3b takes in the data of the data setting unit 6 again and resets the output circuit 5. However, since the output pulse out is originally at the L level, there is no change in the output pulse out. When the carry signal of the counter 3b falls, the data of the latch circuit 2 is taken into the counter 3a, and the counter 3a sets (10)
And counts the clock signal. Therefore, FIG.
When two clock signals clk are counted as shown in FIG.
7 (e), the carry signal of the counter 3a rises, and as shown in FIG. 7 (j), the output pulse out from the output circuit 5 rises. Then, when the carry signal of the counter 3b rises as shown in FIG.
out falls. Thus, the counter 3b determines the period of the output pulse out, and the counter 3a determines the period of the output pulse ou.
Determine the off period of t. FIG. 7 (k) shows the clock signal clk.

As described above, using the latch circuit 2, the two counters 3a and 3b, the selection circuits 4a, 4b and 4c, the output circuit 5, and the data setting unit 6, the mutual load format is used.
One of three types of operation, an external load type and a self-load type, can be selected. In contrast to the conventional configuration in which different components are used for each type of operation according to the application, one circuit is used for three types. It has the advantage that it can be used for different types of operation. In particular, if the circuit is formed as one component as an integrated circuit, one component can be used for various purposes, and component management becomes easy.

[0024]

According to the present invention as described above, the number of clock signals corresponding to the data fetches the de <br/> over data from the outside in synchronization with the signal that will be input to the load terminal with the load terminal An output circuit having two input terminals for setting the output signal to H level by one input signal and setting the output signal to L level by the other input signal; , 2 value generated by the instruction of the input source of the input signal to the output destination and an output circuit for providing an input source and <br/> carry signal of each counter for inputting a signal to the load terminal of each counter from the outside No
Combination of mode signal and binary selection signal given from outside
And a selection circuit that selects by matching .
A first operation state in which the carry signal of each counter is a signal to be input to the load terminal of another counter and each input signal of the output circuit, and the load signal is appropriately interposed.
Generated at an interval and the carry signal of one counter as one input signal of the output circuit and input to the load terminal of that counter
Signal and the other input signal and the load signal of the output circuit that
A second operating state of the item, and the other input signal of one of the counter one of the input signals signal and an output circuit for inputting the carry signal of the other counter to both counter load terminal of the output circuit a carry signal In the first operating state, each counter repeats the counting operation alternately, and the output circuit
Sets the output signal of one counter during counting to H level,
Set to L level during counting by the other counter. In other words, each by incorporated Lud over data in each counter, the on period and off period of the output signal of the output circuit is to be determined. In the second operation state, one of the counters
From generation interval output circuit of the input signal to the load terminal
Output cycle and the load end of the counter .
The data taken into the counter in synchronization with the transition point of the signal input to the slave sets the ON period or the OFF period of the output signal . Further, in the third operation state,
The period of the output signal of the output circuit is determined by the data captured by one counter, and the ON period or the OFF period of the output signal is set by the data captured by the other counter. In this way, the counter and output circuit are shared and the combination of the external load signal and the selection signal
Suit Thus changing the connection between the counter and the output circuit
By providing the selection circuit, there is made possible three types of operations, it has a advantage that share a single circuit in three different control types.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment.

FIG. 2 is a circuit diagram showing a connection relationship when a mutual load format is selected in the embodiment.

FIG. 3 is an explanatory diagram of an operation of a mutual loading format in the embodiment.

FIG. 4 is a circuit diagram showing a connection relationship when an external load format is selected in the embodiment.

FIG. 5 is an explanatory diagram of an operation of an external load format in the embodiment.

FIG. 6 is a circuit diagram showing a connection relationship when a self-loading type is selected in the embodiment.

FIG. 7 is an explanatory diagram of an operation of a self-loading type in the embodiment.

FIG. 8 is a circuit diagram showing a conventional example.

[Explanation of symbols]

 2 Latch circuit 3a Counter 3b Counter 5 Output circuit 6 Data setting section 7a Selection circuit 7b Selection circuit 7c Selection circuit 8 Load signal generation section

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Minoru Kuroda 1048 Odomo Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Works, Ltd. (58) Field surveyed (Int. Cl. ⁷ , DB name) H03K 5/135 H03K 7 / 08 H03K 5/156

Claims (1)

(57) [Claims] A load terminal connected to the load terminal;
And two counter outputs a carry signal when counting the clock signal number corresponding to the data fetches data from an external signal in synchronization that the output signal by one input signal includes two input terminals and an output circuit for setting the output signal by the set other input signal to the H level to the L level, output <br/> Chikarasaki provide input source and the carry signal of the counter for inputting a signal to the load terminal of each counter input source and the external of the input signals to an output circuit
Binary load signal generated by instruction and given from outside
And a selection circuit for selecting the carry signals of the respective counters as signals input to the load terminals of the other counters and as input signals of the output circuit. A first operating state, wherein the load signal is generated at appropriate intervals, a carry signal of one counter is used as one input signal of an output circuit, and a signal input to the load terminal of the counter and the other input signal of the output circuit are used. A second operation state as the load signal , a signal for inputting the carry signal of one counter to one input signal of the output circuit and the carry signal of the other counter to the load terminals of both counters, and the other input to the output circuit. A pulse generating circuit for selectively selecting a third operation state to be a signal.