KR950007509A - HDTV Video Format Converter Combined with Video Decoder - Google Patents

Abstract

The present invention relates to an HDTV video format converting apparatus combined with an image decoder. The present invention relates to a VLD and demultiplexing means for decoding a compressed bit stream into a meaningful signal and dividing the signals into respective necessary portions, which are inputted from the VLD and demultiplexing means. Inverse quantization according to the signal is a de-quantization means, a frame memory means for storing a signal output from the quantization means IDCT means, a signal compensated for the movement output from the VLD and the demultiplexing means, the frame memory means and the IDCT means An addition means for adding a signal outputted from the video signal to the frame memory means, and outputting a video signal having a 525-line sequential scan format as a signal output from the IDCT means, VLD, demultiplexing means, and addition means. It is characterized by consisting of means.

Description

HDTV Video Format Converter Combined with Video Decoder

Since this is an open matter, no full text was included.

1 is a configuration diagram of an image decoder applied to the present invention,

2 is a unit structure diagram of an image signal for coding;

3 is a HDTV video format conversion apparatus according to the present invention,

4 is a detailed configuration diagram of the conversion unit of FIG.

5 is a view illustrating an embodiment of the sequential scan converter of FIG.

6 is a signal waveform diagram of each part of FIG.

Claims (19)

Inverse quantization means inverse quantization means according to a signal input from the VLD and demultiplexing means 12, and the VLD and demultiplexing means 12 for decoding the compressed bitstream and dividing the signals into respective necessary portions. (13), motion compensating means (17) for compensating for the motion by using the motion information output from the IDCT means (14), the VLD and the demultiplexing means (12), and the signal output from the inverse quantization means (13); A frame memory means 16 for storing the motion compensated signal output from the motion compensation means 17, a signal output from the frame memory means 16 and the IDCT means 14, and adding the frame memory means 16 to the frame memory means 16; An adder (15) outputted by the < RTI ID = 0.0 > and < / RTI > the IDCT means (14), the VLD and the demultiplexing means (12) and the adder (15). HDTV video format conversion apparatus according to claim consisting of the conversion means (18) for outputting a signal. 2. The converting means (18) according to claim 1, wherein said converting means (18) is a first sequential scanning converting means (23) for dividing an input 1050-line interlaced video signal into two phases and converting an odd field into a sequential scanning format, Line per frame of the signal output from the first sequential scan conversion means 24 and the first sequential scan conversion means 23 for dividing the 1050-line interlaced video signal into two phases and converting the even field into a sequential scan format. First vertical decimation means 25 for converting the number, second vertical decimation means 26 for converting the number of lines per frame of the signal output from the second sequential scan conversion means 24, and first vertical decimation. A first horizontal decimation means 27 for changing the number of pixels per line of the signal output from the simulation means 25 and a second for converting the number of pixels per line of the signal output from the first vertical decimation means 26. Horizontal decimation number Stage 28, a first frame memory means 29 for converting the video signal output from the first horizontal decimation means 27 into an output of a desired speed, and output from the second horizontal decimation means 28 Second frame memory means 30 for converting the video signal to an output of a desired speed, and switching means 31 for alternately selecting and outputting the video signals output from the second and second frame memories 29,30. HDTV video format converter, characterized in that. 3. The macro block line memory (35) according to claim 2, wherein the first and second sequential scan converting means (23, 24) convert the image signals input in units of macro blocks in units of lines and output them in units of lines. A first line memory 36 connected to 35, a second line memory 37 connected to the first line memory 36, and an adder connected to the second line memory 37 and the macro block line memory 35; (38), 1/2 dividing means 39 for dividing the output of the adder 38, the 1/2 dividing means 39, the first line memory 36 and the first or second frame memory ( A first multiplexer 40 having an output of 29,30 as an input, a second multiplexer 41 selecting an output of the first line memory 36 and the first multiplexer 40, and an error signal being inputted Summing means 45, the first delay compensating means 46 for delay-compensating the output of the summing means 45, and a macroblock type signal are input. Multiplexer selection adjusting means 46 for controlling the first multiplexer 40 by using the second delay compensating means 47 and the signals output from the first and second delay compensating means 46 and 47. HDTV video format converter, characterized in that consisting of. 3. The macro block line memory (55) according to claim 2, wherein the first and second sequential scan converting means (23, 24) convert the image signals input in units of macro blocks in units of lines and output the lines. A first line memory 56 connected to 35, a second line memory 57 connected to the first line memory 56, a third line memory 63 connected to the first line memory 57, and A first adder 58 connected to the macro block line memory 55 and the second line memory 57, a first 1/2 divider 59 connected to the adder 58, and the macro block line memory 55 And a first edge preserving filter 60 connected to the second line memory 57, a second adder 64 connected to the third line memory 63 and the first line memory 56, and the first line memory ( A second edge retention filter 66 connected to a third line memory 63 connected to the first line; a first delay compensation means 72 to which motion information is input; The summation means 73, the second delay compensation means 75 into which the macro block type signal is input, the third delay compensation means 74 connected to the summation means 73, the first, second and third delays; Multiplexer selection adjusting means 71 connected to the compensating means 72, 74, 75, the first 1/2 divider 59, the first edge preservation filter 60, the first line memory 56 and the multiplexer selection Multiplexer selection saving means (71) of the first multiplexer (61) connected to the adjusting means (71), the second half divider (65), the second edge preservation filter (66), and the second line memory (57). A second multiplexer 69 connected to the third multiplexer 62 connected to the first multiplexer 61 and the first line memory 56, and the second multiplexer 69 and the first line memory 57. And a fourth multiplexer (70) connected to the HDTV video format converter. 3. The apparatus of claim 2, wherein the first and second vertical datum means (25, 26) comprise: filter means (85) for eliminating elimination; memory means for converting the output of the filter means (85) to a desired number of lines; (83), and memory adjusting means (84) for controlling read and write operations of said memory means (83). 3. A line according to claim 2, wherein said first and second horizontal datum means (27, 28) comprise a filter means (86) for eliminating elising and a line for converting the output of said filter means (85) to a desired number of lines. HDTV video format converter, characterized in that the conversion means (91). 4. The HDTV video format conversion according to claim 3, characterized in that the macroblock line memory 35 and the first line memory 36 are used simultaneously by the first and second sequential scan conversion means 23,24. Device. 4. The multiplexer selection control means (46) divides a pixel to be interpolated into motions (100, 101) and selects a signal of another field (104) if it is a stop (100, 101). And a control signal for selecting a motion compensated video signal (102) and outputting a control signal for selecting (103) to interpolate through a line average if the motion and stop parts are not. The method of claim 4, wherein the multiplexer selection control unit 71 divides a pixel to be interpolated into a stop part, a part having a small motion, and a part having a large or other motion (110, 111) and selects a signal of another field. Selects an output signal of the edge preserving filter 66 if the motion is a small portion (113); and outputs a control signal for selecting the interpolation (112) through a line average if the motion is large or other portions. HDTV video format converter, characterized in that. 5. The apparatus of claim 4, wherein the first and second edge preserving filters (60, 66) filter by the pixel average when the pixel difference between the vertical diagonal lines is minimum. 6. The filter means (85) according to claim 5, wherein the filter means (85) comprises a plurality of line delay means (77, 78, 79) connected in series, and coefficients (K1, K2,...) Of output signals and image signals of the plurality of delay means (37). And a multiplier (80,81) for multiplying Kn) and an adder (82) for adding the outputs of the multipliers (80,81). 7. The plurality of latches 88 connected in series are multiplied by coefficients K1, K2, ..., Kn by output signals of the plurality of latches 88 and image signals. And an adder (82) for adding up the outputs of the multipliers (80, 81). 7. The line converting means (91) according to claim 6, characterized in that the line converting means (91) comprises a 1: 2 demultiplexer (91) for outputting only one of two phases when the input image format is 1050 lines and the display image format is 525 lines. HDTV video format converter. 7. The demultiplexer (4) according to claim 6, wherein the line converting means (91) divides 4 phases to output only 3 phases when the input image format is 1050 lines and the display image format is 787.5 lines, and the 1 An HDTV video format converter comprising: a 3: 1 demultiplexer (95) for selecting and outputting a phase output of a: 4 demultiplexer (94). 10. The apparatus of claim 8 or 9, wherein the stop unit is a case in which the sum of the errors is less than a threshold and the macro block type is in a non-motion enhanced mode. 10. The apparatus of claim 8, wherein the motion unit is a case in which the sum of errors is less than a threshold and the macro block type is in a non-motion enhanced mode. 9. The apparatus of claim 8, wherein the other part has a sum of errors less than a threshold and the macro block type is in an intra-frame mode. 10. The apparatus of claim 9, wherein the less motion is when the sum of the errors is less than the threshold and the macro block type is in the Non-Motion Comptensated mode. 10. The method of claim 9, wherein the larger or more motion part has an error sum less than a threshold and the macro block type is an intra-frame mode. The HDTV video format converter, characterized in that the non-Motion Comptensated mode, and the sum of the errors is greater than the threshold. ※ Note: The disclosure is based on the initial application.