KR950006582A - Boolean operation method using Programmable Logic Device (PLD) and its device - Google Patents

Abstract

The present invention relates to a Boolean operation method and a device using a programmable logic device (PLD), and in particular, the present invention relates to logic elements and flip-flops such as logical AND (AND), logical OR (OR), inverter (NOT), etc. A function performs a Boolean operation of a predetermined bit of digital data, and performs a Boolean operation by receiving a signal for data processing by connecting to a central processing unit. Therefore, the present invention provides the effect of simplifying the hardware configuration of the system for performing Boolean operations under the control of the central processing unit since the necessary logical operations are performed every time using the PLD.

Description

Boolean operation method using Programmable Logic Device (PLD) and its device

Since this is an open matter, no full text was included.

1 is a block diagram showing a Boolean operation apparatus using a programmable logic device according to the present invention.

Claims (7)

In the apparatus for performing a Boolean operation in the digital data processing, the operable data of a predetermined bit to perform a predetermined logic operation and the read or write signal for controlling the operation of the operation and the logic operation is applied to the Boolean operation unit, A central processing unit for applying an address signal for a specified logical operation to a decoder; A decoder which decodes the address signal applied from the central processing unit and applies a specified logical operator signal and a Boolean operator operation performing signal to the Boolean operator; And a predetermined number of logic operators, the operation is initiated in response to a Boolean operation operation signal applied from the decoder, loaded with operand data applied from the central processing unit in accordance with a write signal, and designated logic applied from the decoder. PLD including a Boolean operation unit that receives the operation data with the corresponding logic operator enabled according to the operator signal, performs the operation data and the corresponding logic operation, and outputs the logical operation result data in response to the read signal applied from the central processing unit. Boolean operation using. The CPU of claim 1, wherein the Boolean operator stores the operand data applied from the central processor in response to a write signal when the operation execution signal is applied from the decoder, and when the logical product operator signal is applied from the decoder. A logical product operator for performing an AND operation on the operation data and the operand data applied from the logic unit, and outputting in response to the read signal applied from the central processing unit; Operand data stored from the central processing unit when the operation execution signal is applied from the decoder, and read operation data from the central processing unit through the logic elements enabled when the logic operator signal is applied from the decoder. A logical arithmetic operator that receives each operation data and performs logical sum operation on the operation data; And operation data applied from the central processing unit through logical AND elements which store the operand data applied from the central processing unit when the operation execution signal is applied from the decoder and is enabled when the exclusive logic operator signal is applied from the decoder. PLD of the PLD, characterized in that it consists of an exclusive logical operation that performs an AND operation on the inverted operand data whose state is inverted, and performs an AND operation on the inverted operation data and the operand data, and outputs the logical OR operation of the two AND operations. Boolean operation device. 3. The apparatus of claim 2, wherein the logical product operator comprises: a D-flip flop for receiving operand data or logical product result data as an input terminal and storing data of the input terminal whenever a write signal is applied to the clock terminal from the central processing unit; A logical AND element for performing an AND operation on the operation execution signal applied from the decoder and the read signal applied from the central processing unit to enable or disable the output state of the buffer; And a buffer receiving the output signal of the D-flip-flop and enabling or disabling the buffer according to the signal applied from the logical multiplication device. 3. The apparatus of claim 2, wherein the logic operator comprises: a D-flip flop for receiving the operand data or the logic operation result data as an input terminal and storing data of the input terminal whenever a write signal is applied to the clock terminal from the central processing unit; A logical AND element for performing an AND operation on the operation execution signal applied from the decoder and the read signal applied from the central processing unit to enable or disable the output state of the buffer; And a buffer under which the output of the data applied from the D-flip-flop is enabled or disabled under the control of the signal applied from the logical multiplication device. 3. The system of claim 2, wherein the exclusive logic operator comprises: a D-flip flop for receiving the operand data or the exclusive logic result data as an input terminal and storing data of the input terminal whenever a write signal is applied to the clock terminal from the central processing unit; A first inverter for inverting the state of the operation data applied from the central processing unit; A second inverter for inverting the state of data applied from the inverting output terminal of the D-flip-flop; A first logical element which performs an AND operation on the operation data applied from the central processing unit and the operand data applied from the inverted output terminal of the D-flip flop; A second logical element for performing an AND operation on data applied from the first inverter and the second inverter; A logic sum element for performing logical sum operation on the first logical element and the second logical element and applying the D-flip flop; A third logical element configured to perform an AND operation on the operation execution signal applied from the decoder and the read signal applied from the central processing unit to enable or disable the output state of the buffer; And a buffer receiving the output signal of the D-flip-flop and enabling or disabling the buffer according to a signal applied from the logical multiplication device. CLAIMS 1. A method for performing Boolean operations under control of a central processing unit using a programmable logic device (PLD) in digital data processing, comprising: generating an address signal for performing a desired logical operation; Generating a logical operation operation performing signal and a logical operator signal to decode the address signal to perform a designated logical operation; Generating operand data and operation data for performing a logical operation; And a Boolean operation step of performing operation according to the logic operation operation performing signal and receiving a specified bit of operand data and operation data to a logic element enabled according to the logic operator signal to perform a specified logic operation. Boolean operation method. 7. The method of claim 6, wherein the Boolean operation includes storing the input operand data for a predetermined time in response to a write signal applied from the central processing unit to receive a feedback input, and performing a desired operation through the input operation data and a plurality of logic steps. A Boolean calculation method using a PLD, comprising: obtaining a result and outputting a calculation result in response to a read signal applied from a central processing unit. ※ Note: The disclosure is based on the initial application.