JPH0721094A - Data inputting and outputting circuit - Google Patents

Abstract

PURPOSE:To prevent a direction register from being rewritten due to the noise, etc., by providing with a writing inhibiting circuit which permits writing in the direction register only once. CONSTITUTION:A latch circuit 26A is constituted of a switch circuit 18 which connects the output of a NOT circuit 16 with the input of a NOT circuit 15, and a switch circuit 17 which connects a power supply voltage with the input of the NOT circuit 15. An N channel transistor 19 is connected with the input of the switch circuit 15. A latch circuit 26B is constituted of NOT circuits 20 and 21, and switch circuits 22 and 23. The output of the latch circuit 26B and a writing signal WR to the direction register are inputted to a NOR circuit 24, and the output becomes a writing signal W to the direction register through a NOT circuit 25, so that the writing can be controlled. Thus, the writing in the direction register is permitted only once, and the direction register can be prevented from being rewritten due to the noise.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data input / output circuit used in a microcomputer and provided with a direction register for determining the direction of data input / output.

[0002]

2. Description of the Related Art FIG. 10 is a circuit diagram of a conventional data input / output circuit used in a microcomputer. In the figure, 10 is a direction register, which outputs the outputs of two NOT circuits 1 and 2 and a NOT circuit 2 connected in series.
The switch circuit 4 is connected to the input of the OT circuit 1 and the switch circuit 3 for obtaining the input signal of the NOT circuit 1 from the data bus 14 through the wiring 8. 5 is an N-channel transistor connected to the input of the NOT circuit 1, and 11
Is an input / output circuit for controlling the input / output direction by the output of the direction register 10 through the wiring 6. 9 is the data bus 1
Reference numeral 4 is a wiring connecting the input / output circuit 11 and 4, and 12 is an external input / output terminal connected to the input / output circuit 11 through the wiring 7. A data input / output circuit block 13 is composed of the direction register 10, the input / output circuit 11, and the external input / output terminal 12.

Next, the operation will be described. FIG. 11 shows
6 is a timing diagram of the direction register switch circuits 3 and 4 for a write signal WR to the direction register 10. FIG. When the content of the direction register 10 is set, the write circuit WR to the direction register 10 turns on the switch circuit 3 and simultaneously turns off the switch circuit 4.
At this time, data is input from the data bus 14 through the wiring 8, the switch circuit 3 is turned off and at the same time the switch circuit 4 is turned on, and the data is held by the latch circuit composed of the NOT circuit 1 and the NOT circuit 2. Therefore, when the data input / output circuit block 13 is used to input data, the content of the direction register 10 is set to the ground level (hereinafter, referred to as low level) and the data input from the external input / output terminal 12 is transferred. Data is input to the data bus 14 via the wiring 7, the input / output circuit 11, and the wiring 9.
When the data input / output circuit block 13 is used for outputting data, the content of the direction register 10 is set to the power supply voltage level (hereinafter, referred to as high level), and the data of the data bus 14 is input to the wiring 9. It outputs to the external input / output terminal 12 through the output circuit 11 and the wiring 7. In the initial state, the direction register 10 holds the low level because the N-channel transistor 5 is on for a certain period of time by the initialization signal.

As described above, the data input / output circuit block 1
The contents of the direction register 10 of No. 3 can be rewritten any number of times by the write signal WR to the direction register 10 as shown in FIG.

[0005]

In the conventional data input / output circuit as described above, the program runs away due to noise or the like and a write signal is output to the direction register, which rewrites the contents of the direction register, or the external register. There was a problem that a through current would flow to the circuit and the internal circuit.

The present invention has been made in order to solve such a problem, and prevents or detects that the program recklessly rewrites the contents of the direction register due to noise or the like, and an external circuit or an internal circuit is detected. The purpose of the present invention is to obtain a data input / output circuit that prevents a through current from flowing.

[0007]

In a data input / output circuit according to a first aspect of the present invention, a write-inhibit circuit is provided which can write to a direction register only once and cannot be repeatedly written.

In the data input / output circuit according to the second aspect of the present invention, the direction register is provided with a write-inhibit circuit that cannot be repeatedly written, and at the same time, the data is once written to the direction register, and then the data is written again when it is desired to change the contents. A write enable register is provided to enable the above.

A data input / output circuit according to a third aspect of the present invention is a circuit capable of changing the contents of a direction register by once writing the contents of the direction register and then changing the contents by writing to the direction register twice. To

A data input / output circuit according to a fourth aspect of the present invention is provided with a circuit for performing interrupt processing, and detects that writing to the direction register has been performed twice or more.

A data input / output circuit according to a fifth aspect of the present invention is provided with an initialization signal generating circuit for initializing the contents of the direction register when writing to the direction register is performed twice or more.

A data input / output circuit according to a sixth aspect of the present invention is provided with an interrupt processing circuit for detecting that the content of the direction register has changed.

[0013]

In the data input / output circuit according to the first aspect of the present invention, since the write inhibit circuit is provided so that the data can be written in the direction register only once, the data cannot be repeatedly written in the direction register.

In the data input / output circuit according to the second aspect of the present invention, since the write enable register is provided in the direction register, the data is written into the direction register only when it is desired to change the contents of the direction register.

In the data input / output circuit according to the third aspect, the writing to the direction register is performed twice only when the content of the direction register is desired to be changed.

According to another aspect of the data input / output circuit, the interrupt processing circuit detects the number of times of writing to the direction register.

According to another aspect of the data input / output circuit, the contents of the direction register are initialized according to the number of times of writing to the direction register.

The data input / output circuit according to the sixth aspect detects that the content of the direction register has changed due to the provision of the interrupt processing circuit.

[0019]

【Example】

Example 1. 1 is a circuit diagram showing a first embodiment of the present invention. In the figure, reference numeral 26A is a latch circuit. The latch circuit 26A connects the NOT circuits 15 and 16 in series to connect the output of the NOT circuit 16 to the input of the NOT circuit 15, and the power supply voltage to the NOT circuit. 15
The switch circuit 17 is connected to the input of. N-channel transistor 19 is connected to the input of the switch circuit 15. 26B is also a latch circuit, which has the same circuit configuration as the latch circuit 26A and is configured by NOT circuits 20 and 21, and switch circuits 22 and 23. The switch circuit 22 connects to the input of the NOT circuit 20. Not the power supply voltage but the output of the latch circuit 26A. Reference numeral 24 is a two-input NOR circuit into which the output 27 of the latch circuit 26B and the conventional write signal WR to the direction register are input, and the output of which passes through the NOT circuit 25 and the write signal W to the direction register according to the present invention.
(Corresponding to WR in FIG. 11), the switch circuits 3 and 4 shown in FIG. 10 are controlled. Although the direction register is not shown in FIG. 1, this direction register is the same as that shown in FIG. In addition, the switch circuits 17, 18, and 2 of FIG.
2, 23 are controlled by the conventional write signal WR to the direction register.

Next, the write signal WR to the direction register according to the first embodiment will be described. FIG. 2 shows a timing diagram for FIG. When a high level initial signal is input to the N-channel transistor 19 for a certain period, the input of the NOT circuit 15 becomes low level,
The output of the NOT circuit 15 becomes high level. as a result,
Since the switch circuits 18 and 22 turn on and the switch circuits 17 and 23 turn off, the output of the latch circuit 26A is held at the high level. At this time, since the switch circuit 22 is turned on, the input of the NOT circuit 20 becomes high level,
The output 27 of the latch circuit 26B becomes low level. In the initial state, as shown in FIG. 2, WR is at high level, so the output of the 2-input NOR circuit 24 is at low level and the output W of the NOT circuit 25 is at high level. Next, when the write signal WR to the conventional direction register becomes low level,
The switch circuits 17 and 23 are turned on, the switch circuits 18 and 22 are turned off, and the output of the NOT circuit 15 becomes low level. At this time, since the latch circuit 26B is held at the low level, the output 27 of the latch circuit also remains at the low level. As a result, the output 27 of the 2-input NOR circuit 24 becomes high level and the output W of the NOT circuit 25 becomes low due to the output 27 of the latch circuit 26B which is the input of the 2-input NOR circuit 24 and the write signal WR to the conventional direction register. It becomes a level. Also, the write signal W to the conventional direction register
When R becomes high level, the switch circuits 17 and 23 are turned off, the switch circuits 18 and 22 are turned on, and the NOT circuit 1
Since the output of 5 is low level, the output of the latch circuit 26A is held at low level. At this time, since the switch circuit 22 is turned on, the input of the NOT circuit 20 becomes low level and the output of the NOT circuit 20 becomes high level. Therefore, since the output 27 of the latch circuit 26B, which is the input of the 2-input NOR circuit 24, and the write signal WR to the conventional direction register are at the high level, the output of the 2-input NOR circuit 24 is at the low level and is the output of the NOT circuit 25. W becomes high level. As shown in FIG. 2, the latch circuit 26
When the output 27 of B is low level, W is input by the input of WR.
Is determined, but when the output 27 of the latch circuit 26B is at the high level, the output of W is always at the high level regardless of the input of WR. As a result of the above, FIG.
Writing to the direction register indicated by 0 can be performed once but cannot be repeated.

Example 2. FIG. 3 is a circuit diagram showing a second embodiment of the present invention. In the figure, the same reference numerals as those in FIG.
The latch circuit 42A has the same structure as that of the NOT circuit 28, the 2-input NOR circuit 29, the switch circuits 30, and 3.
1, the latch circuit 42B includes a NOT circuit 33,
34 and switch circuits 35 and 36. Three
2 is an N-channel transistor connected to the input of the NOT circuit 28, and one input of the two-input NOR circuit receives the output 43 of the latch circuit 42B as the input of the NOT circuits 37, 3
It becomes the output of the delay circuit 42C configured by 8. Also, 2
6C replaces the NOT circuit 15 of the latch circuit 26A in FIG. 1 with a 2-input NAND circuit 41, and inputs the other input to the output of the latch circuit 42B and the initialization signal.
It is a latch circuit obtained as an output of the OR circuit 40. Then, the latch circuits 42A and 42B, the delay circuit 42
A write permission register (hereinafter referred to as permission register) 44 is composed of C. The switch circuits 30 and 3
1, 35 and 36 are controlled by a write signal to the write enable register (hereinafter referred to as a write signal). FIG. 4 is a timing diagram for FIG.

Next, the permission register 44 will be described. In FIG. 3, when a high-level initialization signal is input to the N-channel transistor 32 for a certain period, NO
The input of the T circuit 28 goes low, and the output of the N-channel transistor 32 goes high. As a result, the switch circuits 31 and 35 turn on, and the switch circuits 30 and 3
Since 6 is turned off, the latch circuit 42A is held at the high level. At this time, since the switch circuit 35 is turned on, the input of the NOT circuit 33 becomes high level, and the NOT
The inputs of the circuit 38 and the 2-input NOR circuit 40 are at low level. Since the input of the NOT circuit 38 is low level, the output of the NOT circuit 37 also becomes low level, and the 2-input N
One input of the OR circuit 29 becomes low level. next,
When writing to the permission register, the write signal becomes low level, the switch circuits 30 and 36 are turned on, and the switch circuits 31 and 35 are turned off, so that the output of the NOT circuit 28 becomes low level. At this time, since the switch circuit 36 is on, the output 43 of the latch circuit 42B is held at the low level, and the NOT circuit 38 and the 2-input NOR circuit 40 are held.
The input to is still low. When the write signal goes high, the switch circuits 30 and 35 turn off and the switch circuits 31 and 36 turn on, so the output of the NOT circuit 28 goes low and the latch circuit 42AN.
The O transfer output is held at a low level. At this time, since the switch circuit 35 is turned on, the input of the NOT circuit 33 becomes low level, and the input of the NOT circuit 38 and one input of the 2-input OR circuit 40 become high level. NOT circuit 38
Since the input of is high level, the output of the NOT circuit 37 also becomes high level. Furthermore, since the delay circuits 42C are configured by the NOT circuits 37 and 38, there is a delay of several tens of nanoseconds from the input of the high level signal to the NOT circuit 38 until the output of the high level signal from the NOT circuit 37. . Since the output of the NOT circuit 37 is high level, one input of the 2-input NOR circuit 29 is high level and the output of the 2-input NOR circuit 29 is low level. Therefore, the input of the NOR circuit 28 becomes low level, the other input of the 2-input NOR circuit 29 and the input of the NOT circuit 33 become high level, the output of the latch circuit 42A is held at low level, and the output of the latch circuit 42B is output. Is held low.

As shown in FIG. 3, when it is desired to rewrite the contents of the direction register after writing to the direction register once, the same operation as the initialization signal can be performed by writing to the write enable register. Then, the contents of the latch circuit 26C are set to the high level, and the latch circuit 2
Set the 6B output to low level.

In the first embodiment, the method of changing the input / output direction of the data input / output circuit is not limited to initialization, but in the second embodiment, the contents of the direction register can be rewritten by a program.

Example 3. FIG. 5 is a circuit diagram showing a third embodiment of the present invention. In the figure, the same thing as in FIG.
The same reference numerals are given and the description is omitted. 45 is a wiring connecting the latch circuits 26A and 26B. Figure 6
6 is a timing diagram for FIG.

In FIG. 5, the latch circuit 2 is connected by the wiring 45.
Since the content of 6B is input to the latch circuit 26A, the input of the latch circuit 26A changes every time writing to the direction register is performed. As described above, in the first embodiment, the only method for changing the input / output direction of the data input / output circuit is initialization, but in the third embodiment, the contents of the direction register can be rewritten by a program every odd number of times. .

Example 4. FIG. 7 is a circuit diagram showing Embodiment 4 of the present invention. In the figure, the same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. Reference numeral 46 is a 2-input NAND circuit that receives the output of the latch circuit 26B and the output of the NOT circuit 48, and 47 is the output of the 2-input NAND circuit 46, which is connected to the interrupt circuit block 49.

In the fourth embodiment, when the write signal WR to the conventional direction register becomes low level after the write to the direction register is once performed and the output 27 of the latch circuit 26B becomes high level, two inputs are made. NAND circuit 46
Goes to a low level, and this output is input to the interrupt circuit block 49 for interrupt processing. This makes it possible to detect when the program has run away due to noise or the like and the contents of the direction register have been rewritten after the writing to the direction register once.

Example 5. FIG. 8 is a circuit diagram showing a fifth embodiment of the present invention. The circuit configuration is similar to that of FIG. 7, and the output 47 of the 2-input NAND circuit 46 is the initialization circuit block 5
Connected to 0. In FIG. 8, after writing to the direction register once and the output 27 of the latch circuit 26B becomes high level, the conventional write signal W to the direction register W
When R becomes low level, the output of the 2-input NAND circuit 46 becomes low level, which is the initialization circuit block 50.
And an initialization signal is generated. As a result, if the program recklessly rewrites the contents of the direction register due to noise or the like after writing to the direction register once, initialization is forcibly performed.

Example 6. FIG. 9 is a circuit diagram showing a sixth embodiment of the present invention. In the figure, 51 and 52 are NOT circuits that constitute the delay circuit 60, and 53 is the delay circuit 60.
Is an EXOR circuit having two inputs and outputs of
Outputs the output of the EXOR circuit 53 and the output of the NOT circuit 56 to 2
This is a 2-input NOR circuit that receives the input.
The output of the circuit 54 is connected to the interrupt circuit block 57 via the NOT circuit 55. The input 59 of the delay circuit 60 is the contents of the direction register, and the input 58 of the NOT circuit 56 is the write signal to the direction register.

In FIG. 9, when the content 59 of the direction register changes due to noise or the like, one input of the EXOR circuit 53 changes and the other output becomes the output of the delay circuit 60. ns takes time. Therefore, the output of the EXOR circuit 53 is n
It goes low for s, at which time the write signal 58 to the direction register goes high and the output of the NOT circuit 56 goes low. Since both inputs of the 2-input NOR circuit 54 become low level, its output becomes high level,
The output of the NOT circuit 55 becomes low level. Therefore, at this time, the interrupt circuit block 57 has ten or more ns.
The low pulse of is input and interrupt processing is performed. Also,
When writing to the direction register, the write signal 58 to the direction register goes low and the output of the NOT circuit 56 goes high. At this time, 2 input NO
Since one input of the R circuit 54 is at high level, its output becomes low level and the output of the NOT circuit 55 becomes high level. Therefore, at this time, since the output of the NOT circuit 55 does not change, the interrupt processing is not performed. In this way, it is possible to detect that the contents of the direction register have changed due to noise or the like.

[0032]

According to the data input / output circuit of the first aspect of the present invention, since the write inhibit circuit is provided so that writing to the direction register can be performed only once, the effect that writing to the direction register cannot be performed repeatedly. Play.

According to the data input / output circuit of the second aspect of the invention, since the direction register is provided with the write enable register, the direction register can be written only when it is desired to change the contents of the direction register. Has the effect.

According to the data input / output circuit of the third aspect of the invention, there is an effect that writing to the direction register can be performed twice only when it is desired to change the contents of the direction register.

According to the data input / output circuit of the fourth aspect of the present invention, by providing the interrupt processing circuit,
It is possible to detect the number of times of writing to the direction register.

According to the data input / output circuit of the fifth aspect of the present invention, by providing the initialization signal generating circuit, the number of times of writing to the direction register can be detected and the contents of the direction register can be initialized. It has the effect of being able to.

According to the data input / output circuit of the sixth aspect of the invention, by providing the interrupt processing circuit,
It is possible to detect that the content of the direction register has changed.

As described above, according to the data input / output circuits of claims 1 to 6, it is possible to prevent or detect that the program recklessly rewrites the contents of the direction register due to noise or the like. Thus, it is possible to prevent a through current from flowing to the external circuit and the internal circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a timing diagram for FIG.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a timing diagram for FIG.

FIG. 5 is a circuit diagram showing a third embodiment of the present invention.

FIG. 6 is a timing diagram for FIG.

FIG. 7 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a fifth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a sixth embodiment of the present invention.

FIG. 10 is a circuit diagram of a conventional data input / output circuit.

11 is a timing diagram for FIG. 10. FIG.

[Explanation of symbols]

1, 2, 15, 16, 20, 21, 25, 28, 33,
34, 37, 38, 48, 51, 52, 55, 56 N
OT circuit 3, 4, 17, 18, 22, 23, 30, 31, 35,
36 switch circuit 5, 19, 32 N channel transistor 10 direction register 11 input / output circuit 13 data input / output circuit block 44 write enable register to direction register 49, 57 interrupt circuit block

[Procedure amendment]

[Submission date] July 15, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0005

[Correction method] Change

[Correction content]

[0005]

In the conventional data input / output circuit as described above, the program may run away due to noise or the like and a write signal may be output to the direction register, which may rewrite the contents of the direction register. Further, there is a problem that a through current may flow to an external circuit or an internal circuit.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction content]

According to another aspect of the data input / output circuit of the present invention, the interrupt processing circuit writes data to the direction register twice.
It is detected that the above has been performed .

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0017

[Correction method] Change

[Correction content]

In the data input / output circuit according to the fifth aspect, the contents of the direction register are initialized by writing to the direction register twice or more .

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction content]

Next, the write signal W to the direction register according to the first embodiment will be described. FIG. 2 shows a timing diagram for FIG. When a high-level initial signal is input to the N-channel transistor 19 for a certain period, the input of the NOT circuit 15 becomes low level,
The output of the OT circuit 15 becomes high level. As a result, the switch circuits 18 and 22 are turned on, and the switch circuits 17 and 2 are turned on.
Since 3 is turned off, the output of the latch circuit 26A is held at the high level. Since the switch circuit 22 is turned on at this time, the input of the NOT circuit 20 becomes high level, and the output 27 of the latch circuit 26B becomes low level. In the initial state, as shown in FIG. 2, WR is at high level, so the output of the 2-input NOR circuit 24 is at low level and the output W of the NOT circuit 25 is at high level. Next, when the write signal WR to the conventional direction register becomes low level,
The switch circuits 17 and 23 are turned on, the switch circuits 18 and 22 are turned off, and the output of the NOT circuit 15 becomes low level. At this time, the latch circuit 26B is held at a low level, the output of the latch circuit 26B 27 remains at a low level. As a result, the output 27 of the 2-input NOR circuit 24 becomes high level and the output W of the NOT circuit 25 becomes low due to the output 27 of the latch circuit 26B which is the input of the 2-input NOR circuit 24 and the write signal WR to the conventional direction register. It becomes a level. Further, when the write signal WR to the conventional direction register becomes high level, the switch circuits 17 and 2
3 turns off, switch circuits 18 and 22 turn on, and NOT
Since the output of the circuit 15 is low level, the output of the latch circuit 26A is held at low level. Switch circuit 2 at this time
Since 2 is turned on, the input of the NOT circuit 20 becomes low level and the output of the NOT circuit 20 becomes high level. Therefore, since the output 27 of the latch circuit 26B, which is the input of the 2-input NOR circuit 24, and the write signal WR to the conventional direction register are at high level, the 2-input NOR circuit 2
The output of 4 becomes low level, and the output W of the NOT circuit 25 becomes high level. As shown in FIG. 2, when the output 27 of the latch circuit 26B is at the low level, the output of W is determined by the input of WR.
When 7 is high level, the output of W is always high level regardless of the input of WR. As a result, in the first embodiment, writing to the direction register shown in FIG. 10 can be performed once but cannot be repeated.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Name of item to be corrected] 0022

[Correction method] Change

[Correction content]

Next, the permission register 44 will be described. In FIG. 3, when a high-level initialization signal is input to the N-channel transistor 32 for a certain period, NO
The input of the T circuit 28 goes low, and the output of the N-channel transistor 32 goes high. As a result, the switch circuits 31 and 35 turn on, and the switch circuits 30 and 3
Since 6 is turned off, the latch circuit 42A is held at the high level. At this time, since the switch circuit 35 is turned on, the input of the NOT circuit 33 becomes high level, and the NOT
The inputs of the circuit 38 and the 2-input NOR circuit 40 are at low level. Since the input of the NOT circuit 38 is low level, the output of the NOT circuit 37 also becomes low level, and the 2-input N
One input of the OR circuit 29 becomes low level. next,
When writing to the permission register, the write signal becomes low level, the switch circuits 30 and 36 are turned on, and the switch circuits 31 and 35 are turned off, so that the output of the NOT circuit 28 becomes low level. At this time, since the switch circuit 36 is on, the output 43 of the latch circuit 42B is held at the low level, and the NOT circuit 38 and the 2-input NOR circuit 40 are held.
The input to is still low. Further, when the write signal becomes high level, the switch circuit 30, 35 is turned off, the switch circuits 31 and 36 are turned on, the output of the NOT circuit 28 becomes low level, <br/> output of the latch circuit 42A is Holds low. At this time, since the switch circuit 35 is turned on, one input of the input and two-input NOR circuit 40 of the NOT circuit 38 inputs of the NOT circuit 33 becomes low level to the high level. NOT circuit 38
Since the input of is high level, the output of the NOT circuit 37 also becomes high level. Furthermore, since the delay circuits 42C are configured by the NOT circuits 37 and 38, there is a delay of several tens of nanoseconds from the input of the high level signal to the NOT circuit 38 until the output of the high level signal from the NOT circuit 37. . Since the output of the NOT circuit 37 is high level, one input of the 2-input NOR circuit 29 is high level and the output of the 2-input NOR circuit 29 is low level. Therefore, the input of the NOT circuit 28 becomes low level, the other input of the 2-input NOR circuit 29 and the input of the NOT circuit 33 become high level, and the output of the latch circuit 42A is held at high level and latched. The output of the circuit 42B is held at low level.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0031

[Correction method] Change

[Correction content]

[0031] In FIG 9, one of the input changes of the EXOR circuit 53 the contents 59 of the direction register due noise changes, the number 10 to the other input varies so as an output of the delay circuit 60 ns takes time. Therefore, the output of the EXOR circuit 53 is n
It goes low for s, at which time the write signal 58 to the direction register goes high and the output of the NOT circuit 56 goes low. Since both inputs of the 2-input NOR circuit 54 become low level, its output becomes high level,
The output of the NOT circuit 55 becomes low level. Therefore, at this time, the interrupt circuit block 57 has ten or more ns.
The low pulse of is input and interrupt processing is performed. Also,
When writing to the direction register, the write signal 58 to the direction register goes low and the output of the NOT circuit 56 goes high. At this time, 2 input NO
Since one input of the R circuit 54 is at high level, its output becomes low level and the output of the NOT circuit 55 becomes high level. Therefore, at this time, since the output of the NOT circuit 55 does not change, the interrupt processing is not performed. In this way, it is possible to detect that the contents of the direction register have changed due to noise or the like.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0034

[Correction method] Change

[Correction content]

According to the data output circuit in the invention of claim 3 wherein, an effect that it <br/> by performing twice writing to direction register only if you want to change the contents of the direction register.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0035

[Correction method] Change

[Correction content]

According to the data input / output circuit of the fourth aspect of the present invention, by providing the interrupt processing circuit,
It is possible to detect that writing to the direction register is performed twice or more .

[Procedure Amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0036

[Correction method] Change

[Correction content]

According to the data input / output circuit of the fifth aspect of the present invention, by providing the initialization signal generating circuit, it is detected that writing to the direction register is performed twice or more. This has the effect that the contents of the direction register can be initialized.

[Procedure Amendment 10]

[Document name to be amended] Statement

[Correction target item name] Explanation of code

[Correction method] Change

[Correction content]

[Explanation of Codes] 1, 2, 15, 16, 20, 21, 25, 28, 33,
34, 37, 38, 48, 51, 52, 55, 56 N
OT circuits 3, 4, 17, 18, 22, 23, 30, 3
1, 35, 36 switch circuit, 5, 19, 32 N-channel transistor, 10 direction register, 11 input / output circuit, 13 data input / output circuit block, 44 direction register write enable register, 49, 57 interrupt circuit block, 24 , 29, 40, 54 2 inputs N
OR circuit, 41, 46 2-input NAND circuit, 53
2-input EXOR circuit, 60, 42C delay circuit, 26
A, 26B, 26C, 42A, 42B Latch circuit, 1
2 external input terminals, 13 data input / output circuit block,
14 data buses, 50 initialization circuit blocks, 58 ways
Write signal to the direction register, out of the 59 direction registers
Yong.

Claims (6)

[Claims] 1. A data input / output circuit provided with a direction register for determining a direction of data input / output, comprising a write inhibit circuit which can write to the direction register only once and cannot be repeatedly written. Data input / output circuit. 2. The data input / output circuit according to claim 1,
A data input / output circuit, wherein a write enable register is provided so that the direction register can be written when the input / output direction of the direction register is once set and then the direction of the input / output direction can be changed. 3. The data input / output circuit according to claim 1,
When it is desired to change the input / output direction of the direction register after setting the input / output direction of the direction register once, a circuit is provided which can change the contents of the direction register by writing to the direction register twice. Data input / output circuit. 4. A data input / output circuit having a direction register for determining the direction of data input / output, wherein a circuit for restricting writing to the direction register only once is provided, and a program runs away due to noise and the A data input / output circuit, characterized in that a circuit for performing an interrupt process when writing to the direction register is provided so that it is possible to detect that writing to the direction register is performed twice or more. 5. A data input / output circuit having a direction register for determining the direction of data input / output, wherein a circuit for restricting writing to the direction register only once is provided, and a program runs away due to noise and the A data input / output circuit comprising a circuit for generating an initialization signal when writing is performed to the direction register, forcibly initializing the input / output direction of the direction register. 6. A data input / output circuit having a direction register for determining the direction of data input / output, comprising an interrupt processing circuit for detecting that the content of the direction register is changed by noise or the like. Input / output circuit.