JP2699431B2 - register - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a register, and more particularly, to a multi-bit register connected to a plurality of systems of buses.

[Conventional technology]

In a microprocessor or the like, a multi-bit register connected to a plurality of systems of buses is used. FIG. 4 is a schematic circuit diagram showing the configuration of an 8-bit register connected to two 8-bit data buses as a conventional example of such a register.

In the figure, reference numeral 1 denotes an 8-bit register, which is composed of a first unit register 1-1 to an eighth unit register 1-8, each of which is a 1-bit register.

A and B are first and second data buses each having an 8-bit configuration, and each of bits 0 (1-a, 1-b) to
It is composed of bits 7 (8-a, 8-b). Then, the first unit register 1-1 stores bit 0 (1-a) of the first data bus A and bit 0 (1-a) of the second data bus B.
In (1-b), the second unit register 1-2 stores bit 1 (2-a) of the first data bus A, bit 1 (2-b) of the second data bus B, and so on. Are respectively connected to the first and second data buses B.
Are connected to corresponding bits.

Each of the unit registers 1-1 to 1-8 has the same configuration. For example, the first unit register 1-1 includes two inverters.
It is composed of two, three, three transistors 4, 5, 6, two clocked inverters 7, 8, and the like.

More specifically, one end of transistor 4 is connected to bit 0 (1-a) of first data bus A, one end of transistor 5 is connected to bit 0 (1-b) of second data bus B, The other ends of the transistors 4 and 5 are connected to one end of the transistor 6 and the input terminal of the inverter 2, and the output terminal of the inverter 2 is connected to the input terminal of the inverter 3 and the clocked inverter 7,
8 is connected to the input terminal, and the output terminal of the inverter 3 is connected to the other end of the transistor 6. The output end of clocked inverter 7 is connected to bit 0 (1) of first data bus A.
At -a), the output end of the clocked inverter 8 is connected to the bit 0 (1-b) of the second data bus B, respectively.

The first gate (not shown) is connected to the gate of the transistor 4.
Signal WR obtained by decoding the address bus value of
a is connected to the gate of the transistor 5 by a second
Signal WR obtained by decoding the address bus value of
b is given respectively. At the gate of transistor 6,
A signal (▲) that becomes “1” when both the write signal WRa and the write signal WRb are “0” is given. Further, a read signal RDa obtained by decoding a value of a first address bus (not shown) and a read signal RDb obtained by decoding a value of a second address bus are provided to the gates of the clocked inverters 7 and 8, respectively. Have been.

Similarly, the other unit registers 1-2 to 1-8 have one ends of the transistors 4, 5 and the output ends of the clocked inverters 7, 8 connected to corresponding bits of the first and second data buses B, respectively. I have.

The operation of the conventional register having such a configuration will be described below.

When reading the value of the first unit register 1-1 onto the first data bus A, the clocked inverter 7 is turned on by setting the read signal RDa to "1" through a first address bus (not shown). Thereby, the first data bus A
The data of the first unit register 1-1 is read to bit 0 (1-a) of the first register.

In this case, at the same time, the values of the second unit register 1-2 to the eighth unit register 1-8 are read to bit 1 (2-a) to bit 7 (8-a) of the first data bus A. .

On the other hand, from the first data bus A to the first unit register 1
To write a value to -1, bit 0 of the first data bus A
The value to be written is set in (1-a), and the transistor 4 is turned on by setting the write signal WRa to "1" through a first address bus (not shown). As a result, a signal is transmitted from the bit 0 (1-a) of the first data bus A via the transistor 4, and the value is written to the first unit register 1-1.

In this case, the bit 1 of the first data bus A is simultaneously stored in the second unit register 1-2 to the eighth unit register 1-8.
The values of (2-a) to bit 7 (8-a) are written.

The same procedure as described above applies to the case where the value is read from the first unit register 1-1 to the second data bus B and the case where the value is written to the first unit register 1-1 from the second data bus B. .

As described above, in the conventional register, when writing a value to the first unit register 1-1, the other unit register 1 must be written.
The value of either "0" or "1" is simultaneously written into -2 to 1-8. Therefore, when it is necessary to rewrite only the value of the unit register 1-1, it is necessary to rewrite the same value as before the rewriting to the unit registers 1-2 to 1-8, which is called a read-modify-write cycle. The reading and writing of a series of data is performed continuously. FIG. 5 is a timing chart showing such a procedure.

In FIG. 5, during the period when the read signal RDa is "1", the unit registers 1-1 to 1-1- are connected to the first data bus A.
The value of 8 is read. In the case of FIG. 5, the unit register 1-
All four bits 1 to 1-4 are "1", and the unit register 1-5
The four bits 1-8 are all “0”, and the value of the first data bus A is “0F ₁₆ ” in hexadecimal notation.

Thereafter, a first central processing unit (not shown) connected to the first data bus A outputs a value “0E ₁₆ ” in which the bit 0 (1-a) is changed to “0” to the first data bus A. Then, the write signal WRa is set to “1”. As a result, "0" is written into the first unit register 1-1, and its value is rewritten from "1" to "0". Since the same value as before is written in the other unit registers 1-2 to 1-8, no rewriting is performed.

Through such processing, it is possible to rewrite only the value of the unit register 1-1.

[Problems to be solved by the invention]

By the way, when each bit of the register shown in FIG. 4 is used as a so-called semaphore flag for synchronizing processing with a first central processing unit and a second central processing unit (not shown), It is possible that both the first central processing unit and the second central processing unit asynchronously set the value of the unit register. However, in the above-described conventional register, when settings for different unit registers are performed simultaneously, there is no guarantee that the respective settings are correctly performed. Hereinafter, description will be made with reference to the timing chart of FIG.

For example, a first central processing unit (not shown) rewrites the value of the first unit register 1-1 from “1” to “0” through the first data bus A, and a second central processing unit (not shown) Through the data bus B of the eighth unit register 1-
When a read-modify-write cycle for rewriting the value of 8 from “0” to “1” occurs simultaneously, the read signal RDa,
The write signal WRa and the first data bus A operate in the same manner as in the example shown in FIG. And the read signal
The read signal RDb becomes “1” during a period between the period when RDa is “1” and the period when the write signal WRa is “1”, and the hexadecimal number “0F ₁₆ ” is placed on the second data bus B. Read and write signal WRa is "1"
Is changed from "0" to "0", the second central processing unit (not shown) rewrites bit 4 (5-b) of the hexadecimal number "0F ₁₆ " to "1", that is, "1F ₁₆ " to the second data. Output to the bus B and set the write signal WRb to “1”.

At this time, the fifth unit register 1-5 is rewritten from “0” to “1”, but the first unit register 1-1 is rewritten from “1” to “0” and then “1” again. Will be rewritten.

As described above, simply connecting the conventional register to the two buses causes unexpected data change for each of the two central processing units when the read-modify-write cycle occurs simultaneously. there is a possibility.

The present invention has been made in view of the above circumstances, and when changing the value of a register, the value can be changed by merely writing data without executing a read-modify-write cycle. The purpose is to provide registers.

[Means for solving the problem]

In the register of the present invention, the set / reset signal of each unit register constituting the register is made to correspond to the result of decoding all the bits of the data bus and the write signal to the register.

[Action]

The register of the present invention decodes a write signal to the data bus and the register, and when a write signal to the register occurs in a state where all bits of the data bus other than the bit to which a certain unit register is connected are “1”. Generates a reset signal for that unit register. If a write signal is issued to a register while all bits of the data bus other than the bit to which a certain unit register is connected are “0”, the unit register is reset. A set signal is generated.

(Example of the invention)

Hereinafter, the present invention will be described in detail with reference to the drawings showing examples.

FIG. 1 is a circuit diagram showing a configuration of a register according to the present invention.

In FIG. 1, reference numeral 1 denotes a register of the present invention, which has an 8-bit configuration. The register of the present invention includes a first unit register 1-1 to an eighth unit register 1-8, each of which is a 1-bit register.

A and B are first and second data buses each having an 8-bit configuration, and each of bits 0 (1-a, 1-b) to
It is composed of bits 7 (8-a, 8-b). Then, the first unit register 1-1 stores bit 0 (1-a) of the first data bus A and bit 0 (1-a) of the second data bus B.
(1-b). Similarly, the second unit register 1-2 stores the bit 1 (2-bit) of the first data bus A in the same manner.
a) and bit 1 (2-b) of the second data bus B,.
And so on.

The first data bus A is connected to the signal lines 1-c to 8-c.
Of the second data bus B are applied to the signal lines 1-d to 8-d. .
These inverted signals can be easily generated by using an inverter.

Each of the unit registers 1-1 to 1-8 is composed of two inverters 2, 3, two clocked inverters 7, 8 and 32 transistors each constituting a latch.

For example, in the first unit register 1-1, the input terminal of the inverter 2 is connected in series with the transistors 4-1, 2-e, 3-e ... 8-e, and the output terminal of the inverter 3 is connected to 5-1 and 5-1. 2−g, 3
-G ... 8-g, the output terminal of the inverter 2 is connected in series with the transistors 4-2,2-f, 3-f ... 8-f, and the input terminal of the inverter 3 is 5-2, 2-h, 3-h ... 8-
h are connected in series.

The output terminal of the clocked inverter 7 is at bit 0 (1-a) of the first data bus A, and the output terminal of the clocked inverter 8 is at bit 0 (1-a) of the second data bus B.
b), both clocked inverters 7, 8
Are input terminals of the transistor 2 and the output terminal of the transistor 3.
Is connected to the input terminal of

A write signal WRa obtained by decoding the value of a first address bus (not shown) is supplied to the gates of the transistors 4-1 and 4-2.
A write signal WRb obtained by decoding a value of a second address bus (not shown) is applied to each of the gates 2. Further, a read signal RDa obtained by decoding a value of a first address bus (not shown) and a read signal RDb obtained by decoding a value of a second address bus are provided to the gates of the clocked inverters 7 and 8, respectively. Have been.

Note that the write signal WR is applied to the transistors 4-1 and 4-2.
a, the respective bits of the first data bus A are supplied to the gates 2e to 8-e, and the inverted signals of the respective bits of the first data bus A are supplied to the gates to 2f to 8-4. ing. These transistors connect the value of the first data bus A and the write signal to the latch constituted by the inverters 2 and 3.
A transistor for setting the value of “1” or “0” according to the state of WRa, and transistors 4-1 and 2-e
If all of .about.8-e are on, the latch is set to "0". If all of the transistors 4-2 and 2-f to 8-f are on, the latch is set to "1". You. Otherwise, the value of the latch does not change.

Similarly, a write signal is applied to transistors 5-1 and 5-2.
WRb is the gate of each of the bits of the second data bus B in 2-g to 8-g, and the inverted signal of each bit of the second data bus B in the gates of 2-g to 8-h. Has been given. These transistors connect the latch constituted by the inverters 2 and 3 to the value of the second data bus B and the write signal.
By setting or resetting according to the state of WRb, a set / reset signal generation circuit for writing a value of “1” or “0” is configured. And the transistor 5-
If all of the transistors 1 and 2-g to 8-g are on, the latch is set to "0". If all of the transistors 5-2 and 2-h to 8-h are on, the latch is set. Is set to “1”. Otherwise, the value of the latch does not change.

Hereinafter, the operation of the register of the present invention having the above configuration will be described with reference to the timing chart of FIG.

In the initial state, the first unit register 1-1 is "0"
It is assumed that the value of each of the eighth unit registers 1-8 is set to "1".

The first unit register 1- through the first data bus A
When rewriting "1" to "1", the first data bus A
To Decimal "FE _16", to "1" then the write signal WRa. As a result, all of the transistors 4-1 and 2-e to 8-e are turned on, the output of the inverter 3 is forcibly set to "0", and the inverters 2 and 3 of the unit register 1-1 are configured. The latched value of the latch is inverted, and the first unit register 1
-1 is rewritten to "0".

At this time, the other unit registers 1-2 to 1-8 store the bit 0 (1-a) of the first data bus A and the bit 1 (2-c) to the inverted bit of the first data bus A. Bit 7 (8
Since -c) is "0", at least one of the transistors connected in series is turned off, so that the respective values are not rewritten.

Eighth unit register 1- through the second data bus B
8 is rewritten to "1", the second data bus B
The base number may be "80 ₁₆ ", and the write signal WRb may be set to "1".

Thus, as in the case of the unit register 1-1, only the eighth unit register 1-8 is rewritten to "1".

The table in FIG. 3 shows the values to be set on the first data bus A or the second data bus B and the first unit registers 1-1 to 1-1.
It shows a state of a change in the value of the eighth unit register 1-8.

As is apparent from the table of FIG. 3, only one bit of the data bus is "1" and all other bits are "0", or conversely, only one bit is "0" and all other bits are "0". When it is “1”, only one bit of the unit registers 1-1 to 1-8 becomes “1” or “0”, and the other bits do not change. When all the bits of the data bus are "1" or "0", all the bits of the unit registers 1-1 to 1-8 simultaneously become "0" or "1". When the data bus has a value other than the above, the values of the unit registers 1-1 to 1-8 do not change.

Therefore, no matter what timing data is written from the first data bus A and the second data bus B, the process of simultaneously rewriting the values of the same unit registers 1-1 to 1-8. Otherwise, unexpected rewriting of register values does not occur.

In the above embodiment, the MOS integrated circuit constituted by the inverter, the transistor and the clocked inverter has been described. However, it is a matter of course that another logic integrated circuit or a combination thereof constitutes a circuit having the same function. It is possible.

In the above embodiment, the description has been given of the 8-bit register. However, the present invention is not limited to this.

〔The invention's effect〕

As described above, according to the register of the present invention,
The register is set / reset by a signal obtained as a result of decoding all bits of the data bus and a write signal to the register. As a result, "1" or "0" is assigned to each of the unit bits constituting the register. Since the value of "is written, unexpected data rewriting can be avoided even when data is simultaneously written from a plurality of buses.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the register of the present invention, FIG. 2 is a timing chart thereof, and FIG. 3 is a diagram showing the value of each bit of a data bus and the register when writing data to the register of the present invention. FIG. 4 is a circuit diagram showing the configuration of a conventional register, FIG. 5 is a timing chart of the read-modified-write cycle, and FIG. 6 is a read / write cycle of the conventional register. 10 is a timing chart showing an operation state when a modified write cycle is simultaneously generated from two buses. A: first data bus, B: second data bus, 1
... register, 1-1 to 1-8 ... unit register, 2, 3
…… Inverter, 4-1,4-2,5-1,5-2,2-e to 8-e,
2-f to 8-f, 2-g to 8-g, 2-h to 8-h... Transistors The same reference numerals in each drawing denote the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A register comprising n unit registers connected to a plurality of n-bit data buses and corresponding to n bits of the plurality of n-bit data buses, wherein each of the unit registers is For each of the n-bit data buses, the bit corresponding to itself of the corresponding n-bit data bus is “1”, all other bits are “0”, and the write signal is applied. In the case where "1" is written to itself, the corresponding bit of the corresponding n-bit data bus is "0", all other bits are "1", and a write signal is given A write circuit for writing "0" to itself, and a read circuit for reading own data into corresponding bits of each n-bit data bus when a read signal is applied. .