JPS6398733A - Control system for arithmetic circuit - Google Patents

Abstract

PURPOSE:To omit a decoder and to shorten the arithmetic time by using plural control bits of an arithmetic microinstruction to control directly each part of an arithmetic circuit. CONSTITUTION:An arithmetic microinstruction contains 16 bits and the higher order 4 bits (12-16) of this microinstruction show an operation field OP. Then the value is supplied to instruct that the microinstruction shows an arithmetic mode. The lower order 7 bits (0-6) of the microinstruction are used as control bits A-G and other 5 bits (7-11) are not used by the arithmetic microinstruction. The bit A decides whether or not the arithmetic result is stored in an arithmetic register 15 or 16. The bit B instructs a register 15 or 16 that stores the arithmetic result. The bit C instructs the selection of an inverting circuit 18 and the bit D instructs the selection of an adding circuit 20. Then the bit E instructs the inversion/subtraction or no-inversion/addition of the data on a selector 22.

Description

[Detailed Description of the Invention] [Summary] The present invention is a trunk circuit III control method, and the circuit configuration is is simple and reduces calculation time.

[Industrial application field]

The present invention relates to an arithmetic circuit IQwJ method, and more particularly to an arithmetic circuit control method for controlling an arithmetic circuit according to a microinstruction to obtain an arithmetic result.

Programmed normal instructions, ie macro instructions, are developed into micro instructions and executed by a processing device such as a CPU.

It is desired that each microinstruction in the CPU be executed at high speed, and furthermore, it is desired that the number of microinstruction pits be small and the circuit configuration of the CPU be simple.

(Prior Art) Vertical microinstructions are used as arithmetic microinstructions for performing conventional numerical operations.

A vertical microinstruction defines an operation to be executed using a code stored in a bit field, and a decoder attached to the arithmetic circuit in the CPU decodes the code in the bit field to identify the operation and execute the instruction. Running.

[Problem that the invention seeks to solve]

In order to control an arithmetic circuit using the conventional vertical arithmetic micro-instructions mentioned above, a decoder is required along with the arithmetic circuit, which complicates the circuit configuration and requires time to decode the instructions. Therefore, there were problems such as a long calculation time.

It is also possible to make the microinstructions horizontal microinstructions that do not require decoding, but microinstructions include data transfer instructions in addition to calculation instructions.

Because there are various instructions such as bit manipulation instruction 1, the number of bits of microinstructions becomes large. - The storage capacity of the memory that stores microinstructions increases, and the wiring from each bit of the microinstructions to the arithmetic circuit increases. This results in problems such as complicated wiring and the need for a large area.

The present invention has been made in view of the above points, and it is an object of the present invention to provide an arithmetic circuit control method with a simple circuit configuration and short calculation time.

[Means to solve the problem]

In the arithmetic control method of the present invention, an operation microinstruction is provided with an operation field that indicates that the microinstruction is an arithmetic instruction, and a plurality of control bits for controlling an arithmetic circuit, and each of the plurality of control bits is directly controlled. Controls each part of the arithmetic circuit.

[Effect]

In the present invention, each part of the arithmetic circuit is directly controlled by each of the plurality of control bits of the arithmetic microinstruction, and there is no need to decode the arithmetic microinstruction.

〔Example〕

FIG. 2 shows a block system diagram of an embodiment of an arithmetic circuit to which the method of the present invention is applied. In the figure, 10 is a data bus through which 16-bit microinstructions are received, 11 and 12 are buses through which control signals from the sequencer and decoder are received, and 13 is a data bus through which calculation results are output.

The arithmetic microinstruction has a 16-bit configuration as shown in FIG. The upper 4 bits of the microinstruction (bits 12 to
16) is an operation field OP, which has a predetermined value indicating that this microinstruction is in an operation mode. The lower 7 bits (bits O to 6) are control bits A to G (hereinafter simply referred to as "bits A to GJ"), and the remaining five bits (bits 7 to 11) are not used by microinstructions for calculation.

Bit A above stores the operation result in operation register 15 or 1.
6 indicates whether to store or not, and is supplied to the multiplexer 17, where v □ v indicates non-store, and 717 indicates store.

Bit B indicates which of the registers 15 and 16 the operation result is to be stored in, and is supplied to the multiplexer 17 so that W Q T indicates storage to register 15 and vlv indicates storage to register 16 .

Bit C instructs whether or not to selectively output the output of the inverting circuit 18 as a calculation result, and is supplied to the selector 19 to
QY indicates non-selection, and '17 indicates selection.

Bit D instructs whether or not to selectively output the output of the adder circuit 20 as the calculation result, and is supplied to the selector 19 and outputs W.
Q Y indicates non-selection, vlv indicates selection.

Bit E inverts or subtracts the data in selector 22, or
or non-inversion or addition, and is supplied to the inversion circuit 18 and the addition circuit 20, 70 is non-inversion in the inversion circuit 18 and addition is in the addition circuit 20, and '11 is inversion circuit 18.
Instructs inversion at , and subtraction at addition circuit 20 .

Bit G is supplied to selector 21 and register 15.1
6 Indicate which data to select, and press V Q ? 117 instructs selection of data in register 15, and 117 instructs selection of data in register 16.

Bit F is supplied to the selector 22 together with bit G and instructs which of the data of register 15.16 and constant data v17 to select.If bit F is 717, it instructs selection of constant data v1v, and bit F is v
Ov and bit G is v. If Ov, it instructs the selection of data in register 15, and bit F is 10v and bit G is vl.
If it is v, it instructs selection of data in register 16.

Further, bits C-F are supplied to the selector 19 to instruct selective output of the calculation result, and bits C-F are 'ooooo'.
If so, the output of the AND circuit 23 is selectively output, and '00
01', the output of the OR circuit 24 is selectively output, and '
If it is 0010', the output of the XOR circuit 25 is selectively output.

Note that an AND circuit 23, an OR circuit 24, an XOR circuit 25
Each of the registers 15 and 16 obtains and outputs logical product, logical sum, and exclusive logical operations of the respective data. The above-mentioned inverting circuit 18, addition circuit 20, AND circuit 23, OR circuit 24,
Each of the XOR circuits 25 is composed of static circuits that can operate in parallel. Further, the inverting circuit 18 is connected to the selector 2
An exclusive logical operation is performed on the data from selector 22 and data in which all pits have the same value as bit E, and the data from selector 22 is inverted or non-inverted. The adder circuit 20 adds the data from the selector 21 and the data from the inversion circuit 18, and adds bit E to the least significant bit of the addition result as a carry.When bit E is vlv, the data from the selector 21 is added. The two's complement of the data in the selector 22 is added and subtracted.

During one period from the rise of the clock signal φ1 shown in FIG. 3(A) supplied from the bus 11 shown in FIG. It is assumed that a microinstruction has been received.

In this case, the selector 21 selects the data in the register 15 and supplies it to the adder circuit 20. The selector 22 selects the data in the register 16 , this data is inverted by the inverting circuit 18 and supplied to the adder circuit 20 , and the adder circuit 20 subtracts the data in the register 16 from the data in the register 15 . Further, the selector 19 selects the output of the adder circuit 20 and supplies it to the data bus 13 and the latch circuit 30.

The latch circuit 30 is connected to the buses 11 and 12 respectively as shown in FIG. 3(B).
, (C) are supplied with the clock signal φ2 shown in FIG. The data is passed through, and the data from the selector 19 is latched and supplied to the multiplexer 17 at the falling edge of the control signal ACCFB.

The latch circuit 31 also uses the clock signal φ2 and the control signal A.
CCF, latches bits A and B supplied from data bus 10 at the falling edge of signal ACCFB, and supplies them to multiplexer 17.

The multiplexer 17 is supplied with the clock signal φ1 and the i control signal ARWS from the bus 11, and when the control signal ARWS becomes H level as shown in FIG. 3(E) in the next cycle of the operation execution cycle, the latch circuit 31 Since the bits A and B supplied from the latch circuit 30 are v107, the data of the operation result from the latch circuit 30 is supplied to the register 15 and stored therein.

In this way, the bits A to G of the operation microinstruction are selected as shown in the right column of FIG. 4, and the operations in the left column are performed. In FIG. 4, ACCA and AccB are registers 15.
16, and CMP AccA and AccB represent the comparison of data in registers 15 and 16, respectively. or represents any value.

In this way, since each part of the arithmetic circuit is directly controlled by each of the control bits, that is, bits A to G of the arithmetic microinstruction, there is no need to provide a decoder, the circuit configuration is simple, and the time required to decode the instructions is unnecessary. The time can be reduced accordingly.

Furthermore, compared to the conventional method using horizontal microinstructions, the storage capacity of the memory for storing microinstructions is small, and the wiring is simple and requires a small area.

〔Effect of the invention〕

As described above, according to the present invention, there is no need for a decoder for decoding commands, the circuit configuration is simplified, and the time required for decoding commands is not required, so that the performance time can be shortened, which is extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of an arithmetic microinstruction to which the method of the present invention is applied. FIG. 2 is a block diagram of an embodiment of an arithmetic circuit to which the method of the present invention is applied. 2 is a signal waveform diagram of each part of the circuit shown in FIG. 4, and FIG. 4 is a diagram showing the relationship between bits A to G shown in FIG. 1 and an arithmetic expression. In the figure, 15.16 is a register, 17 is a multiplexer, 18 is an inversion circuit, 19.21.22 is a selector, 20 is an addition circuit, 23 is an AND circuit, 24 is an OR circuit, 25 is an XOR circuit, 30.31 is a latch circuit, OP is an operation field, and A to G are control bits.

Claims (1)

[Claims] Controlling each part of an arithmetic circuit according to an arithmetic microinstruction,
In an arithmetic circuit control method that performs operations such as addition, subtraction, inversion, logical sum, logical product, exclusive OR, etc. of data and obtains a calculation result according to the calculation microinstruction, the calculation microinstruction includes the microinstruction in the calculation microinstruction. It is characterized by providing an operation field for indicating that is an arithmetic instruction, and a plurality of control bits for controlling the arithmetic circuit, and each of the plurality of control bits directly controlling each part of the arithmetic circuit. Arithmetic circuit control method.