KR950002080A - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR950002080A
KR950002080A KR1019930010622A KR930010622A KR950002080A KR 950002080 A KR950002080 A KR 950002080A KR 1019930010622 A KR1019930010622 A KR 1019930010622A KR 930010622 A KR930010622 A KR 930010622A KR 950002080 A KR950002080 A KR 950002080A
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KR
South Korea
Prior art keywords
gate oxide
forming
oxide layer
active region
mos transistor
Prior art date
Application number
KR1019930010622A
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Korean (ko)
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KR960012588B1 (en
Inventor
김진오
Original Assignee
박성규
대우통신 주식회사
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Application filed by 박성규, 대우통신 주식회사 filed Critical 박성규
Priority to KR93010622A priority Critical patent/KR960012588B1/en
Publication of KR950002080A publication Critical patent/KR950002080A/en
Application granted granted Critical
Publication of KR960012588B1 publication Critical patent/KR960012588B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 저전압 및 고전압 모스트랜지스터들을 동일한 반도체 기판상에 형성하는 반도체장치의 제조방법에 관한 것으로서, 제1 및 제2활성영역들을 제외한 반도체 기판에 표면에 필드산화막을 형성하고 제1 및 제2활성영역들의 표면에 제 1 게이트산화막을 형성한다. 그리고, 고전압 모스트랜지스터가 형성될 제 2활성영역들을 제외한 저전압 모스트랜지스터가 형성될 활성영역의 제 1 게이트산화막을 제거한 후, 재차, 제1 및 제 2 활성영역들의 표면에 제 2 게이트산화막을 형성한다. 따라서, 고전압모스트랜지스터의 게이트산화막을 고내압을 갖도록 형성하면서 저전압 모스트랜지스터의 게이트산화막을 얇게 형성할 수 있으므로 고집적화를 이룰 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which low voltage and high voltage morph transistors are formed on the same semiconductor substrate. A first gate oxide film is formed on the surfaces of the regions. After removing the first gate oxide layer of the active region in which the low voltage MOS transistor is to be formed except for the second active regions in which the high voltage MOS transistor is to be formed, a second gate oxide layer is formed on the surfaces of the first and second active regions. . Therefore, the gate oxide film of the high voltage MOS transistor can be formed to have a high breakdown voltage, and the gate oxide film of the low voltage MOS transistor can be formed thinly, thereby achieving high integration.

Description

반도체 장치의 제조방법Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도(A) 내지 (D)는 본 발명에 따른 동일기판상에 저전압 모스트랜지스터와 고전압 모스트랜지스터를 가지는 반도체 장치의 제조공정도.2A to 2D are manufacturing process diagrams of a semiconductor device having a low voltage MOS transistor and a high voltage MOS transistor on the same substrate according to the present invention.

Claims (3)

제 1 도전형의 반도체 기판의 표면에 제1 및 제 2 활성영역들을 한정하는 필드 산화막들을 형성하는 공정과, 상기 제 1 활성영역을 제외한 제 2 활성영역의 표면에 제 1 게이트 산화막을 형성하는 공정과, 상기 제1 및 2 활성영역들의 표면에 제 2 게이트 산화막을 형성하는 공정과, 상기 제1 및 제2활성영역들의 제 2 게이트 산화막들의 상부에게이트 전극들을 형성하는 공정과, 상기 게이트 전극들 양측에 반도체 기판에 상기 제 1 도전형과 반대도전형인 제 2 도전형의 소오스 및 드레인 영역들을 형성하는 공정을 구비한 동일한 반도체 기판상에 저전압 및 모스트랜지스터를 가지는반도체 장치의 제조방법.Forming field oxide films defining first and second active regions on a surface of a first conductivity type semiconductor substrate, and forming a first gate oxide film on a surface of a second active region except for the first active region And forming a second gate oxide layer on the surfaces of the first and second active regions, forming gate electrodes on the second gate oxide layers of the first and second active regions, and forming the gate electrodes. A method for manufacturing a semiconductor device having a low voltage and a MOS transistor on the same semiconductor substrate having a process for forming source and drain regions of a second conductivity type opposite to the first conductivity type on both sides of the semiconductor substrate. 제 1 항에 있어서, 상기 제2 활성영역의 표면에 제 1 게이트 산화막을 형성하는 공정은, 상기 제1 및 제2활성영역들의 표면에 제 1 게이트 산화막을 형성하는 단계와, 상기 제 1 활성영역 표면에 형성된 제 1 게이트 산화막을 포토리쏘그래피방법으로 제거하는 단계로 이루어진 반도체 장치의 제조방법.The method of claim 1, wherein the forming of the first gate oxide layer on the surface of the second active region comprises: forming a first gate oxide layer on the surfaces of the first and second active regions; And removing the first gate oxide film formed on the surface by a photolithography method. 제 2 항에 있어서, 상기 제1 활성영역의 제 1 게이트 산화막을 제거한 후 상기 제1 활성영역 표면에 남아있는 제 1 게이트 산화막의 표면을 소정 두께 제거하는 단계를 더 구비한 반도체 장치의 제조방법.The method of claim 2, further comprising removing a predetermined thickness of a surface of the first gate oxide layer remaining on the surface of the first active region after removing the first gate oxide layer of the first active region. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR93010622A 1993-06-11 1993-06-11 Semiconductor device having thin film transistor & method of manufacturing the same KR960012588B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR93010622A KR960012588B1 (en) 1993-06-11 1993-06-11 Semiconductor device having thin film transistor & method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR93010622A KR960012588B1 (en) 1993-06-11 1993-06-11 Semiconductor device having thin film transistor & method of manufacturing the same

Publications (2)

Publication Number Publication Date
KR950002080A true KR950002080A (en) 1995-01-04
KR960012588B1 KR960012588B1 (en) 1996-09-23

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KR93010622A KR960012588B1 (en) 1993-06-11 1993-06-11 Semiconductor device having thin film transistor & method of manufacturing the same

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KR960012588B1 (en) 1996-09-23

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