KR950000520B1 - Bias ic - Google Patents
Bias ic Download PDFInfo
- Publication number
- KR950000520B1 KR950000520B1 KR1019920002221A KR920002221A KR950000520B1 KR 950000520 B1 KR950000520 B1 KR 950000520B1 KR 1019920002221 A KR1019920002221 A KR 1019920002221A KR 920002221 A KR920002221 A KR 920002221A KR 950000520 B1 KR950000520 B1 KR 950000520B1
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- voltage
- bias
- component
- integrated circuit
- resistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Abstract
Description
제 1a 도 및 제 1b 도는 종래의 바이어스 회로를 나타내는 것이다.1A and 1B show a conventional bias circuit.
제 2 도는 본 발명에 따른 바이어스 회로를 나타내는 것이다.2 shows a bias circuit according to the present invention.
제 3a 도는 본 발명에 따른 바이어스 회로의 공정상에서 발생하는 기생 트랜지스터를 포함하는 회루 구성을 나타내는 것이다.3A illustrates a circuit configuration including parasitic transistors generated in the process of the bias circuit according to the present invention.
제 3b 도는 본 발명에 따른 바이어스 회로의 수직적인 구조를 나타내는 것이다.3b shows a vertical structure of a bias circuit according to the present invention.
제 3c 도는 본 발명에 따른 바이어스 회로의 테브닌 등가 회로를 나타내는 것이다.Figure 3c shows a Thevenin equivalent circuit of the bias circuit according to the invention.
제 3d 도는 제 3c 도에 나타낸 회로의 베이스-에미터 루프를 등가적으로 나타낸 등가 회로를 나타내는 것이다.FIG. 3d shows an equivalent circuit equivalently representing the base-emitter loop of the circuit shown in FIG. 3c.
본 발명은 바이어스 회로에 관한 것으로, 특히 CMOS 집적회로내에서의 바이어스 집적회로에 관한 것이다.The present invention relates to a bias circuit, and more particularly to a bias integrated circuit in a CMOS integrated circuit.
종래의 CMOS 집적회로내에서의 바이어스 회로는 제 1a 도에 나타낸 바이어스 회로에 제 1b 도에 나타낸 일정 전압 발생 회로가 추가로 접속되어야 한다. 따라서, 그 회로 구성이 복잡하여 집적화시에 레이아웃 면적을 많이 차지하는 단점이 있었다.The bias circuit in the conventional CMOS integrated circuit must be further connected to the bias circuit shown in FIG. 1A with the constant voltage generating circuit shown in FIG. 1B. Therefore, the circuit configuration is complicated, which takes up a lot of layout area at the time of integration.
따라서, 본 발명의 목적은 CMOS 집적 회로 구현시에 발생하는 기생 트랜지스터를 이용함으로써 회로 구성이 간단하고 집적화시에 레이 아웃 면적을 줄일 수 있는 CMOS 집적회로내에서의 바이어스 집적회로를 제공하는데 있다.Accordingly, it is an object of the present invention to provide a bias integrated circuit in a CMOS integrated circuit which can simplify the circuit configuration and reduce the layout area at the time of integration by using parasitic transistors generated during CMOS integrated circuit implementation.
본 발명의 다른 목적은 공정 변수에 무관한 전원 전압에 비례하는 CMOS 집적회로내에서의 바이어스 집적회로를 제공하는데 있다.It is another object of the present invention to provide a bias integrated circuit in a CMOS integrated circuit that is proportional to the power supply voltage independent of process variables.
이와같은 목적을 달성하기 위하여 본 발명에 따른 바이어스 집적회로는 제 1 전압과 제 2 전압 사이에 직렬 연결된 제 1 저항 성분, 다이오우드 성분, 제 2 저항 성분과 상기 제 1 저항 성분과 다이오우드 성분의 공통점과 상기 제 2 전압 사이에 제 3 저항 성분으로 구성되고 CMOS 공정을 사용하여 집적화한 것을 특징으로 한다.In order to achieve the above object, the bias integrated circuit according to the present invention has a common resistance between the first resistor component, the diode component, the second resistor component and the first resistor component and the diode component connected in series between the first voltage and the second voltage. A third resistor component is formed between the second voltages and integrated using a CMOS process.
첨부된 도면을 참조로 하여 본 발명에 따른 바이어스 회로를 설명하면 다음과 같다.Referring to the accompanying drawings, a bias circuit according to the present invention will be described.
제 2 도에 있어서, 전원 전압(VDD)과 전지전압 사이에 직렬 연결된 저항(R1), 다이오우드(D), 저항(Re)와 상기 다이오우드(D)의 애노우드 전극과 접지 전압 사이에 연결된 저항(R2)로 구성되어 있다.In FIG. 2, a resistor R1, diode D, resistor Re and a resistor connected between the anode voltage of the diode D and the ground voltage are connected in series between the power supply voltage V DD and the battery voltage. It consists of (R2).
제 3a 도는 본 발명에 따른 바이어스 회로의 공정상에서 발생하는 기생 트랜지스터를 포함하는 회로구성을 나타내는 것이다.3A shows a circuit configuration including parasitic transistors generated in the process of the bias circuit according to the present invention.
제 3a 도에 있어서, 전원전압(VDD)과 접지사이에 직렬 연결된 저항(R1,R2)와, 전원전압(VDD)과 접지사이에 직렬 연결된 저항(Rc), NPN 트랜짓터, 저항(Re)와, 상기 저항(R1,R2)의 공통점과 상기 트랜지스터의 베이스가 고통 접속되어 구성되어 있다. NPN 트랜지스터는 공정상에서 발생되는 기생 트랜지스터이다.The 3a also in the power supply voltage connected in series resistance between (V DD) and ground (R1, R2) and a supply voltage (V DD) resistance (Rc) connected in series between the ground, NPN transit emitter, a resistor (Re in ), A common point between the resistors R1 and R2, and the base of the transistor are connected to each other. NPN transistors are parasitic transistors generated in the process.
제 3b 도는 본 발명에 따른 바이어스 회로의 수직적인 구조를 나타내는 것이다.3b shows a vertical structure of a bias circuit according to the present invention.
제 3b 도에 있어서, 점선내 구조는 기생 NPN 트랜지스터를 나타내는 것이다.In FIG. 3B, the dotted line structure represents a parasitic NPN transistor.
제 3c 도는 제 3a 도에 나타낸 바이어스 회로의 테브닌 등가 회로를 나타내는 것이다.FIG. 3C shows a Thevenin equivalent circuit of the bias circuit shown in FIG. 3A.
제 3c 도에 있어서, 전원 전압(VDD)과 접지 사이에 직렬 연결된 저항(Rc), NPN 트랜지스터, 저항(Re)와, 상기 NPN 트랜지스터의 벵스와 접지 사이에 직렬 연결된 등가저항(Rb), 등가전압(VBB)로 구성되어 있다.In FIG. 3C, the resistor Rc, the NPN transistor, and the resistor Re connected in series between the power supply voltage V DD and the ground, and the equivalent resistance Rb connected in series between the vanes and the ground of the NPN transistor are equivalent. It consists of the voltage V BB .
등가저항 (Rb)와 등가전압(VBB)는 다음의 식으로 나타내어 진다.The equivalent resistance Rb and the equivalent voltage V BB are expressed by the following equation.
본 발명에 얻고자 하는 바이어스 전압은 전원 전압(VDD)에 비례하는 일정한 전압을 얻고자 하므로 베이스-에미터간 전압(VBE)을 사용하게 된다. 상기 베이스-에미터간 전압(VBE)은 다이오우드를 이용하여 쉽게 얻을 수 있지만, 이 베이스-에미터간 전압(VBE)의 중심값인 기준전압(Vref)을 전원 전압(VDD)에 비례한 전압으로 하고자 할 경우는 쉽지않다. 본 발명의 회로는 이 기준전압(Vref)을 항상 전원 전압(VDD)에 비례하는 전압을 나타내면서 베이스-에미터간 전압(VBE)을 일정하게 유지시켜 준다.The bias voltage to be obtained in the present invention is to obtain a constant voltage proportional to the power supply voltage (V DD ) to use the base-emitter voltage (V BE ). The base-emitter voltage (V BE ) can be easily obtained by using diodes, but the reference voltage (Vref) that is the center of the base-emitter voltage (V BE ) is proportional to the power supply voltage (V DD ). If you want to do it is not easy. The circuit of the present invention keeps the voltage V BE constant between the base and emitters while the voltage Vref is always proportional to the power supply voltage V DD .
제 3d 도는 제 3c 도에 나타낸 회로의 베이스-에미터 루프를 등가적으로 나타낸 등가회로를 나타내는 것이다.FIG. 3d shows an equivalent circuit equivalently representing the base-emitter loop of the circuit shown in FIG. 3c.
제 3d 도에 있어서, 에미터 전류(iE)는 다음과 같이 나타내어 진다.In FIG. 3d, the emitter current i E is represented as follows.
즉, 에미터 전류(iE)는조건에서는 β에 무관하게 나타나고 단지 영향을 미치는 것은 등가전압(VBB)이다. 상기 등가전압(VBB)는 저항비에 비례한 전압이고, 에미터 전류(iE)는 등가전압(VBB)의 함수이므로 에미터 전류(iE)도 전원 전압(VDD)에 비례해서 증감하므로 베이스-에미터간 전압(VBE)의 중간값인 기준전압(Vref)도 전원 전압(VDD)에 비례한 전압을 얻을 수 있다.That is, the emitter current i E is Under conditions, it is independent of β and the only effect is the equivalent voltage (V BB ). Since the equivalent voltage V BB is a voltage proportional to the resistance ratio, and the emitter current i E is a function of the equivalent voltage V BB , the emitter current i E is also proportional to the power supply voltage V DD . Since the reference voltage Vref, which is an intermediate value of the base-emitter voltage V BE , can be obtained in proportion to the power supply voltage V DD .
따라서 본 발명에 따른 바이어스 집적회로는 회로 구성이 간단하여 레이아웃 면적을 줄일 수 있으며, 전원 전압에 비례하는 기준전압을 출력한다.Therefore, the bias integrated circuit according to the present invention can simplify the circuit configuration, reduce the layout area, and output a reference voltage proportional to the power supply voltage.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920002221A KR950000520B1 (en) | 1992-02-14 | 1992-02-14 | Bias ic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920002221A KR950000520B1 (en) | 1992-02-14 | 1992-02-14 | Bias ic |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930018714A KR930018714A (en) | 1993-09-22 |
| KR950000520B1 true KR950000520B1 (en) | 1995-01-24 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019920002221A KR950000520B1 (en) | 1992-02-14 | 1992-02-14 | Bias ic |
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| Country | Link |
|---|---|
| KR (1) | KR950000520B1 (en) |
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1992
- 1992-02-14 KR KR1019920002221A patent/KR950000520B1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR930018714A (en) | 1993-09-22 |
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