KR940025198A

KR940025198A - Error Detecting Device for Line Length Decoder

Info

Publication number: KR940025198A
Application number: KR1019930007088A
Authority: KR
Inventors: 이창표
Original assignee: 이헌조; 주식회사 금성사
Priority date: 1993-04-27
Filing date: 1993-04-27
Publication date: 1994-11-19

Abstract

본 발명은 부호 복호기의 에러 검출 장치에 관한 것으로, 종래에는 하드웨어 구현이 용이한 가변장 부호화 방법에 따라 효과적으로 데이타 압축을 수행할 수 있으나 실시간으로 복호를 수행하는 경우 입력되는 런 값이 하나라도 잘못되면 발생하는 계수들의 위치가 계속해서 틀려지게 됨으로 계수의 동기가 어긋남에 따라 데이타 처리 시간이 오래 걸리거나 처리 동작에 에러가 발생되는 문제점이 있었다.The present invention relates to an error detection apparatus of a code decoder. In the related art, data compression can be efficiently performed according to a variable length coding method that can be easily implemented in hardware. However, when decoding is performed in real time, at least one run value is incorrect. As the positions of the generated coefficients continue to be wrong, there is a problem in that data processing takes a long time or errors occur in the processing operation as the coefficients are out of synchronization.

이러한 점을 감안하여 본 발명에서는 런/레벨부호(Run/Level)를 입력받아 연산함으로써 절대 번지(Addr)와 레벨신호(Level)로 변환하고 EOB신호 검출시 메모리에 저장한 후 절대 번지를 기준 번지와 비교함에 따라 디지탈신호인 계수를 발생시키고 계수 발생에 따라 비트 에러를 검출하도록 구성한다.In view of this point, the present invention converts the absolute address (Addr) and the level signal (Level) by receiving and calculating the run / level code, and stores the result in the memory when the EOB signal is detected. And generate a coefficient that is a digital signal and detect a bit error in accordance with the coefficient generation.

따라서, 연속적인 비트 에러에 의해 에러 프로퍼게이션(Error Propagation)이 계속될 경우 이를 검출하여 시스템의 부호 동작을 정지시킴으로써 안정된 신호 처리를 수행할 수 있다.Therefore, when error propagation continues due to continuous bit errors, stable signal processing can be performed by stopping the sign operation of the system by detecting the error propagation.

Description

Error Detecting Device for Line Length Decoder

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명 가변장 부호 복호기의 에러 검출장치2 is an error detection apparatus for a variable length code decoder of the present invention.

Claims

A signal processor 11 for outputting an absolute address Addr and a level signal VI which is an actual count value according to a cumulative operation of the decoded run / level signal, and the signal processor by detecting an EOB signal ( A memory 12 for storing the absolute address Addr and the level signal V1 according to the write signal WR of 11) and outputting the stored absolute address Addr1 and the level signal V11 according to the read signal RD; Then, the memory 12 and the absolute address Addr1 of the memory 12 are compared with the reference address C _Add according to the coefficients, and compared with the comparison signal Vc1 according to the comparison signal Vc1 ( A coefficient generation control unit 13 for combining the read signal RD to the memory 12 by combining Vc2, an output RD of the coefficient generation control unit 13, and a level signal V11 of the memory 12. And a coefficient generator 14 for outputting the coefficient Vo, which is a digital signal, and the reference address C _Add and the absolute memory 12 of the coefficient generation controller 13, respectively. An error detection apparatus for a variable length code decoder, characterized in that an error is formed by the detection unit (15) by logically combining the address (Addr1).

The memory 12 stores the absolute address Addr and the level signal V1 according to the write signal WR of the signal processor 11 and the read signal RD of the coefficient generation controller 13. And a first-in first-out part 12-1 for outputting an absolute address Addr 'and a level signal V1' stored according to the first address, and an output Addr 'and a level signal V1' of the first-in first-out 12-1. Is a register (12-2) (12-3) for temporarily storing and outputting the data according to the output (RD) of the coefficient generation control section (13).

The count generation control unit 13 includes a run counter 13-1 for counting a reference address Cad for generating a count, and a reference address Cad of the run counter 13-1 is a memory. Comparators 13-2 and 13-3 for comparing each of the same or greater than the absolute address Addr1 of (12), and the outputs Vc1 and Vc2 of the comparators 13-2 and 13-3. And an OR gate for outputting the read signal RD to the memory 12 and the coefficient generator 14 according to the ").

The coefficient generator 14 includes an AND gate AN11 that combines the level signal V11 of the memory 12 and the read signal RD of the coefficient generation controller 13, and the AND gate ( An error detection device for a variable length code decoder, comprising: a register (14-1) for storing and outputting the output of AN11 according to a clock (CLK).

The NAND gate device according to claim 1, wherein the error detector 15 detects and outputs an output Addr 1 (C _Add ) of the memory 12 and the coefficient generation controller 13, and the NAND gate. And an AND gate (AN12) for outputting an error detection signal (Err) according to the presence or absence of an absolute address by logically combining the outputs of (NA1) and (NA2).

※ Note: The disclosure is based on the initial application.