JP3325277B2 - Audio coding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a speech coding apparatus and, more particularly, to a speech coding apparatus which focuses on coding of a silent part.

[0002]

2. Description of the Related Art Conventionally, when encoding an audio signal, a special process has been performed for processing of a silent portion in order to encode with high efficiency.

[0003] For example, a so-called adaptive system in which a silent section without sound is encoded at a low bit rate with a small number of encoding bits per unit time is one of them. This is, for example, as follows. That is, as shown in the timing chart of FIG. 5, it is assumed that the speech codes sequentially inputted from the nth frame to the n + 7th frame as the time t elapses are sequentially encoded from the low memory address to the high memory address. n
Between the +3 frame and the n + 5 frame is a silent section. For this reason, these sections are encoded at a low bit rate, so that the
The compression ratio is set to 1 / k.

On the other hand, there is also known a run-length encoding in which a silent section having no sound is not encoded at all.
This is as follows. That is, as shown in the time chart of FIG. 6, only the (n + 1) and (n + 3) sections that are equal to or greater than a certain threshold TH in the audio waveform W input as time t elapses, as shown in FIG. N and n + 2 sections that are equal to or less than the threshold value TH are not subjected to encoding at all. Then, as shown in FIG.
This is a method in which only n + 1 and n + 3 sections with speech are connected and encoded.

[0005] The conventional speech coding apparatus has improved the coding efficiency by any of the above methods.

[0006]

In the case of the first method for encoding a silent section at a lower bit rate than a speech section,
The memory amount per unit time differs between the voice section and the silent section. Therefore, if special reproduction such as skipping is performed during decoding, the amount of address skipping per unit time differs depending on whether encoded data is audio. Therefore, when calculating the addressing at the time of skipping, it is necessary to read out the memory contents once. As a result, there is a problem that the circuit scale increases and the operation time also increases.

On the other hand, in the case of the second method in which a silent section is not encoded at all, data of a silent section is completely missing. For this reason, when the decoded sound is reproduced, the reproduced sound has a silent section missing. For this reason, there is a problem that the faithful reproduction of the sound at the time of recording cannot be performed, resulting in an unnatural reproduction sound.

As described above, the conventional speech coding has a problem that the processing becomes complicated when the speech is decoded and the reproduced sound becomes unnatural.

[0009] The present invention has been made in view of the above,
An object of the present invention is to facilitate addressing at the time of sound reproduction and to enable natural sound reproduction.

[0010]

According to a first aspect of the present invention, there is provided a speech encoding apparatus for detecting a silence portion of an input speech signal and outputting a silence detection signal, and a clock for outputting the silence detection signal. A silence counter that counts a number and outputs a counter value, and when the silence portion is not detected and the counter value is not output, a sound portion of the input audio signal is used as an encoded audio signal, and the silence portion is output. Is detected,
A speech encoding unit that generates a silence code when the counter value exceeds a predetermined reference value, and a signal corresponding to the counter value from the silence counter when the silence portion is detected is provided, An address generation unit that increments an address at the time of inputting a part, and a memory that stores the encoded audio signal output from the audio encoding unit and is provided with the silence code, the address generation unit includes:
When the counter value does not exceed the reference value, the address is incremented.When the counter value exceeds the reference value, the increment of the address of the memory is stopped. An address is generated so as to store a silence portion from the time of exceeding to the next sound portion in one frame having the same length as one frame regardless of the period, and the address is outputted to the memory. It is characterized by having.

Further, the second speech coding apparatus of the present invention is configured as follows.

A silence detecting section for detecting a silence portion of the input audio signal and outputting a silence detection signal; a silence counter for counting the number of clocks in outputting the silence detection signal and outputting a counter value; When the counter value is not output because no part is detected, the sound part of the input audio signal is used as the encoded audio signal, and the silent part is detected, and the counter value exceeds a predetermined reference value. A speech encoding unit that generates a silence code when a signal is generated, and a signal corresponding to the counter value from the silence counter is provided when the silence portion is detected, and an address generation step that increments an address when the speech portion is input. And a memory for storing the encoded audio signal output from the audio encoding unit and to which the silence code is given. When the counter value does not exceed the reference value, the address is incremented. When the counter value exceeds the reference value, not only the increment of the address of the memory is stopped, but also the address is changed to the silence. Return to the address at the start of the output of the detection signal, and store the silent part from the output of the silent detection signal to the next sound part in one frame of the same length as one frame regardless of the period. And outputs the address to the memory.

[0013]

The silent part of the input audio signal is detected by the silent detection means. When it is determined that the silent part is longer than the predetermined length, the silent code from the encoding means is stored in the memory. However, from this time, the address generation means stops the address increment. Thereafter, when the voice portion of the input voice means is input, the address increment is resumed. Then, the audio part is stored in the memory as an encoded audio signal.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a speech coding apparatus according to one embodiment of the present invention. As shown in FIG. 1, the silence detecting section 1 detects a silence section from the audio signal S1. The number of detected frames is counted by the silence counter 2. The audio encoding unit 4 encodes the audio to be encoded in the audio signal S1. That is, the audio encoding unit 4
The audio part is encoded as it is, the silent part is compressed, and the data is output together with the count value from the silent counter 2. Data from the audio encoding unit 4 is recorded in the code storage memory 5. The memory address Am used for this recording is generated by the address generator 3 based on a count signal from the silence counter 2.

FIG. 2 is a block diagram showing an example of the silence detecting section 1 of FIG. As shown in FIG. 2, the detector 11 detects the input audio signal S1. As a detection method in this case, a method such as an absolute value detection or a square detection is used.
The signal detected by the detector 11 is applied to a low-pass filter 12.
, And is compared by the comparator 13 with the fixed threshold value θ1. Then, for a section of the signal smaller than the fixed threshold value θ1, the silence detection signal S2 is output.

FIG. 3 is a block diagram showing an example of the silence counter 2 of FIG. As shown in FIG. 3, the silence counter 2 performs a counting operation by the clock CLK1, and is synchronously reset by the silence detection signal S2. Counter value θn
Is output from the silence counter 2.

FIG. 4 is a block diagram showing an example of the address generator 3 of FIG. As shown in FIG.
Is the counter value θn from the silence counter 2 and the fixed threshold value θ
2 and outputs the result. The logic gate 36
The NAND logic of the comparison result and the clock CLK2 is calculated, and a strobe signal is supplied to the address register 32.
The increment unit 33 receives the output data of the address register 32, and outputs data obtained by adding +1 to the data as the memory address Am. The subtractor 34 receives the output data of the address register 32, and outputs a value obtained by subtracting the data D from the data as a memory address Am. The switch 35 is based on the output from the comparator 31.
Any one of the output of the increment unit 33 and the output of the subtractor 34 is switched and output, and is provided to the address register 32.

The output of the comparator 31 is supplied to the code storage memory 5.
Is also used as a write signal WR for

Next, the operation of the above-described configuration will be described with reference to the timing chart of FIG. By the way, FIG. 7A shows the input speech waveform W,
(B) is a silence detection signal by the silence detection unit 1, (c) is a counter value of the silence counter 2, and (d) is an address generator 3.
WR, which is the output of the comparator 31 at
(E) shows the count value of the address register 32 of the address generator 3, and (f) shows the strobe signal of the address register 32.

First, it is assumed that the audio signal S1 is inputted and the audio waveform W exceeds the fixed threshold value θ1. in this case,
The silence detector 1 does not detect silence. Therefore, the audio encoding unit 4 encodes the audio signal S1 and writes the encoded audio signal S1 in the code storage memory 5 as encoded data. At this time, the output data of the increment unit 33 is supplied to the address register 32 through the switch 35. Therefore, the address is sequentially incremented based on the clock CLK2, and the encoded data is sequentially written in the code storage memory 5. At this time, the count value of the silence counter 2 remains "0" and does not advance.

On the other hand, the audio signal S1 is input, and the audio waveform W is set to a fixed threshold value θ1 or less. In this case, the silence detector 1
Outputs a silence detection signal S2 as shown in FIG. 7 (b). Thereby, the silence counter 2 becomes as shown in FIG.
As shown in the figure, the counting of the clock CLK1 is started,
The counter value θn is output. When the counter value θn reaches the fixed threshold value θ2, it is determined that encoding compression should be performed. This determination is performed by the comparator 31. As a result, as shown in FIG. 7D, the comparator 31 sends the write signal WR and the switching signal CH, and the switching unit 35 switches. When the switch 35 is switched, as shown in FIG. 7E, an address (kD) obtained by subtracting the data D from the current address k by the subtractor 34 is set in the address register 32. On the other hand, as shown in FIG.
LK2 is masked. Therefore, the address register 3
2 will keep the address (kD). Incidentally, the subtraction data D here is set to data corresponding to the fixed threshold value θ2 set in the comparator 31. on the other hand,
From the address generator 3, the counter value θn is set to a fixed threshold value θ2
It is assumed that a write signal WR indicating that the signal has exceeded the limit is output. At this time, the voice coding unit 4 writes a silent mark into the code storage memory 5 instead of the coded data of the voice signal S1. As long as the silent section continues, the address register 32 holds the address (kD). Silence counter 2
Keeps counting the silent section. Next, the audio signal S1
Is greater than the fixed threshold θ1, the silence detector 1
Is lost. As a result, the silence counter 2 stops the counting operation with the count value n at that time, and is reset synchronously to return the counter value n to “0”. Prior to this, the speech encoding unit 4 records the count value n of the silence counter 2 in the code storage memory 5. As a result, as shown in FIG. 9, the code storage memory 5 records the coded data of the voice coding unit 4 until the state shown in FIG. At this point, it is determined that there is no sound. At this point, as shown in (b), a silent mark is recorded at the memory address whose address has been returned by the data D, and thereafter the address is not advanced and the next time the voice section starts Record n, which is the counter value θn of the silence counter 2.

Now, returning to the voice section, when the counter value θn returns to “0”, the counter value θn becomes a fixed threshold value θ.
It becomes smaller than 2. For this reason, the write signal WR disappears, and the switch 35 is also switched from the subtractor 34 to the incrementer 33.
Switch to the side. As a result, the address register 32
Again, the address (kD) is synchronized with the clock CLK2.
From (k-D + 1) to start the increment operation. Thereby, the audio signal S1 encoded by the audio encoding unit 4 is sequentially written into the code storage memory 5.

The audio coded data written in the code storage memory 5 as described above is, as shown in FIG.
In a silent section, a silent mark and the number of silent section frames are recorded in a silent data format, and in a voice section, encoded audio data is recorded in an audio data format.

In order to reproduce the encoded audio data recorded in the above format, the encoded audio data may be reproduced as it is while the address of the code storage memory 5 is advanced in the audio data format section. On the other hand, in the silence data format section, the fact that the frame is a silence frame is detected by the silence mark, and in that section, the address of the code storage memory 5 is stopped, and the silence data may be continuously reproduced. At the same time, the number of silent section frames is counted, and when the count value is full, the address of the code storage memory 5 may be advanced without stopping. If a silent section is to be skipped, it is sufficient to proceed without stopping the address of the code storage memory 5. As shown in FIG. 10, if the data size is the same between the silent data format and the audio data format, there is no need to switch the address control between the silent portion and the audio portion.

When the data size is the same in the silence data format and the audio data format, addressing becomes easy, and special reproduction such as high-speed search, fast forward, and rewind can be realized without having to read data contents. Can be.

According to the above configuration, the silent section is compressed into one frame regardless of the length of the continuous silent section, so that the longer the silent section, the higher the data compression rate. Now, it is assumed that the ratio between the voice section and the silent section is 1: u. A comparison will be made with a case where the silent part is compressed to 1 / k with respect to the audio part by using the compression method as shown in FIG. The compression rate α1 that can be realized by the method shown in FIG. 5 is as follows: α1 = (1 + u) / {1 + u (1 / k)} = (1 + u) · k / (k + u), and the compression rate α2 is α2 = (1 + u) / 2. If u> k, then α1 <α2, and in this embodiment, the longer the silent section, the longer the
The data compression ratio increases. In addition, there is an advantage that a silent section does not need to be expanded even when a silent section is skipped.

FIG. 8 shows another example of the configuration of the address generator 3. The difference between the configuration in FIG. 8 and the configuration in FIG. 4 is that the subtractor 34 and the switch 35 are omitted, and the configuration is simplified. When the silent section is determined, the silent counter 2 has already counted up to the fixed threshold value θ2. However, in this example, the address of the address register 32 is merely restored without being restored. As a result, silence data is recorded in the code storage memory 5 only for the frame corresponding to the fixed threshold value θ2, which is disadvantageous in terms of the compression ratio. However, there is an advantage that the circuit configuration is simple and the cost is low.

In the above embodiment, each component is shown as an individual circuit configuration. However, the same function can be realized by using a microcomputer or a digital signal processor controlled by software. Also, the counter and the like can be realized by an analog circuit such as an integrator instead of the digital count. Further, in the above-described embodiment, the configuration in which the output values of the two circuits of the subtractor 34 and the increment unit 33 are switched by the switch 35 in order to give the address value to the address register 32 has been exemplified. However, the increment unit 3
3 and the subtractor 34 may be configured by a common computing unit, and the computation value may be switched by a switching signal to the switching unit 35.

It should be noted that the speech encoding device 4 is a PCM
Various coding methods such as (pulse code modulation), ADM (adaptive delta modulation), ADPCM (adaptive differential pulse code modulation), and APC-AB (adaptive adaptive coding-adaptive bit allocation) are applicable. . The audio signal S1 input to the audio encoding unit 4 may be an analog signal or a digital signal.

The code storage memory 5 may be not only a semiconductor memory but also a magnetic disk or a magnetic tape, and any medium that can record data can be applied. If real-time recording is not required, a slightly slower memory is applicable.

Further, the silence counter 2 outputs the audio signal S1
Is reset when the value exceeds the fixed threshold θ1, but the silence counter 2 may be reset when the time exceeding the fixed threshold θ1 exceeds a certain time. The silence counter 2 is not limited to the up counter, but may be a down counter.

[0033]

As described above, according to the present invention, a silent section of an audio signal is compressed into one frame of the same length as one frame of a sound section, together with data of the number of silent section frames, regardless of its length. Therefore, it is possible to increase the compression ratio in the case where the silent section continues for a long time. Further, since the frame size in the sound section and the frame section in the silent section are the same, that is, in the memory, One frame for storing the signal and one frame for storing the silence code and this counter value have the same data size,
The silent part in the input audio signal is 1 regardless of its length.
Since addressing is performed in frames, there is no need to switch address control in two sections, addressing becomes easy, storage and reproduction can be performed at high speed, and the circuit configuration of the entire apparatus is simple and low-cost. Can be obtained as In addition, data can be easily handled during reproduction and the circuit configuration can be simplified. Further, since a silent section is not determined unless a silent section continues for a certain period of time by a silent counter, the quality of reproduced sound can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a speech encoding device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a silence detecting section in FIG. 1;

FIG. 3 is a block diagram showing an example of a silence counter of FIG. 1;

FIG. 4 is a block diagram showing an example of an address generator 3 of FIG. 1;

FIG. 5 is a timing chart showing an example of a conventional audio encoding method.

FIG. 6 is a timing chart showing another example of a conventional audio encoding method.

FIG. 7 is a timing chart for explaining the operation of the circuits of FIGS. 1 to 4;

FIG. 8 is a partial block diagram of a speech encoding device according to another embodiment of the present invention.

FIG. 9 is an explanatory diagram of a recording state of a silent section in a code storage memory.

FIG. 10 is an explanatory diagram of a recording format in a code storage memory.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silence detection part 2 Silence counter 3 Address generator 4 Voice encoding part 5 Code storage memory 11 Detector 12 Low-pass filter 13 Comparator 31 Comparator 32 Address register 33 Increment part 34 Subtractor 35 Switch 36 Logic gate

Claims (2)

(57) [Claims] 1. A silence detection unit that detects a silence portion of an input audio signal and outputs a silence detection signal, a silence counter that counts the number of clocks in outputting the silence detection signal and outputs a counter value, and a silence counter. When the counter value is not output because no part is detected, the sound part of the input audio signal is used as the encoded audio signal, and the silent part is detected, and the counter value exceeds a predetermined reference value. A speech encoding unit that generates a silence code when a signal corresponding to the counter value is given from the silence counter when the silence part is detected, and an address generation step that increments an address when the speech part is input. And a memory for storing the encoded audio signal output from the audio encoding unit and to which the silence code is given. When the value does not exceed the reference value, the address is incremented, and when the counter value exceeds the reference value, the increment of the address of the memory is stopped, and the counter value exceeds the reference value. It is configured to generate an address so as to store a silent portion from a time to a next sound portion in one frame having the same length as one frame length regardless of the period, and output the address to the memory. A speech coding apparatus characterized by the above-mentioned. 2. A silence detecting section for detecting a silence portion of an input audio signal and outputting a silence detection signal, a silence counter for counting the number of clocks in outputting the silence detection signal and outputting a counter value; When the counter value is not output because no part is detected, the sound part of the input audio signal is used as the encoded audio signal, and the silent part is detected, and the counter value exceeds a predetermined reference value. A speech encoding unit that generates a silence code when a signal corresponding to the counter value is given from the silence counter when the silence part is detected, and an address generation step that increments an address when the speech part is input. And a memory for storing the encoded audio signal output from the audio encoding unit and to which the silence code is given. When the value does not exceed the reference value, the address is incremented. When the counter value exceeds the reference value, not only the increment of the address of the memory is stopped but also the silence detection of the address is performed. Return to the address at the start of signal output, and store the silence part from the output of the silence detection signal to the next sound part in one frame of the same length as one frame regardless of the period. A speech encoding device configured to generate an address and output the address to the memory.