KR970013797A - Reed-Solomon Decoder - Google Patents

Reed-Solomon Decoder Download PDF

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Publication number
KR970013797A
KR970013797A KR1019950024819A KR19950024819A KR970013797A KR 970013797 A KR970013797 A KR 970013797A KR 1019950024819 A KR1019950024819 A KR 1019950024819A KR 19950024819 A KR19950024819 A KR 19950024819A KR 970013797 A KR970013797 A KR 970013797A
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South Korea
Prior art keywords
error
memory device
output
reed
input data
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KR1019950024819A
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Korean (ko)
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KR0149298B1 (en
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임민중
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김광호
삼성전자 주식회사
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Publication of KR970013797A publication Critical patent/KR970013797A/en
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Publication of KR0149298B1 publication Critical patent/KR0149298B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1515—Reed-Solomon codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing

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  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Algebra (AREA)
  • General Physics & Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

이 발명은 디지탈 통신 시스템(Digital Communication System)의 수신단에 적용되어, 오증계산(Syndrome computation)과 알람 발생(alarm generation)이 하나의 하드웨어(hardware)에 의해 공유되도록 한 리드-솔로몬 디코더에 관한 것으로서, 선택소자에 의해 입력데이타를 선택하여 오증계산 및 에러정정을 수행한후, 에러가 정정된 데이타를 선택하여 보정된 데이타의 오증을 계산하고 이의 알람발생 여부를 결정하고, 에러가 없을 경우에만 보정된 데이타를 출력하도록 구성하여, 하나의 오증계산부가 시스템이 의해 공유되도록 구성함으로써 하드웨어 크기를 줄일 수 있는 리드-솔로몬 디코더를 제공할 수 있다.The present invention relates to a Reed-Solomon decoder which is applied to a receiving end of a digital communication system so that syndrome calculation and alarm generation are shared by one hardware. After selecting the input data by the selection device to perform the error calculation and error correction, select the data where the error is corrected, calculate the error of the corrected data, determine whether or not the alarm occurs, and correct only if there is no error. It is possible to provide a Reed-Solomon decoder that can be configured to output data, so that one miscalculation unit can be shared by the system, thereby reducing hardware size.

Description

리드-솔로몬 디코더Reed-Solomon Decoder

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 이 발명의 실시예에 따른 리드-솔로몬 디코더의 구성 블럭도이다.1 is a block diagram of a Reed-Solomon decoder according to an embodiment of the present invention.

Claims (3)

두 영역의 기억공간으로 구분되어, 입력데이타의 쓰기 및 읽기가 두 영역에 번갈아 수행되는 메모리장치와; 첫번째 주기에는 상기 메모리 장치에서 읽어진 입력데이타의 오증을 계산한 후 출력하며, 두번째 주기에는 에러가 정정된 데이타의 오증을 계산하여 에러가 제대로 정정되지 않았으면 알람신호를 출력하고, 에러가 제대로 정정되었으며 에러가 정정된 데이타를 출력하는 오증계산 및 알람발생부와; 상기 오증계산 및 알람발생부의 첫번째 주기에 계산된 오증을 받아들여 에러의 위치 및 크기를 계산하는 에러계산부와; 상기 에러계산부의 에러의 위치 및 크기를 받아들이는 한편, 상기 메모리장치의 입력데이타를 받아들여 입력데이타에 존재하는 에러를 정정하는 에러보정부와; 상기 메모리장치의 출력과 상기 에러보정부의 출력을 두 입력으로 하여, 첫번째 주기에 상기 메모리장치의 출력을 선택하고, 두번째 주기에 상기 에러보정부의 출력을 선택하는 선택수단으로 이루어지는 것을 특징으로 하는 리드-솔로몬 디코더.A memory device divided into two storage areas, in which writing and reading of input data is alternately performed in the two areas; In the first period, the error of the input data read from the memory device is calculated and then outputted. In the second period, the error of the corrected data is calculated, and if the error is not corrected, an alarm signal is output and the error is correctly corrected. A miscalculation and alarm generation unit for outputting data corrected with errors; An error calculation unit which receives the error calculated in the first period of the error calculation and alarm generation unit and calculates the position and size of the error; An error correction unit that accepts the position and size of an error of the error calculator and accepts input data of the memory device and corrects an error present in the input data; And selecting means for selecting the output of the memory device in the first period and the output of the error correction in the second period, with the output of the memory device and the output of the error correcting unit being two inputs. Reed-Solomon Decoder. 제1항에 있어서, 상기한 오증계산 및 알람발생부와 에러계산부와 에러보정부의 동작 사이클은 상기 메모리장치의 쓰기 또는 읽기를 위한 사이클의 두배 이상인 것을 특징으로 하는 리드-솔로몬 디코더.The Reed-Solomon decoder of claim 1, wherein an operation cycle of the miscalculation and alarm generation unit, the error calculation unit, and the error correction unit is more than twice the cycle for writing or reading the memory device. 제1항에 있어서, 상기한 선택수단은 멀티플렉스이며, 상기 메모리장치의 입력데이타와 상기 에러보정부의 출력을 번갈아 선택하도록 동작하는 것을 특징으로 하는 리드-솔로몬 디코더.The Reed-Solomon decoder according to claim 1, wherein the selection means is multiplexed and operates to alternately select an input data of the memory device and an output of the error correction unit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950024819A 1995-08-11 1995-08-11 Reed-solomon decoder KR0149298B1 (en)

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KR970013797A true KR970013797A (en) 1997-03-29
KR0149298B1 KR0149298B1 (en) 1998-12-15

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Publication number Priority date Publication date Assignee Title
KR100510503B1 (en) * 2002-12-10 2005-08-26 삼성전자주식회사 New pipline Reed Solomon decoding method for providing extreme hardware efficiency
KR100617129B1 (en) * 2004-11-22 2006-08-31 엘지전자 주식회사 Digital Multimedia Broadcasting Receiver with Forward Error Correction

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