KR920013377A - Error correction decoding method and device - Google Patents

Abstract

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Description

Error device decoding method and device

Since this is an open matter, no full text was included.

3 is a block diagram of an RS code applied to an embodiment of the present invention, FIG. 4 is a flowchart according to the present invention, and FIG. 5 is a first decoding block diagram according to a horizontal pariter according to an embodiment of the present invention.

Claims (2)

Add a pariter with error correction capability of n (n is integer) symbol and 2n symbol error in the horizontal direction, and add a pariter with loss correction capability of m (m is integer) symbol in the vertical direction. In the RS protection, a step of performing a syndrome operation by constant input data in the horizontal direction, a step of error correction and memory if the error in the horizontal direction is n or less according to the syndrome operation, and a memory in the horizontal direction if correction is impossible Determining whether or not an error is less than 2n is possible, and adding a horizontal error position flag to the memory if it is possible to detect it; if not, adding a memory to the burst error flag and storing it; Outputting data in the vertical direction and performing vertical loss correction when the error flag in the vertical direction is less than or equal to m. Error correction decoding method consisting of the steps to output as it is and to correct in the later stage. A syndrome calculation circuit in which syndromes are calculated by input data, an incomplete n error correction decoding circuit for correcting n cases or less according to the output of the input data and the syndrome calculation circuit, the input data and the incomplete an error correction judging circuit for comparing the outputs of the n error correction decoding circuits to determine whether an error has been corrected, and an output of the syndrome operation circuitry outputs the output of the incomplete n error correction decoding circuit and the output of the error Error position detection circuit for detecting an error position when the error is less than 2n, a missing flag adding circuit for adding a missing flag to an error position in accordance with the error position detection of the error position detection circuit, and in the error position detection circuit. Burst error to add a missing flag to the entire amount of input data when the error is greater than 2n A first decoding section by a horizontal parrer comprising a leg addition circuit, a memory section for storing data corrected by the error correction circuit, output data of the missing flag adding circuit, and output data of the burst error flag adding circuit; And a serial / parallel converter for sequentially outputting signals sequentially input in the horizontal direction to the memory unit in a vertical direction, an error flag counter for calculating the number of error flags of the output of the serial / parallel converter, and an output of the error flag counter. A control circuit for generating a control signal according to an error flag, a loss correction circuit for receiving the control signal having the error flag number of m or less, and correcting and outputting the output data of the serial-to-parallel converter, and a control signal having the error flag number of m or more A delay circuit for outputting the output data of the serial-to-parallel converter as it is Error correction decoding device comprising a second decoding unit by a vertical pariter. ※ Note: The disclosure is based on the initial application.