KR940024666A - VRL's Variable Speed Data Recording and Reproduction Circuit - Google Patents

VRL's Variable Speed Data Recording and Reproduction Circuit Download PDF

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Publication number
KR940024666A
KR940024666A KR1019930006444A KR930006444A KR940024666A KR 940024666 A KR940024666 A KR 940024666A KR 1019930006444 A KR1019930006444 A KR 1019930006444A KR 930006444 A KR930006444 A KR 930006444A KR 940024666 A KR940024666 A KR 940024666A
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KR
South Korea
Prior art keywords
data
signal
output
memory
unit
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Application number
KR1019930006444A
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Korean (ko)
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KR970005642B1 (en
Inventor
최만출
신용후
서윤석
임순기
조중권
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이헌조
주식회사 금성사
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Priority to KR1019930006444A priority Critical patent/KR970005642B1/en
Publication of KR940024666A publication Critical patent/KR940024666A/en
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Publication of KR970005642B1 publication Critical patent/KR970005642B1/en

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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B5/02Recording, reproducing, or erasing methods; Read, write or erase circuits therefor

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  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

본 발명은 브이씨알의 가변 속도 데이타 기록재생 회로에 관한 것으로, 종래에는 디지탈방식 또는 아날로그 방식에 따라 데이타 처리속도가 고정되어 외부에서 수신된 다양한 전송 속도의 데이타를 기록 재생하지 못함으로 각종 사무기기의 데이타를 기록, 재생하지 못하는 불편함이 있었다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable speed data recording / reproducing circuit of a BC-R. In the related art, a data processing speed is fixed according to a digital method or an analog method, and thus data of various transmission rates received from the outside cannot be recorded and reproduced. There was an inconvenience in not being able to record and play data.

이러한 점을 감안하여 본 발명에서는 기록모드시 시 분할에 따라 영상데이타를 해당 메모리에 저장한 후 일정 크기의 데이타가 저장되면 인식명을 부가하여 테이프에 기록하고 재생모드시 재생데이타의 인식명을 분리, 판별함에 따라 해당 메모리에 데이타를 저장한 후 외부기기에서 연상 데이타를 재현하도록 구성한다.In view of the above, the present invention stores image data in a corresponding memory according to time division in the recording mode, and when data of a certain size is stored, adds a recognition name to record on a tape, and separates the recognition name of the playback data in playback mode. After determining that the data is stored in the memory, the external device is configured to reproduce the association data.

따라서, 본 발명은 다양한 전송속도의 데이타를 일정 속도로 처리하여 테이프에 기록함으로써 각종 사무기기의 데이타를 시 분할 저장 기록하고 필요시 재생할 수 있다.Therefore, according to the present invention, data of various office devices can be processed at a constant speed and recorded on a tape, so that data of various office devices can be time-divided and recorded and reproduced when necessary.

다양한 속도의 데이타를 기록 재생할 수 있다.Record and play back data at various speeds.

Description

브이씨알의 가변 속도 데이타 기록재생 회로VRL's Variable Speed Data Recording and Reproduction Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1도는 본 발명 브이씨알의 가변 속도 데이타 기록재생 회로의 블럭도, 제 2도는 본 발명에 따른 데이타 포멧의 예시도, 제 3도는 본 발명에 따른 기록, 재생시, 신호 흐름도.1 is a block diagram of a variable speed data recording and reproducing circuit of the present invention V2, FIG. 2 is an illustration of a data format according to the present invention, and FIG. 3 is a signal flow chart during recording and reproduction according to the present invention.

Claims (1)

디지탈 데이타 기록모드시 외부기기(8A)(8B)(8C)에서 입력된 디지탈 입력신호(VDi1)(VDi2)(VDi3)를 특정의 고화질 티브이 신호(HDi1)(HDi2)(HDi3)로 변화시켜 메모리(2A)(2B)(3C)에 저장시키고 재생모드시 상기 메모리(2A)(2B)(2C)에서 입력된 고화질 티부이신호(HDo1)(HDo2)(VDo3)를 디지탈 신호(VDo1)(VDo2)(VDo3)로 변환하는 인터페이스(1A)(1B)(1C)와, 기록 모드시 상기 인터페이스(1A)(1B)(1C)의 출력클럭(CLK1)(CLK2)(CLK3)에 따라 상기 고화질 티브이 신호(HDi1)(HDi2)(HDi3)를 저장하는 메모리(2A)(2B)(2C)의 출력을 스위치(SW4)를 통해 입력받아 인식명(ID)을 부가하여 메인 메모리(2D)에 출력하고 재생 모드시 상기 메인 메모리(2D)의 출력을 입력받아 인식명(ID)을 분리하여 스위치(SW3)를 통해 상기 메모리(2A)(2B)(2C)에 출력하는 인식명 부가/분리부(7)와, 기록 재생 모드시 상기 인터페이스(1A)(1B)(1C), 메모리(2A)(2B)(2C) 및 인식명 부가/분리부(7)의 동작을 동기시키고 상기 스위치(SW3)(SW4)를 절환시킴으로써 데이타의 입출력 및 저장 동작을 시 분할 제어하는 데이타 입출력 제어부(6)와, 기록시 상기 메인 메모리(2D)의 출력 또는 재생시 원래의 복원신호(V4)를 입력받아 디지탈 에러를 정정하는 에러정정부(3)와, 기록시 상기 에러정정부(3)의 출력(V1)을 특정 형태의 기록포멧으로 재배열하고 재생시 증폭 신호(V3)의 주파수와 위상을 동기시켜 복조시킴에 따라 원래 형태의 신호(V4)로 복원하여 상기 에러 정정부(3)에 출력하는 포멧 변환부(4)와, 기록시 상기 포멧 변환부(4)의 출력(V2)을 일정레벨 증폭하여 헤드(HD1)에 출력하고 재생시 상기 헤드(HD1)의 검출신호를 소정레벨 증폭하는 신호증폭시(5)와, 기록 재생시 상기 에러 정정부(3) 및 포멧 변환부(4)의 동작을 동기시킴과 아울러 헤드(HD1)를 스위칭시키고 시스템 전체의 동작을 제어하는 시스템 제어부(9)로 구성함을 특징으로 하는 브이씨알의 가변 속도 데이타 기록 재생 회로.In the digital data recording mode, the digital input signals VDi 1 (VDi 2 ) (VDi 3 ) input from the external devices 8A, 8B, and 8C are converted to specific high-definition TV signals HDi 1 (HDi 2 ) (HDi). 3 ) is stored in the memory (2A) (2B) (3C) and the high-definition Tibuy signal (HDo 1 ) (HDo 2 ) (VDo 3 ) input from the memory (2A) (2B) (2C) in the playback mode Interface 1A (1B) 1C for converting the signal into a digital signal (VDo 1 ) (VDo 2 ) (VDo 3 ), and the output clock (CLK 1 ) of the interface (1A) (1B) (1C) in the recording mode. Input the output of the memory (2A) (2B) (2C) for storing the high-definition TV signal (HDi 1 ) (HDi 2 ) (HDi 3 ) according to (CLK 2 ) (CLK 3 ) through the switch (SW4) Receives the recognition name (ID) and outputs it to the main memory (2D), and receives the output of the main memory (2D) in the playback mode, separates the recognition name (ID), and switches the memory (2A) through the switch (SW3). (2B) and the recognition name addition / separation unit 7 outputted to 2C, and in the recording / playback mode, Input / output of data by synchronizing the operations of the interfaces 1A, 1B, 1C, memory 2A, 2B, 2C, and recognition name adding / detaching unit 7 and switching the switches SW3 and SW4. and error correction to the data input-output control unit 6 for dividing the control during the storage operation, the recording receives the original reconstructed signal (V 4) in the output or reproduction of said main memory (2D) corrects the digital error (3 ) And the output V 1 of the error correcting unit 3 during recording is rearranged to a specific type of recording format, and the frequency and phase of the amplified signal V 3 are synchronized and demodulated during reproduction. signal (V 4) to restore it to the error correction unit 3 format converting section 4, a record in the output (V 2) to a predetermined level amplification head of the format converting unit 4 for outputting the (HD 1 Signal amplification unit 5 for amplifying a predetermined level of the detection signal of the head HD 1 during reproduction, and the error correction unit (3) and variable speed data of V-Cal, characterized by comprising a system control unit 9 for synchronizing the operation of the format conversion unit 4, switching the head HD 1 , and controlling the operation of the entire system. Record reproduction circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930006444A 1993-04-16 1993-04-16 Variable speed data recording and reproducing circuit of vcr KR970005642B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930006444A KR970005642B1 (en) 1993-04-16 1993-04-16 Variable speed data recording and reproducing circuit of vcr

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930006444A KR970005642B1 (en) 1993-04-16 1993-04-16 Variable speed data recording and reproducing circuit of vcr

Publications (2)

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KR940024666A true KR940024666A (en) 1994-11-18
KR970005642B1 KR970005642B1 (en) 1997-04-18

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100741189B1 (en) * 1999-10-22 2007-07-19 소니 가부시끼 가이샤 Digital broadcast receiver, recording apparatus and data recording method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100741189B1 (en) * 1999-10-22 2007-07-19 소니 가부시끼 가이샤 Digital broadcast receiver, recording apparatus and data recording method

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KR970005642B1 (en) 1997-04-18

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