KR910001204B1 - Recording and revival circuit of field picture - Google Patents

Abstract

The circuit is for recording or reproducing one field of the television or VTR signal. The multiplxed image signal (CV) is stored in a RAM (4) after converting to digital data. The data is converted to 18 bit by adding 6 bit data three times in a controller (3) of D/A (2) and A/D (1) converters. The data transmitting to a tape or the RAM is converted by a 16 bit (5) or 18 bit (9) counter so that one field data is recorded or reproduced with high speed. The circuit is applicable to a digital audio tape recorder, still picture video camera, or optical filing system.

Description

Field image recording and reproducing circuit

Circuit diagram of the present invention.

* Explanation of symbols for main parts of the drawings

1: Analog to Digital Converter 2: Digital to Analog Converter

3: controller 4: ram

5: hexadecimal counter 6: hexadecimal counter

7: parallel-to-parallel converter 8: parallel-to-parallel converter

9: 18 hex counter 10: clock generator

11A, 11B, 11C: Analog switch 12A, 12B, 12C, 12D: 3 state buffer

13: inverter

It is an object of the present invention to provide a field image recording and reproducing circuit capable of receiving and recording one field of a television signal or a video signal on a tape.

Conventionally, one field of a video signal is converted into a digital signal through an analog digital converter, stored in a RAM, and the data stored in the RAM is recorded on an audio tape. After the data was stored in the RAM, the data stored in the RAM was reduced to an analog video signal through a digital analog converter, so that one field of image was reproduced during playback of one song.

However, the sampling frequency of the digital audio tape recorder is 1.53MHZ, whereas the sampling frequency of the signal output through the analog and digital analog converters is 3fsc (= 93ns), which is three times the color signal frequency (fsc = 3.58MHZ). Recording from stored RAM to tape and data transfer from tape to RAM are difficult, especially the problem of writing and reading high-speed sampling data to RAM to reproduce one field of image during a single song playback on a digital audio tape recorder. It was the biggest difficulty.

In view of the above, the present invention converts a sampling frequency of a video signal and a sampling frequency between a digital audio tape recorder so that data between a RAM and a tape can be transferred at a high speed and can be easily written to and read from the tape. The present invention will be described in detail with reference to the accompanying drawings as follows.

The 6-bit digital signal converted from the analog digital converter 1 to the 3 fsc sampling frequency is converted into 18 bits through the controller 3 and then stored in the RAM 4 through the analog switch 11B, and at this time, the address of the RAM 4 Is configured to be applied through the analog switch 11C at the fsc frequency at the controller 3.

The data stored in the RAM 4 divides the clock frequency of the clock generator 10 by the hexadecimal counter 6, divides it by the hexadecimal counter 5, and then, by the frequency applied through the analog switch 11C. The data addressed and read from the RAM 4 is configured to be converted into serial data in the parallel-to-serial converter 7 via the analog switch 11B and then written to the tape.

On the other hand, the data recorded on the tape is read at the time of reproduction, converted into parallel data by the serial-to-parallel converter 8, and then stored in the RAM 4 by the addressing of the hexadecimal counter 5 through the analog switch 11A. Is stored by the controller 3, is applied to the controller 3 through the analog switch 11A, converted into 6-bit data, and then output through the digital analog converter 2;

, 라이트

신호를 출력시키게 된다.At this time, the sampling frequency of the analog digital converter 1 and the digital analog converter 2 is 3fsc, and the controller 3 applies the address signal of fsc to the RAM 4 and switches to the analog switches 11A, 11B, and 11C. The signal CT is applied while the enable signal EM and the RAM 4 are read in the three-state buffers 12C and 12D.

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Will output a signal.

In addition, the clock frequency of the clock generator 10 is applied to the parallel-to-parallel converter 7 and the serial-to-parallel converter 8 through the three-state buffers 12A and 12B, and to the hexadecimal counter 9 and 18 The output of the binary counter 9 synchronizes the parallel-to-parallel converter 7 with the serial-to-parallel converter 8.

The selection signal P applied by the user is applied to the three-state buffer 12A through the three-state buffer 12C and to the three-state buffer 12B through the inverter 13 at the same time.

The present invention configured as described above converts the composite video signal CV into digital data, stores the data in the RAM 4, records the data stored in the RAM 4 on the tape, and reads the data recorded on the tape during playback. After storing the data in 4) and converting the data stored in the RAM 4 into an analog signal, the screen of one field is reproduced.

First, the recording will be described.

The composite video signal CV is applied to the analog digital converter 1, sampled at a frequency of 3 fsc (= 93 ns), and applied to the controller 3 as 6-bit digital data. At this time, the large controller 3 has a frequency of 3 fsc. It takes 6 feet of data three times and outputs 18 bits of data at the frequency of fsc.

The controller 3 controls the analog switches 11A, 11B, and 11C to be connected to the contacts a.

Therefore, the 18-bit digital data output from the controller 3 is stored in the RAM 4 through the analog switch 11B. At this time, the address of the RAM 4 is applied through the analog switch 11C in the controller 3. do.

The controller 3 judges whether one field of data is stored in the RAM 4, and when the storage is completed, all the analog switches 11A, 11B, 11C are controlled to switch to the contact b.

At this time, when the analog switch 11C is switched to the contact point b, the output of the hexadecimal counter 5 is applied to the RAM 4 as an address signal, and the clock signal of the clock generator 10 is applied to the hexadecimal counter 5. The output of the hexadecimal counter 6 to which is applied is applied through the three-state buffer 12D driven by the enable signal EN of the controller 3.

Therefore, after one field of data is stored in the RAM 4 by the address signal of the controller 3, the contacts b of the analog switches 11A, 11B, and 11C are selected and the hexadecimal The output of the counter 5 is applied as an address signal and the data read by the address signal of the hexadecimal counter 5 is taped through the parallel-to-serial converter 7 synchronized with the output of the hexadecimal counter 9. Will be written to

In this case, the clock frequency of the clock generator 10 is applied to the parallel-serial converter 7 through the three-step buffer 12B. In this case, the clock frequency of the clock generator 10 is 1.53MHZ because the sampling frequency of the digital audio tape recorder is 1.53MHZ. It outputs a frequency of 1.53MH2 × 2.

The clock frequency of the clock generator 10 is selected by the selection signal P applied through the inverter 13 and the three-state buffer 12C.

On the other hand, look at the playback time.

When reproducing the signal, the controller 3 connects the analog switches 11A, 11B, and 11C to the contacts b, and the data read from the tape is synchronized by the output of the 18-degree counter 9, which is synchronized. After (8) is stored in the RAM (4) by 18 bits through the analog switch (11A).

At this time, the address is applied by the address hexadecimal counter 5 of the data stored in the RAM 4.

The clock frequency of the clock generator 10 is applied to the serial-to-parallel converter 8 through the three-state buffer 12A. At this time, the three-state buffer 12A is applied to the selection signal P applied through the three-state buffer 12C. To be selected.

In other words, when the RAM 4 writes data to the tape, the selection signal P is "low" to turn on the three-state buffer 12B, and when the signal read from the tape is stored in the RAM 4, the selection is made. The signal P is applied to " high " to turn on the 3 state buffer 12A.

When the data of one field read from the tape is stored in the RAM 4, the controller 3 detects this and switches the analog switches 11A, 11B, and 11C into the contacts A. Data stored in 4) is addressed by the fsc frequency of the controller 3 so that 18 bits of data are applied to the controller 3.

At this time, the controller 3 applies the 18-bit data to the digital analog converter 2 as 6-bit data at the frequency 3fsc, so that the video signal for one field first recorded on the output side of the digital analog converter 2 is output. Will be.

As described above, in the present invention, the digital and analog converter controller collects 6 bits three times, converts them into 18 bits, and processes data, and converts data transmitted to tape and RAM as hexadecimal counters and hexadecimal counters to facilitate high-speed transmission. This can be widely applied to digital audio tape recorders capable of recording and reproducing data for one field, video cameras for still screen generation, and optical disc filing systems for storing screen information.

Claims (1)

The 6-bit data converted by the analog digital converter 1 is converted into 18-bit, stored in the RAM 4, the 18-bit data read from the RAM 4 is applied to the digital analog converter 2 as 6-bit data, and the circuit operation is performed. The controller 3 to control and the control of the large controller 3 are switched to select the writing and reading of the data of the RAM 4, and the address and clock generator of the address controller 3 of the RAM 4. Analog switches 11A, 11B, 11C, which select an address divided by the hexadecimal counter 6 and the hexadecimal counter 5 by the clock frequency of 10, and the data read from the RAM 4 are serially connected. A parallel-to-parallel converter 7 and a serial-to-parallel converter 8 for converting data into a tape and writing serial data read from the tape into parallel data and storing the same in the RAM 4; Synchronizing the parallel converter 8 with the clock generator 10 An 18-degree counter 9 that adjusts the clock frequency by 18 and the clock frequency of the clock generator 10 is selectively controlled by the parallel-to-serial converter 7 and the serial-to-parallel converter 8 under the control of the selection signal P. FIG. A field image recording and reproducing circuit composed of three state buffers 12A, 12B, 12C, and an inverter 13 to be applied to the.

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