KR940020537A - Semiconductor package - Google Patents

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Publication number
KR940020537A
KR940020537A KR1019930001665A KR930001665A KR940020537A KR 940020537 A KR940020537 A KR 940020537A KR 1019930001665 A KR1019930001665 A KR 1019930001665A KR 930001665 A KR930001665 A KR 930001665A KR 940020537 A KR940020537 A KR 940020537A
Authority
KR
South Korea
Prior art keywords
heat sink
semiconductor package
semiconductor
semiconductor chip
lead
Prior art date
Application number
KR1019930001665A
Other languages
Korean (ko)
Other versions
KR100222294B1 (en
Inventor
오세혁
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019930001665A priority Critical patent/KR100222294B1/en
Publication of KR940020537A publication Critical patent/KR940020537A/en
Application granted granted Critical
Publication of KR100222294B1 publication Critical patent/KR100222294B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

효과적인 열방출을 위한 히트싱크를 구비하는 반도체 패키지에서, 상부 평탄면의 중앙부분에 반도체 칩이 실장되며, 하부표면의 일측이 패키지 몸체의 외부로 노출되는 히트싱크를 구비하였다. 이러한 히트 싱크의 외곽 둘레 표면에는 리이드들이 절연 접착되며, 상기 리이드들 및 히트 싱크와 접착 테이프와의 접착력 향상을 위한 접착성 도금막이 개제되어 있다. 상기 히트 싱크의 리이드와 반도체 칩사이에는 몰딩부재의 유입압력의 균형을 위한 관통공이 형성되어 있으며, 상기 관통공과 반도체 칩사이의 히트 싱크 표면에 시트 형상의 댐바들을 구비하고, 상기 댐바들의 상부에는 와이어 처짐시의 단락 방지를 위한 절연층이 구비되어 있다.In a semiconductor package having a heat sink for effective heat dissipation, a semiconductor chip is mounted on a central portion of an upper flat surface, and one side of the lower surface is provided with a heat sink exposed to the outside of the package body. Leads are insulated and adhered to the outer circumferential surface of the heat sink, and an adhesive plating film is provided to improve adhesion between the leads and the heat sink and the adhesive tape. Through holes for balancing the inflow pressure of the molding member are formed between the lead of the heat sink and the semiconductor chip, and sheet-shaped dam bars are provided on the surface of the heat sink between the through holes and the semiconductor chip. The insulation layer for preventing a short circuit at the time of wire sag is provided.

따라서 반도체 패키지의 패키지 몸체 형성을 위한 몰딩공정시 히트 싱크의 관통공이 몰딩부재의 유입 통로가 되므로 몰딩부재의 유입 압력의 불균형이 일어나지 않으므로 패키지 몸체에 크랙 및 불완전 몰딩등의 불량 발생이 방지되어 반도체 패키지의 신뢰성을 향상시킬 수 있다. 또한 접착 테이프와 리이드 및 히트싱크와의 결합력이 접착성 도금막에 의해 향상되어 리이드 떨어짐이 발생하지 않으므로 반도체 패키지의 신뢰성을 향상시킬 수 있다. 또한 열방출 효과가 우수하며, 한가지 종류의 히트 싱크상에 여러 가지 크기의 반도체 칩을 실장하여도 와이어 처짐에 의한 불량발생을 방지할 수 있어 반도체 패키지의 개발 및 생산에 필요한 시간 및 경비를 절감할 수 있다.Therefore, since the through hole of the heat sink becomes an inflow passage of the molding member during the molding process for forming the package body of the semiconductor package, the inflow pressure of the molding member does not occur so that defects such as cracks and incomplete molding are prevented in the package body. Can improve the reliability. In addition, since the bonding force between the adhesive tape, the lead, and the heat sink is improved by the adhesive plating film, no lead drop occurs, thereby improving reliability of the semiconductor package. In addition, the heat dissipation effect is excellent, and even if various sizes of semiconductor chips are mounted on one type of heat sink, defects caused by sagging wires can be prevented, thereby reducing the time and cost required for the development and production of semiconductor packages. Can be.

Description

반도체 패키지Semiconductor package

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 이 발명에 따른 반도체 패키지 히트 싱크의 실시예의 사시도,3 is a perspective view of an embodiment of a semiconductor package heat sink according to the present invention,

제4도는 제3도의 히트 싱크와 조합된 반도체 리이드 프레임의 평면도,4 is a plan view of a semiconductor lead frame in combination with the heat sink of FIG.

제5도는 이 발명에 따른 반도체 패키지의 몰딩공정을 설명하기 위한 도면이다.5 is a view for explaining a molding process of a semiconductor package according to the present invention.

Claims (8)

반도체 패키지에 있어서, 반도체 칩이 상부 표면에 실장되며 하부 일측이 패키지 몸체의 외부로 노출되어 열이 방출되도록 하는 히트 싱크와, 일정간격으로 형성되어 상기 반도체 칩의 본딩패드와 와이어로 연결되며 상기 히트 싱크의 둘레 표면에 부착되는 다수의 리이드들과, 상기 반도체 칩과 리이드들 사이의 히트 싱크를 관통하여 몰딩 부재의 유입통로가 되도록 형성되어 있는 관통공들과, 상기 반도체 칩과 리이드들 사이의 히트 싱크 상부에 돌출되도록 형성되어 있는 댐바들과, 상기 반도체 칩과 와이어 및 히트 싱크의 소정부분을 감싸도록 형성되어 있는 패키지 몸체를 구비하는 반도체 패키지.In the semiconductor package, a heat sink is mounted on the upper surface and the lower side is exposed to the outside of the package body to release heat, and formed at regular intervals to be connected to the bonding pad of the semiconductor chip by a wire. A plurality of leads attached to the circumferential surface of the sink, through holes formed through the heat sink between the semiconductor chip and the leads to be an inflow passage of the molding member, and the heat between the semiconductor chip and the leads And a dam body formed to protrude above the sink, and a package body formed to surround a predetermined portion of the semiconductor chip, the wire, and the heat sink. 제1항에 있어서, 상기 히트싱크가 Cu, Al, 그 합금 및 세라믹으로 구성되는 군에서 임의로 선택되는 하나의 물질로 형성되는 반도체 패키지.The semiconductor package of claim 1, wherein the heat sink is formed of one material arbitrarily selected from the group consisting of Cu, Al, alloys thereof, and ceramics. 제1항에 있어서, 상기 히트 싱크의 둘레 표면에 부착되는 리이들이 접착 테이프, 접착 코팅액 및 실링 글라스로 이루어지는 군에서 임의로 선택되는 하나의 수단에 의해 접착되어 있는 반도체 패키지.The semiconductor package according to claim 1, wherein the leases attached to the circumferential surface of the heat sink are bonded by one means arbitrarily selected from the group consisting of an adhesive tape, an adhesive coating liquid and a sealing glass. 제3항에 있어서, 상기 접착 수단과 리이드 및 히트싱크와의 접착력을 향상시키기 위한 접착성 도금막이 상기 리이드 하부 및 상기 히트싱크 둘레의 표면상에 형성되어 있는 반도체 패키지.4. The semiconductor package according to claim 3, wherein an adhesive plating film for improving the adhesion between the bonding means and the lead and the heat sink is formed on the lower surface of the lead and around the heat sink. 제1항에 있어서, 상기 댐바들이 서로 소정의 간격을 갖도록 설치되어 몰딩부재의 유입이 자유로운 반도체 패키지.The semiconductor package of claim 1, wherein the dam bars are installed to have a predetermined distance from each other to free flow of a molding member. 제1항에 있어서, 상기 댐바들의 상부에 절연층이 구비되어 있어 상기 와이어와 히트싱크와의 단락을 방지하는 반도체 패키지.The semiconductor package of claim 1, wherein an insulation layer is provided on the dam bars to prevent a short circuit between the wire and the heat sink. 제1항에 있어서, 상기 히트싱크의 상부 및 하부로 이루어지는 군에서 선택되는 적어도 한곳에 몰딩부재와의 결합력을 향상시키도록 홈 또는 구멍이 구비되어 있는 반도체 패키지.The semiconductor package of claim 1, wherein a groove or a hole is provided in at least one selected from the group consisting of upper and lower portions of the heat sink to improve a bonding force with the molding member. 제1항에 있어서, 상기 히트싱크와 리이드 프레임의 접합성 향상을 위하여 상기 히트 싱크의 모서리 부위에 요철을 구비하며 상기 리이드 프레임의 상기 요철과 대응하는 부분에 삽입홈을 구비하는 반도체 패키지.The semiconductor package of claim 1, wherein the semiconductor package includes an uneven portion at an edge portion of the heat sink and an insertion groove at a portion corresponding to the uneven portion of the lead frame to improve bonding between the heat sink and the lead frame. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930001665A 1993-02-08 1993-02-08 Semiconductor package KR100222294B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930001665A KR100222294B1 (en) 1993-02-08 1993-02-08 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930001665A KR100222294B1 (en) 1993-02-08 1993-02-08 Semiconductor package

Publications (2)

Publication Number Publication Date
KR940020537A true KR940020537A (en) 1994-09-16
KR100222294B1 KR100222294B1 (en) 1999-10-01

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930001665A KR100222294B1 (en) 1993-02-08 1993-02-08 Semiconductor package

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KR (1) KR100222294B1 (en)

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Publication number Publication date
KR100222294B1 (en) 1999-10-01

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