KR940020533A - Metal wiring formation method of semiconductor device - Google Patents

Metal wiring formation method of semiconductor device Download PDF

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Publication number
KR940020533A
KR940020533A KR1019930002418A KR930002418A KR940020533A KR 940020533 A KR940020533 A KR 940020533A KR 1019930002418 A KR1019930002418 A KR 1019930002418A KR 930002418 A KR930002418 A KR 930002418A KR 940020533 A KR940020533 A KR 940020533A
Authority
KR
South Korea
Prior art keywords
metal
semiconductor device
metal wiring
formation method
wiring formation
Prior art date
Application number
KR1019930002418A
Other languages
Korean (ko)
Inventor
이성권
김진태
김상익
백동원
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019930002418A priority Critical patent/KR940020533A/en
Publication of KR940020533A publication Critical patent/KR940020533A/en

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Abstract

본 발명은 금속 브리지(bridge)를 막기 위한 반도체 소자의 금속 배선 방법에 있어서, 금속을 증착하는 제1 단계, 및 상기 넓은 폭을 갖는 금속선(1)의 내부를 식각하여 금속폭을 줄이는 제2 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 금속 배선 방법에 관한 것으로, 측면 힐록에 의한 금속 선간의 브리지 문제를 해결함으로써 수율 개선(yield up) 및 제품 신뢰성 향상의 효과가 있다.The present invention provides a method for metal wiring of a semiconductor device for preventing a metal bridge, comprising: a first step of depositing a metal, and a second step of reducing the metal width by etching an inside of the wide metal line 1 It relates to a metal wiring method of a semiconductor device comprising a, it has the effect of improving the yield (yield up) and product reliability by solving the bridge problem between the metal line by the side hilllock.

Description

반도체 소자의 금속 배선 형성 방법Metal wiring formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래의 금속 배선 형성 평면도.1 is a plan view of forming a conventional metal wiring.

제2도는 본 발명에 의한 금속 배선 형성 평면도.2 is a plan view of forming a metal wiring according to the present invention.

Claims (1)

금속 브리지(bridge)를 막기 위한 반도체 소자의 금속 배선 형성 방법에 있어서, 금속을 증착하는 제1 단계 및 상기 넓은 폭을 갖는 금속선(1)의 내부를 식각하여 금속폭을 줄이는 제2 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 금속 배선 형성방법.A method of forming metal wirings in a semiconductor device to prevent metal bridges, the method comprising: a first step of depositing metal and a second step of reducing the metal width by etching the inside of the wide metal wire 1; The metal wiring formation method of the semiconductor element characterized by the above-mentioned. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930002418A 1993-02-22 1993-02-22 Metal wiring formation method of semiconductor device KR940020533A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930002418A KR940020533A (en) 1993-02-22 1993-02-22 Metal wiring formation method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930002418A KR940020533A (en) 1993-02-22 1993-02-22 Metal wiring formation method of semiconductor device

Publications (1)

Publication Number Publication Date
KR940020533A true KR940020533A (en) 1994-09-16

Family

ID=66866335

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930002418A KR940020533A (en) 1993-02-22 1993-02-22 Metal wiring formation method of semiconductor device

Country Status (1)

Country Link
KR (1) KR940020533A (en)

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