KR940008067A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
KR940008067A
KR940008067A KR1019920017606A KR920017606A KR940008067A KR 940008067 A KR940008067 A KR 940008067A KR 1019920017606 A KR1019920017606 A KR 1019920017606A KR 920017606 A KR920017606 A KR 920017606A KR 940008067 A KR940008067 A KR 940008067A
Authority
KR
South Korea
Prior art keywords
wiring
insulating layer
contact
semiconductor device
exposed
Prior art date
Application number
KR1019920017606A
Other languages
Korean (ko)
Other versions
KR100207443B1 (en
Inventor
이원식
김병선
김형근
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019920017606A priority Critical patent/KR100207443B1/en
Publication of KR940008067A publication Critical patent/KR940008067A/en
Application granted granted Critical
Publication of KR100207443B1 publication Critical patent/KR100207443B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 다층 배선이 형성되는 반도체 장치를 있어서 배선층간의 접촉 면적을 넓혀서 접촉 저항을 감소시킨 반도체 장치 및 그 제조방법에 관한 것으로서, 표면상에 제1배선이 패턴되어 형성된 제1절연층과, 상기 제1절연층상에 상기 제1배선의 한정된 지역내에서 상부표면과 측면이 노출되도록 제거되어 형성된 제2절연층과, 상기 노출된 제1배선의 상부표면과 측면과 접촉하면서 상기 제2절연층상을 지나가는 제2배선을 포함하여 이루어진 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multi-layer wiring formed therein, wherein the contact area between wiring layers is reduced to reduce contact resistance, and a method of manufacturing the same. A second insulating layer formed on the first insulating layer so that the upper surface and side surfaces thereof are exposed in a limited area of the first wiring, and the second insulating layer image being in contact with the upper surface and side surfaces of the exposed first wiring line. It is characterized by including a second wiring passing.

본 발명에 의하면, 배선층간의 접촉을 위한 공정 시 정렬곤란에 구애받음 없이 배선층간의 접촉 면적이 증가되어 접촉 저항이 감소되고 접촉의 신뢰도가 향상된다.According to the present invention, the contact area between the wiring layers is increased regardless of the misalignment during the process for the contact between the wiring layers to reduce the contact resistance and improve the reliability of the contact.

Description

반도체 장치 및 그 제조방법Semiconductor device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도의 (가)-(다)는 본 발명의 일 실시예에 의한 배선층간의 접촉부를 나타낸 평면도 및 단면도.(A)-(c) of FIG. 2 is a plan view and a sectional view showing a contact portion between wiring layers according to an embodiment of the present invention.

Claims (4)

표면상에 제1배선이 패턴되어 형성된 반도체기판상의 제1절연층과, 상기 제1절연층상에 상기 제1배선의 한정된 지역내에서 상부표면과 측면이 노출되도록 제거되어 형성된 제2절연층과, 상기 노출된 제1배선의 상부표면과 측면과 접촉하면서 상기 제2절연층상을 지나가는 제2배선을 포함하여 이루어진 것을 특징으로 하는 반도체 장치.A first insulating layer on a semiconductor substrate formed by patterning a first wiring on a surface thereof, a second insulating layer formed on the first insulating layer by removing an upper surface and side surfaces thereof in a limited region of the first wiring; And a second wiring passing over the second insulating layer while in contact with the exposed upper surface and side surfaces of the first wiring. 제1항에 있어서, 상기 제1, 2배선은 폴리 실리콘 또는 금속 중 어느 하나로 된 것임을 특징으로 하는 반도체 장치.The semiconductor device according to claim 1, wherein the first and second wirings are made of either polysilicon or metal. 제1항에 있어서, 상기 상부표면과 측면이 노출된 제1배선이 상기 노출 부위내에서 그 일부가 절단되어 있는 것을 특징으로 하는 반도체 장치.The semiconductor device according to claim 1, wherein a part of the first wiring having the upper surface and the side surface exposed thereof is cut in the exposed portion. 표면상에 제1배선이 패턴되어 형성된 반도체 기판상의 제1절연층상에 제2절연층을 형성시켜주는 제1공정과, 상기 제1배선상의 일정 지역에서 제1배선의 폭보다 넓게 상기 제2절연층을 제거하여 개구부를 형성시켜주는 제2공정과, 상기 개구부내에 노출된 상기 제1배선의 상부표면 및 측면과 접촉하여 지나가도록 제2배선을 형성시켜주는 제3공정을 구비하여 이루어진 것을 특징으로 하는 반도체 장치의 제조방법.Forming a second insulating layer on the first insulating layer on the semiconductor substrate on which the first wiring is patterned on the surface; and the second insulating layer having a width wider than the width of the first wiring in a predetermined region on the first wiring. And a second process of removing the layer to form an opening, and a third process of forming a second wiring so as to be in contact with the upper surface and the side surface of the first wiring exposed in the opening. A method of manufacturing a semiconductor device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920017606A 1992-09-26 1992-09-26 Semiconductor device and method for manufacture of the same KR100207443B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920017606A KR100207443B1 (en) 1992-09-26 1992-09-26 Semiconductor device and method for manufacture of the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920017606A KR100207443B1 (en) 1992-09-26 1992-09-26 Semiconductor device and method for manufacture of the same

Publications (2)

Publication Number Publication Date
KR940008067A true KR940008067A (en) 1994-04-28
KR100207443B1 KR100207443B1 (en) 1999-07-15

Family

ID=19340172

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920017606A KR100207443B1 (en) 1992-09-26 1992-09-26 Semiconductor device and method for manufacture of the same

Country Status (1)

Country Link
KR (1) KR100207443B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100892243B1 (en) * 2005-07-08 2009-04-09 주식회사 토이론 Foam pad for pipe

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100892243B1 (en) * 2005-07-08 2009-04-09 주식회사 토이론 Foam pad for pipe

Also Published As

Publication number Publication date
KR100207443B1 (en) 1999-07-15

Similar Documents

Publication Publication Date Title
KR920005304A (en) Wiring connection structure of semiconductor integrated circuit device and its manufacturing method
KR960019784A (en) Semiconductor device and manufacturing method thereof
KR880013239A (en) Connection hole formation method of semiconductor device
KR950010067A (en) Semiconductor device including a plurality of transistors
KR900001003A (en) Manufacturing Method of Semiconductor Device
KR950004532A (en) Highly Integrated Semiconductor Wiring Structure and Manufacturing Method
KR920020618A (en) Wiring connection structure of semiconductor device and manufacturing method thereof
KR910020932A (en) Semiconductor device and manufacturing method
KR970060467A (en) Semiconductor device
KR950012628A (en) Semiconductor device with double metallization layers for scribe line
KR950021526A (en) Semiconductor device and manufacturing method thereof
KR930020590A (en) Etching method of metal thin film mainly composed of aluminum and manufacturing method of thin film transistor
KR870008388A (en) Semiconductor device and manufacturing method
KR940008067A (en) Semiconductor device and manufacturing method thereof
KR910003783A (en) Semiconductor device and manufacturing method
KR920018889A (en) Interlayer contact structure and method of semiconductor device
KR910019194A (en) Semiconductor device and manufacturing method
KR950025908A (en) Semiconductor device manufacturing method
KR980005930A (en) Semiconductor device and manufacturing method
KR900003974A (en) Manufacturing Method of Semiconductor Device
KR950021414A (en) Connecting process between multilayer wirings of semiconductor device
KR870001655A (en) Manufacturing Method of Semiconductor Device
KR950027946A (en) Method for manufacturing metallization contact of semiconductor device
KR920010820A (en) Semiconductor device connection device and manufacturing method
KR890011059A (en) Manufacturing Method of Semiconductor Device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20070327

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee