KR950021412A - Power Line Formation Method of Semiconductor Device - Google Patents

Power Line Formation Method of Semiconductor Device Download PDF

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Publication number
KR950021412A
KR950021412A KR1019930026656A KR930026656A KR950021412A KR 950021412 A KR950021412 A KR 950021412A KR 1019930026656 A KR1019930026656 A KR 1019930026656A KR 930026656 A KR930026656 A KR 930026656A KR 950021412 A KR950021412 A KR 950021412A
Authority
KR
South Korea
Prior art keywords
power line
semiconductor device
formation method
line formation
power lines
Prior art date
Application number
KR1019930026656A
Other languages
Korean (ko)
Inventor
도재익
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019930026656A priority Critical patent/KR950021412A/en
Publication of KR950021412A publication Critical patent/KR950021412A/en

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  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 전원선 형성방법에 관한 것으로, 반도체 칩(chip)의 회로 설계에 있어 고전위 및 저전위 전원선 각각을 각기 다른층에 배열, 형성하므로써 불순물에 의한 전원선간의 단락 및 금속층의 에칭부족으로 인한 전원선간의 단락을 방지할 수 있는 반도체 소자의 전원선 배치 방법에 관해 기술된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a power line of a semiconductor device. In the circuit design of a semiconductor chip, short and metal layers between power lines caused by impurities are formed by arranging and forming high and low potential power lines in different layers. A power line arrangement method of a semiconductor device capable of preventing a short circuit between power lines due to lack of etching is described.

Description

반도체 소자의 전원선 형성방법Power Line Formation Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래의 반도체 소자의 전원선 배치도이다.1 is a layout view of power lines of a conventional semiconductor device.

제2도는 본 발명에 따른 반도체 소자의 전원선 형성방법을 나타내는 단면도이다.2 is a cross-sectional view showing a power line forming method of a semiconductor device according to the present invention.

제3도는 본 발명의 제1실시예이다.3 is a first embodiment of the present invention.

Claims (1)

반도체 소자의 전원선 형성방법에 있어서, 절연체(1)를 사이에 두고 고전위 전원선용 제1금속층(2) 및 저전위 전원선용 제2금속층(3) 각각을 분리하여 형성하는 것을 특징으로 하는 반도체 소자의 전원선 형성방법.A method for forming a power line of a semiconductor device, characterized in that the first metal layer (2) for high potential power line and the second metal layer (3) for low potential power line are formed separately with an insulator (1) therebetween. Method for forming a power line of the device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930026656A 1993-12-07 1993-12-07 Power Line Formation Method of Semiconductor Device KR950021412A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930026656A KR950021412A (en) 1993-12-07 1993-12-07 Power Line Formation Method of Semiconductor Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930026656A KR950021412A (en) 1993-12-07 1993-12-07 Power Line Formation Method of Semiconductor Device

Publications (1)

Publication Number Publication Date
KR950021412A true KR950021412A (en) 1995-07-26

Family

ID=66825767

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930026656A KR950021412A (en) 1993-12-07 1993-12-07 Power Line Formation Method of Semiconductor Device

Country Status (1)

Country Link
KR (1) KR950021412A (en)

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