KR980006117A - Wiring method of semiconductor device - Google Patents
Wiring method of semiconductor device Download PDFInfo
- Publication number
- KR980006117A KR980006117A KR1019960020645A KR19960020645A KR980006117A KR 980006117 A KR980006117 A KR 980006117A KR 1019960020645 A KR1019960020645 A KR 1019960020645A KR 19960020645 A KR19960020645 A KR 19960020645A KR 980006117 A KR980006117 A KR 980006117A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- upper metal
- wiring layer
- metal film
- film
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명 반도체 소자에 관한 것으로 특히, 반도체 제품의 각 개별 소자를 전기적으로 연결시키는 적층 구조의 금속막 반도체 소자의 배선 제작에 관한 것이다. 이를 위한 본 발명 일실시예의 반도체 소자의 배선 제작방법은 웨이퍼 소정 영역에 제1금속 배선층과 제1상부 금속막 형성하는 단계; 상기 제1상부 금속막상의 소정영역에 제2금속 배선층과 상기 제2금속 배선층 위에 제2상부 금속막 형성하는 단계; 상기 제2상부 금속막 까지 평탄하게 제1절연막 형성하는 단계; 상기 제1절연막 상에 제3금속 배선층 및 제3상부 금속막 형성하는 단계; 상기 제3상부 금속막 상의 소정 영역에 제4금속 배선층과 제4상부 금속막 형성하는 단계; 상기 제4상부 금속막까지 평탄하게 제2절연막 형성하는 단계; 상기 제2절연막 상에 제4상부 금속막과 연결되도록 제5금속 배선층 형성하는 단계; 상기 제5금속 배선층 상에 제5상부 금속막 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to wire fabrication of metal film semiconductor devices having a laminated structure that electrically connects individual elements of a semiconductor product. According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method comprising: forming a first metal wiring layer and a first upper metal film on a predetermined region of a wafer; Forming a second upper metal film on the second metal wiring layer and the second metal wiring layer in a predetermined region on the first upper metal film; Forming a first insulating film evenly up to the second upper metal film; Forming a third metal wiring layer and a third upper metal layer on the first insulating layer; Forming a fourth metal wiring layer and a fourth upper metal film in a predetermined region on the third upper metal film; Forming a second insulating film evenly up to the fourth upper metal film; Forming a fifth metal wiring layer on the second insulating layer to be connected to a fourth upper metal layer; And forming a fifth upper metal film on the fifth metal wiring layer.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제2도는 본 발명 일실시예의 반도체 소자의 배선 공정 단면도.2 is a cross-sectional view of a wiring process of a semiconductor device according to one embodiment of the present invention.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960020645A KR100186515B1 (en) | 1996-06-10 | 1996-06-10 | Method for forming layer of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960020645A KR100186515B1 (en) | 1996-06-10 | 1996-06-10 | Method for forming layer of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR980006117A true KR980006117A (en) | 1998-03-30 |
| KR100186515B1 KR100186515B1 (en) | 1999-04-15 |
Family
ID=19461344
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960020645A KR100186515B1 (en) | 1996-06-10 | 1996-06-10 | Method for forming layer of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100186515B1 (en) |
-
1996
- 1996-06-10 KR KR1019960020645A patent/KR100186515B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR100186515B1 (en) | 1999-04-15 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20101125 Year of fee payment: 13 |
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| LAPS | Lapse due to unpaid annual fee |