KR840000984A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
KR840000984A
KR840000984A KR1019820003080A KR820003080A KR840000984A KR 840000984 A KR840000984 A KR 840000984A KR 1019820003080 A KR1019820003080 A KR 1019820003080A KR 820003080 A KR820003080 A KR 820003080A KR 840000984 A KR840000984 A KR 840000984A
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South Korea
Prior art keywords
aluminum
bonding
insulating film
conductor layer
film
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KR1019820003080A
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Korean (ko)
Inventor
다모쯔 우사미
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미쓰다 가쓰시게
가부시기 가이샤 히다찌 세이사꾸쇼
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Priority claimed from JP56115080A external-priority patent/JPS5817627A/en
Priority claimed from JP56122994A external-priority patent/JPS5825241A/en
Application filed by 미쓰다 가쓰시게, 가부시기 가이샤 히다찌 세이사꾸쇼 filed Critical 미쓰다 가쓰시게
Publication of KR840000984A publication Critical patent/KR840000984A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Wire Bonding (AREA)

Abstract

내용 없음No content

Description

반도체 장치와 그의 제조 방법Semiconductor device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 의하여서 만들어진 반도체 장치의 완성품의 일부 단면도. 제2도는 제1도에 표시한 반도체 장치에서 본딩패드 부분을 크게 확대한 대략적인 평면도.1 is a partial cross-sectional view of a finished product of a semiconductor device made in accordance with the present invention. FIG. 2 is a plan view schematically enlarging a bonding pad portion in the semiconductor device shown in FIG.

Claims (14)

다음과 같은 구성으로 된 반도체 장치Semiconductor device with the following configuration (1) 내부에 회로소자가 형성된 반도체 기판. 상기 반도체 기판에는 그의 주면상(主面上)에 형성된 절연막 위에 이온화 경향이 있는 금속 첨가물이 함유된 알미늄재료의 본딩패드가 만들어져 있는 것임.(1) A semiconductor substrate having a circuit element formed therein. In the semiconductor substrate, a bonding pad made of aluminum material containing a metal additive having a tendency to ionize is formed on an insulating film formed on the main surface thereof. (2) 상기의 반도체 기판 근방에 설치된 리드(2) a lead provided near the semiconductor substrate (3) 한쪽 끝이 상기의 본딩패드에 접속되어 있고 다른쪽 끝이 전기 리드에 접속되어 있는 알미늄재료로 된 본딩와이어, 상기한 본딩와이어의 알미늄 재료는 전기의 본딩패드의 알미늄재료에 첨가된 금속 첨가물과 동일한 첨가물을 함유하는 것임. 그리고,(3) Bonding wires made of an aluminum material, one end of which is connected to the bonding pad and the other end of which is connected to an electrical lead, wherein the aluminum material of the bonding wire is a metal added to the aluminum material of the bonding pad of electricity. It contains the same additives as the additives. And, (4) 전기한 본딩와이어의 표면과, 전기한 본딩패드에 상기 밖으로 노출된 본딩패드의 표면에 형성된 알미늄산화물의 피막(4) A film of aluminum oxide formed on the surface of the bonding wire described above and the surface of the bonding pad exposed out of the bonding pad described above 특허청구범위 1항에 따르는 반도체 장치에서 전기한 본딩패드에 첨가되는 금속 첨가물을 구리(銅)로 하는 것.The metal additive added to the bonding pad described above in the semiconductor device according to claim 1 is copper. 다음 공정에 따르는 반도체 장치의 제조방법.The manufacturing method of the semiconductor device which concerns on the following process. (1) 내부에 회로소자가 형성되어 있고, 또 그의 주면상에 형성된 절연막 위에 만들어진 알미늄재료로된 여러개의 본딩패드가 있는 반도체 기판과, 상기 반도체 기판에 근접하여 리드의 끝(단자)이 설치되어 있고, 또 전기의 본딩패드와 각각 대응하도록 배치되어 있는 여러개의 리드를 제작하는 공정.(1) A circuit element is formed inside, and a semiconductor substrate having a plurality of bonding pads made of aluminum material formed on an insulating film formed on the main surface thereof, and a lead end (terminal) is provided in proximity to the semiconductor substrate. And fabricating a plurality of leads arranged to correspond to the bonding pads of the above, respectively. (2) 전기한 각 본딩패드와 대응하는 각 리드와의 사이를 알미늄 재료로 된 본딩 와이어로 접속시키는 공정.(2) A step of connecting the bonding pads described above and the corresponding leads with a bonding wire made of aluminum. (3) 그리고, 전기한 여러개의 리드들을 모두 동일한 전위가 되게 하기 위하여 그들을 서로 전기적으로 접속시킨 상태에서 전기한 본딩와이어들과 또 본딩패드들의 표면을 산화시키는 방법에 의하여 그들의 표면에 알미늄산화피막을 형성하는 공정.(3) In order to oxidize the surfaces of the bonding wires and the bonding pads which were electrically connected to each other in order to bring the same plurality of leads into the same potential, an aluminum oxide film was deposited on their surfaces. Forming process. 특허청구범위 제3항에 따르는 반도체 장치의 제조방법에다 다음의 공정을 더 포함하는 것.The method of manufacturing a semiconductor device according to claim 3, further comprising the following steps. (1) 반도체 기판과 리드의 일부를 레진에 의하여 몰딩하는 공정.(1) A step of molding a semiconductor substrate and a part of the lead with a resin. (2) 그리고, 리드표면에 형성된 산화막을 제거하는 공정.(2) A step of removing the oxide film formed on the lead surface. 다음과 같은 구성으로 된 반도체장치Semiconductor device with the following configuration (1) 반도체 기판상의 제1의 절연막 위에다 형성된 제1의 도체층(1) The first conductor layer formed on the first insulating film on the semiconductor substrate (2) 상기 제1의 도체층 위에다 형성시킨 제2의 절연막 상기 제2의 절연막에는 전기한 제1의 도체층의 일부를 노출시키는 접점 구멍이 있다.(2) Second insulating film formed on the first conductor layer The second insulating film has contact holes for exposing a part of the first conductor layer. (3) 상기 제1의 절연막 위에다 전기한 접점구멍에 의하여 노출된 전기 제1의 도체층의 부분을 덮고 있도록 형성된 알미늄의 제2의 도체층.(3) A second conductor layer of aluminum formed on the first insulating film so as to cover a portion of the first conductor layer exposed by the contact hole that is electrically provided. (4) 전기한 접점구멍을 덮고 있도록 상기 제2의 도체층에 접속된 본딩와이어, 그리고,(4) a bonding wire connected to said second conductor layer so as to cover said contact hole, and (5) 상기의 본딩와이어가 접속된 부분을 제외한 전기 제2의 도체층의 다른 부분의 표면에 형성된 알미늄산화물의 피막.(5) A film of aluminum oxide formed on the surface of another portion of the second electrical conductor layer except for the portion to which the bonding wire is connected. 특허청구범위 제5항에서 전기한 본딩와이어는 알미늄으로 된 것이고 그 표면에 알미늄의 산화피막이 형성되어 있는 것.The bonding wire described in claim 5 is made of aluminum, and an aluminum oxide film is formed on the surface thereof. 특허청구범위 제5항과 또는 제6항의 어느 하나의 청구범위에 따르는 반도체 장치에서 전기한 제1의 도체층이 알미늄으로 되어 있는 것.The first conductor layer described above in the semiconductor device according to any one of claims 5 and 6 is made of aluminum. 다음과 같은 공정에 따르는 반도체 장치의 제조방법.The manufacturing method of the semiconductor device which concerns on the following processes. (1) 반도체 기판상의 제1의 절연막 위에다 제1의 도체층을 형성하는 공정.(1) A step of forming a first conductor layer on a first insulating film on a semiconductor substrate. (2) 상기 제1의 도체층 위에다 제2의 절연막을 형성하는 공정.(2) A step of forming a second insulating film on the first conductor layer. 상기 제2의 절연막에는 전기 제1도의 도체층의 일부를 노출시키는 접점 구멍이 있다.The second insulating film has a contact hole for exposing a part of the conductor layer of FIG. (3) 상기의 접점구멍 내부와 전기 제2의 절연막 위에다 제2의 도체층을 형성하는 공정.(3) A step of forming a second conductor layer on the inside of the contact hole and the second electric insulating film. (4) 전기한 접점구멍을 덮고 있도록 본딩와이어를 제2의 도체층에 접속하는 공정.(4) The process of connecting a bonding wire to a 2nd conductor layer so that the said contact hole may be covered. (5) 상기의 본딩와이어가 접속된 부분을 제외한 전기 제2의 도체층의 여타(余他) 부분의 표면에 알미늄 산화물의 피막을 형성하는 공정.(5) A step of forming an aluminum oxide film on the surface of the other part of the second conductor layer except for the part to which the bonding wire is connected. 특허청구범위 제8항에서 위에 말한 본딩와이어는 알미늄으로 된 것이고, 그 표면에 전기 제2의 도체층의 알미늄산화물의 피막을 형성하는 과정에서 동시에 알미늄산화피막을 형성하는 것.The above-mentioned bonding wire of claim 8 is made of aluminum, and simultaneously forming an aluminum oxide film in the process of forming an aluminum oxide film of the second conductor layer on the surface thereof. 다음과 같은 구성으로 된 반도체장치.A semiconductor device having the following configuration. (1) 반도체기판상의 제1의 절연막 위에 형성된 알미늄중.(1) Among the aluminum formed on the first insulating film on the semiconductor substrate. (2) 상기의 알미늄층의 표면에 형성된 알미늄산화물의 피막.(2) A film of aluminum oxide formed on the surface of the aluminum layer. (3) 상기의 알미늄산화물의 피막위에 형성된 제2의 절연막.(3) A second insulating film formed on the film of aluminum oxide. (4) 본딩패드를 형성하게 되는 전기한 알미늄층의 일부를 노출하기 위하여 전기한 알미늄의 산화막과 전기 제2의 절연막에 형성된 구멍.(4) Holes formed in the oxide film of aluminum and the second insulating film for exposing a portion of the aluminum layer to form a bonding pad. (5) 상기의 구멍으로 노출된 전기의 알미늄층에 접속된 접속부가 있는 본딩와이어.(5) Bonding wires with a connection part connected to the aluminum layer of electricity exposed by said hole. (6) 상기 본딩와이어의 상기 접속부 주위 부분이 전기의 구멍으로 부터 노출된 알미늄층의 표면에 형성된 알미늄산화물의 피막.(6) A film of aluminum oxide formed on the surface of the aluminum layer in which a portion around the connecting portion of the bonding wire is exposed from an electric hole. 특허청구 범위 제10항에서 전기한 본딩와이어는 알미늄으로 된 것이고, 그 표면에 알미늄의 피막이 형성되어 있는 것.The bonding wire described in claim 10 is made of aluminum, and an aluminum film is formed on the surface thereof. 다음과 같은 공정에 따르는 반도체장치의 제조방법.A method for manufacturing a semiconductor device according to the following process. (1) 반도체기판상의 제1의 절연막 위에 알미늄으로 된 배선층과 본딩패드를 형성하는 공정.(1) A step of forming an aluminum wiring layer and a bonding pad on a first insulating film on a semiconductor substrate. (2) 상기의 알미늄과 또 본딩패드가 전기의 제1의 절연막과 접촉되어 있지 아니한 면의 표면에 알미늄의 산화피막을 형성하는 공정.(2) A step of forming an aluminum oxide film on the surface of the surface where the aluminum and the bonding pad are not in contact with the first electrical insulating film. (3) 상기한 알미늄의 산화피막 위에 반도체기판을 덮고 있도록 제2의 절연막을 형성하는 공정.(3) forming a second insulating film on the aluminum oxide film so as to cover the semiconductor substrate. (4) 본딩패드의 표면의 일부가 노출되도록 전기의 알미늄산화피막과 상기의 제2의 절연막을 국부적으로 제거하는 공정.(4) A step of locally removing the aluminum oxide film and the second insulating film so that a part of the surface of the bonding pad is exposed. (5) 본딩패드의 노출된 부위에 와이어를 본딩하는 공정.(5) Bonding the wire to the exposed portion of the bonding pad. (6) 본딩패드의 상기 노출된 부위에 표면에서 상기한 와이어가 본딩된 부분을 제외하고 나머지 표면에다 알미늄의 산화피막을 형성하는 공정.(6) forming an aluminum oxide film on the remaining surface of the exposed pad except for the portion where the wire is bonded to the exposed portion of the bonding pad. 특허청구 범위 제12항에서 전기한 본딩와이어는 알미늄으로 만든 가이고, 그 표면에다 알미늄의 산화피막을 형성하는데, 이가은 본딩패드의 노출된 표면에서 본딩와이어가 본딩된 부분을 제외한 나머지 표면에다 알미늄의 산화막을 형성할 때에 동시에 형성한다.The bonding wire described in claim 12 is made of aluminum, and forms an oxide film of aluminum on the surface thereof. When the oxide film is formed, it is formed simultaneously. 특허청구 범위 제1,5,6,7,10,11항 가운데서 어느 하나에 따르는 반도체 장치에서 상기한 반도체 기판과 본딩와이어가 레진으로 몰딩된 것.In the semiconductor device according to any one of claims 1,5,6,7,10,11, wherein the semiconductor substrate and the bonding wire are molded with a resin. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019820003080A 1981-07-24 1982-07-09 Semiconductor device and manufacturing method thereof KR840000984A (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP56-115080~2 1981-07-24
JP56115080A JPS5817627A (en) 1981-07-24 1981-07-24 Semiconductor integrated circuit device and manufacture thereof
JP56-122994~2 1981-08-07
JP56122994A JPS5825241A (en) 1981-08-07 1981-08-07 Manufacture of semiconductor i.c. device

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KR840000984A true KR840000984A (en) 1984-03-26

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KR1019820003080A KR840000984A (en) 1981-07-24 1982-07-09 Semiconductor device and manufacturing method thereof

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100482655B1 (en) * 2002-06-28 2005-04-13 윤연옥 Method for combine with pin of a pendant

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100482655B1 (en) * 2002-06-28 2005-04-13 윤연옥 Method for combine with pin of a pendant

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