KR940012625A - Capacitor Manufacturing Method - Google Patents

Capacitor Manufacturing Method Download PDF

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Publication number
KR940012625A
KR940012625A KR1019920021021A KR920021021A KR940012625A KR 940012625 A KR940012625 A KR 940012625A KR 1019920021021 A KR1019920021021 A KR 1019920021021A KR 920021021 A KR920021021 A KR 920021021A KR 940012625 A KR940012625 A KR 940012625A
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KR
South Korea
Prior art keywords
insulating film
polysilicon
insulating
forming
etching
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Application number
KR1019920021021A
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Korean (ko)
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KR960011649B1 (en
Inventor
전영권
Original Assignee
문정환
금성일렉트론 주식회사
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Priority to KR92021021A priority Critical patent/KR960011649B1/en
Publication of KR940012625A publication Critical patent/KR940012625A/en
Application granted granted Critical
Publication of KR960011649B1 publication Critical patent/KR960011649B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

본발명은 반도체 장치의 커패시터 제조방법에 관한 것으로, 종래의 커패시터 제조방법은 링구조를 형성하기 위하여 폴리실리콘을 3차에 걸쳐 증착함으로 공정이 복잡하며 폴리실리콘층간에 발생한 자연산화막이 제거되지 않아서 커패시터 자체가 실현되지 않을 가능성이 높다.The present invention relates to a method of manufacturing a capacitor of a semiconductor device, the conventional method of manufacturing a capacitor is complicated by the process of depositing polysilicon over three times to form a ring structure, and the natural oxide film generated between the polysilicon layer is not removed capacitor It is very unlikely that it will be realized.

본발명은 폴리실리콘막을 1회 형성하고 2단계로 식각함으로써 단순한 공정을 적용하여 커패시턴스를 증가시키는 효과가 있으며 폴리실리콘막 표면에 자연산화막이 존재하지 않아서 소자 특성이 향상된다.The present invention has the effect of increasing capacitance by applying a simple process by forming a polysilicon film once and etching in two steps, and the device characteristics are improved because there is no natural oxide film on the surface of the polysilicon film.

Description

커패시터 제조방법Capacitor Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본발명의 메모리셀 커패시터 공정단면도.2 is a cross-sectional view of a memory cell capacitor process according to the present invention.

Claims (8)

실리콘기판(11)위에 메모리셀 트랜지스터를 형성하고 전면에 평탄화용 제1절연막(12)과 제2절연막(13) 제3절연막(14)을 차례로 형성하는 제1공정과, 상기 제1, 제2, 제3절연막(12, 13, 14)을 선택적으로 제거하어 베리드콘택홀을 형성하고 전면에 도핑된 폴리실리콘(15)을 증착하는 제2공정과, 폴리실리콘(15)위에 제4절연막(16)을 증착하고 제4절연막(16)융기부가 형성되도록 패터닝하는 제3공정과, 상기 패터닝된 제4절연막(16)측벽에 제5절연막(17)으로 측벽을 형성하는 제4공정과, 상기 제4, 제5절연막(16, 17)을 마스크로 이용하여 상기 폴리실리콘(15)을 1차식각하여 단차를 형성하는 제5공정과, 상기 제4절연막(16)을 제거하고 제5절연막(17) 및 폴리실리콘(15)의 단차가 형성된 측벽에 제6절연막(18)으로 측벽을 형성하는 제6공정과, 제5절연막(17)을 제거하고 제6절연막(18)을 마스크로 이용하여 폴리실리콘(15)을 식각하는 제7공정과, 제6절연막(18)을 제거하고 유전체막과 플레이트를 형성하는 제8공정으로 이루어짐을 특징으로 하는 커패시터 제조방법.A first process of forming a memory cell transistor on the silicon substrate 11 and sequentially forming a planarizing first insulating film 12, a second insulating film 13, and a third insulating film 14 on the entire surface of the silicon substrate 11; And selectively removing the third insulating layers 12, 13, and 14 to form buried contact holes, and depositing the doped polysilicon 15 on the entire surface, and a fourth insulating layer on the polysilicon 15. A third step of depositing 16 and patterning the fourth insulating film 16 to form a ridge, a fourth step of forming a sidewall of the patterned fourth insulating film 16 with a fifth insulating film 17, and A fifth step of forming a step by first etching the polysilicon 15 using the fourth and fifth insulating films 16 and 17 as a mask; and removing the fourth insulating film 16 and removing the fifth insulating film ( 17) and the sixth step of forming the sidewalls with the sixth insulating film 18 on the sidewalls formed with the step of the polysilicon 15, the fifth insulating film 17 is removed and the sixth insulating film 18 is removed. The method for manufacturing a capacitor, characterized a seventh step of etching the polysilicon 15, using as a mask and removing the sixth insulating film 18 and constituted by any of claim 8, the step of forming the dielectric film and the plate. 제1항에 있어서, 제1, 제3, 제4, 제6절연막은 산화막으로 형성함을 특징으로하는 커패시터 제조방법.The method of claim 1, wherein the first, third, fourth, and sixth insulating films are formed of an oxide film. 제1항에 있어서, 제2, 제5절연막은 실리콘질화막으로 형성함을 특징으로 하는 커패시터 제조방법.The method of claim 1, wherein the second and fifth insulating layers are formed of silicon nitride. 제1항에 있어서, 제5절연막 대신 폴리이미드를 형성함을 특징으로 하는 커패시터 제조방법.The method of claim 1, wherein a polyimide is formed in place of the fifth insulating film. 제1항에 있어서, 제2공정의 폴리실리콘증착은 LPCVD법으로 5mTorr이하의 압력에서 520∼620℃의 온도조건으로 두께를 300∼800Å로 증착함을 특징으로 하는 커패시터 제조방법.The method of manufacturing a capacitor according to claim 1, wherein the polysilicon deposition of the second step is performed by LPCVD to a thickness of 300 to 800 kPa at a temperature of 520 to 620 캜 at a pressure of 5 mTorr or less. 제1항에 있어서, 제2, 제3, 제4, 제5절연막은 200Å 이하의 두께로 증착함을 특징으로 하는 커패시터 제조방법.The method of claim 1, wherein the second, third, fourth, and fifth insulating films are deposited to a thickness of 200 μm or less. 제1항에 있어서, 제5공정의 단차형성은 1000∼2000Å두께로 1차식각하여 형성함을 특징으로 하는 커패시터 제조방법.2. The method of claim 1, wherein the step formation in the fifth step is performed by primary etching to a thickness of 1000 to 2000 microseconds. 제1항에 있어서, 제7공정의 폴리실리콘(15)식각은 제5공정에서 1차식각한 부위가 완전히 식각될때까지 식각함을 특징으로 하는 커패시터 제조방법.The method of claim 1, wherein the etching of the polysilicon (15) of the seventh step is etched until the first etched portion is completely etched in the fifth step. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR92021021A 1992-11-10 1992-11-10 Capacitor manufacture KR960011649B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR92021021A KR960011649B1 (en) 1992-11-10 1992-11-10 Capacitor manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR92021021A KR960011649B1 (en) 1992-11-10 1992-11-10 Capacitor manufacture

Publications (2)

Publication Number Publication Date
KR940012625A true KR940012625A (en) 1994-06-24
KR960011649B1 KR960011649B1 (en) 1996-08-24

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Application Number Title Priority Date Filing Date
KR92021021A KR960011649B1 (en) 1992-11-10 1992-11-10 Capacitor manufacture

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KR960011649B1 (en) 1996-08-24

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