KR940012145A - Redundancy Status Decision Circuit of Redundancy System - Google Patents

Redundancy Status Decision Circuit of Redundancy System Download PDF

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Publication number
KR940012145A
KR940012145A KR1019920022866A KR920022866A KR940012145A KR 940012145 A KR940012145 A KR 940012145A KR 1019920022866 A KR1019920022866 A KR 1019920022866A KR 920022866 A KR920022866 A KR 920022866A KR 940012145 A KR940012145 A KR 940012145A
Authority
KR
South Korea
Prior art keywords
redundancy
state
status
determination circuit
information
Prior art date
Application number
KR1019920022866A
Other languages
Korean (ko)
Other versions
KR0139968B1 (en
Inventor
염진섭
Original Assignee
정장호
금성정보통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정장호, 금성정보통신 주식회사 filed Critical 정장호
Priority to KR1019920022866A priority Critical patent/KR0139968B1/en
Publication of KR940012145A publication Critical patent/KR940012145A/en
Application granted granted Critical
Publication of KR0139968B1 publication Critical patent/KR0139968B1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023—Failover techniques
    • G06F11/2028—Failover techniques eliminating a faulty processor or activating a spare
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4286—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a handshaking protocol, e.g. RS232C link
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0002—Serial port, e.g. RS232C

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Hardware Redundancy (AREA)

Abstract

본 발명은 소프트웨어의 도움을 받아 하드웨어적으로 동작/대기상태를 결정함으로써 소프트웨어적으로 이중화상태를 결정하는 이중화 시스템에 적당하도록 된 이중화상태결정회로에 관한것으로, 하드웨어적인 처리와 소프트웨어적인 처리를 병행함으로써 응답시간이 짧으면서 고도한 이중화기능을 구현할 수 있는 이중화 시스템의 이중화상태결정회로에 관한 것이다.The present invention relates to a redundancy state determination circuit suitable for a redundancy system that determines the redundancy state by software by determining the operation / standby state by hardware with the help of software. The present invention relates to a redundancy state determination circuit of a redundancy system capable of implementing a high redundancy function with a short response time.

본 발명은 제어레지스터에 데이터를 기록하는 동작과 상태레지스터의 데이터를 독출하는 동작만으로 동작/대기상태의 결정이 이루어지도록 된 것을 특징으로 한다.The present invention is characterized in that the operation / standby state is determined only by the operation of writing data to the control register and the operation of reading data of the state register.

Description

이중화시스템의 이중화상태 결정회로Redundancy Status Decision Circuit of Redundancy System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 따른 이중화상태 결정회로가 채용된 이중화시스템의 동작을 설명하기 위한 개략적인 구성도,3 is a schematic configuration diagram for explaining the operation of a redundancy system employing a redundancy state determination circuit according to the present invention;

제4도는 본 발명에 따른 이중화상태 결정회로에서 생성되는 논리값을 시스템 각각의 상태에 따라 나타낸 논리값표, 제5도는 논리회로인 상태결정회로의 동작을 설명하기 위한 도면.4 is a logic value table showing logic values generated in a redundant state determination circuit according to each state of the system, and FIG. 5 is a diagram for explaining the operation of the state determination circuit which is a logic circuit.

Claims (1)

이중화 시스템 제어부로 부터 공급된 시스템 상태 정보에 따라 상태 제어 정보를 출력하는 제어 레지스터, 상기 제어 레지스터로부터 공급된 상태 제어정보와 상대편의 상태 정보에 따라 자신의 상태를 결정하고 결정된 자신의 상태에 대응하는 상태정보를 상기 상대편으로 출력함과 동시에 상기 이중화 시스템 제어부 측으로 상태변환 인터럽트 신호를 출력하는 상태결정 회로 및, 상기 상태 결정회로로부터 공급된 상태정보와 상기 상대편의 상태정보를 상기 이중화 시스템 제어부 측으로 공급하는 상태 레지스터를 구비하는 것을 특징으로 하는 이중화 시스템의 이중화 상태 결정회로.A control register for outputting state control information according to the system state information supplied from the redundant system control unit, and determining its own state according to the state control information supplied from the control register and the state information of the other party and corresponding to the determined own state. A status determination circuit for outputting status information to the counterpart and outputting a status conversion interrupt signal to the redundant system controller, and supplying status information supplied from the status determination circuit and status information of the counterpart to the redundant system controller A redundancy status determination circuit of a redundancy system, comprising: a status register. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920022866A 1992-11-30 1992-11-30 Redundancy Status Decision Circuit of Redundancy System KR0139968B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920022866A KR0139968B1 (en) 1992-11-30 1992-11-30 Redundancy Status Decision Circuit of Redundancy System

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920022866A KR0139968B1 (en) 1992-11-30 1992-11-30 Redundancy Status Decision Circuit of Redundancy System

Publications (2)

Publication Number Publication Date
KR940012145A true KR940012145A (en) 1994-06-22
KR0139968B1 KR0139968B1 (en) 1998-07-01

Family

ID=56800390

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920022866A KR0139968B1 (en) 1992-11-30 1992-11-30 Redundancy Status Decision Circuit of Redundancy System

Country Status (1)

Country Link
KR (1) KR0139968B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100305872B1 (en) * 1997-06-03 2001-11-30 박종섭 Duplicated system using state information of the other side

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100305872B1 (en) * 1997-06-03 2001-11-30 박종섭 Duplicated system using state information of the other side

Also Published As

Publication number Publication date
KR0139968B1 (en) 1998-07-01

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