KR920003301A - Data input circuit of dual port memory device - Google Patents

Data input circuit of dual port memory device Download PDF

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Publication number
KR920003301A
KR920003301A KR1019900010958A KR900010958A KR920003301A KR 920003301 A KR920003301 A KR 920003301A KR 1019900010958 A KR1019900010958 A KR 1019900010958A KR 900010958 A KR900010958 A KR 900010958A KR 920003301 A KR920003301 A KR 920003301A
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KR
South Korea
Prior art keywords
data input
pulse
data
input circuit
data latch
Prior art date
Application number
KR1019900010958A
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Korean (ko)
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KR930006619B1 (en
Inventor
정성욱
Original Assignee
김광호
삼성전자 주식회사
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Priority to KR1019900010958A priority Critical patent/KR930006619B1/en
Publication of KR920003301A publication Critical patent/KR920003301A/en
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Publication of KR930006619B1 publication Critical patent/KR930006619B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

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  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

내용 없음.No content.

Description

듀얼포트 메모리소자의 데이타 입력회로Data input circuit of dual port memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 종래의 듀얼포트 메모리소자의 데이타 입력회로도,1 is a data input circuit diagram of a conventional dual port memory device;

제2도는 제1도의 동작파형도,2 is an operating waveform diagram of FIG.

제3도는 이 발명에 따른 듀얼포트 메모리소자의 데이타 입력회로도,3 is a data input circuit diagram of a dual port memory device according to the present invention;

제4도는 제3도의 동작파형도이다.4 is an operating waveform diagram of FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 데이타입력버퍼부 20 : 데이타래치펄스발생부10: data input buffer unit 20: data latch pulse generation unit

30 : 래치부30: latch portion

Claims (4)

듀얼포트메모리소자의 동작시 소정의 펄스폭을 갖는 제1데이타래치펄스를 발생하는 데이타래치펄스발생부와, 블록라이트신호의 유무에 따라 상기 제1데이타래치펄스의 폭을 제어하여 제2데이타 래치펄스를 발생하는 래치부와, 상기 제2데이타래치펄스를 이용하여 데이타입력신호에 따라 데이타입력 또는 컬럼선택신호를 발생하는 입력버퍼로 이루어짐을 특징으로 하는 듀얼포트메모리소자의 데이타 입력회로.A data latch pulse generator for generating a first data latch pulse having a predetermined pulse width during operation of the dual port memory device, and controlling the width of the first data latch pulse according to the presence or absence of a block write signal to control the second data latch; And a latch unit for generating a pulse and an input buffer for generating a data input or a column selection signal according to a data input signal using the second data latch pulse. 제1항에 있어서, 상기 제2데이타래치펄스는, 블록라이트모드시 블록라이트신호와 펄스폭이 동일함을 특징으로 하는 듀얼포트메모리소자의 데이타입력회로.The data input circuit of claim 1, wherein the second data latch pulse has the same pulse width as that of the block write signal in the block write mode. 제1항에 있어서, 상기 제2데이타래치펄스는, 노말라이트모드시 제1데이타래치펄스와 펄스폭이 동일함을 특징으로 하는 듀얼포트 메모리소자의 데이타입력회로.The data input circuit according to claim 1, wherein the second data latch pulse has the same pulse width as the first data latch pulse in the normal light mode. 제1항에 있어서, 상기 래치부는, 2개의 낸드게이트와 한개의 인버터로 구성되는 것을 특징으로 하는 듀얼포트메모리소자의 데이타입력회로.2. The data input circuit of a dual port memory device according to claim 1, wherein the latch unit comprises two NAND gates and one inverter. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900010958A 1990-07-19 1990-07-19 Data input buffer circuit of dual port memory KR930006619B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900010958A KR930006619B1 (en) 1990-07-19 1990-07-19 Data input buffer circuit of dual port memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900010958A KR930006619B1 (en) 1990-07-19 1990-07-19 Data input buffer circuit of dual port memory

Publications (2)

Publication Number Publication Date
KR920003301A true KR920003301A (en) 1992-02-29
KR930006619B1 KR930006619B1 (en) 1993-07-21

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900010958A KR930006619B1 (en) 1990-07-19 1990-07-19 Data input buffer circuit of dual port memory

Country Status (1)

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KR (1) KR930006619B1 (en)

Also Published As

Publication number Publication date
KR930006619B1 (en) 1993-07-21

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