KR940011101B1 - Dram 셀용 고성능 트렌치 커패시터 - Google Patents

Dram 셀용 고성능 트렌치 커패시터 Download PDF

Info

Publication number
KR940011101B1
KR940011101B1 KR1019860700510A KR860700510A KR940011101B1 KR 940011101 B1 KR940011101 B1 KR 940011101B1 KR 1019860700510 A KR1019860700510 A KR 1019860700510A KR 860700510 A KR860700510 A KR 860700510A KR 940011101 B1 KR940011101 B1 KR 940011101B1
Authority
KR
South Korea
Prior art keywords
layer
trench
doped
conductive
extending
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
KR1019860700510A
Other languages
English (en)
Korean (ko)
Other versions
KR880700451A (ko
Inventor
레보위츠 죠셉
토마스 린츠 윌리암
Original Assignee
아메리칸 텔리폰 앤드 텔레그라프 캄파니
마이클 와이. 엡스 라인
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아메리칸 텔리폰 앤드 텔레그라프 캄파니, 마이클 와이. 엡스 라인 filed Critical 아메리칸 텔리폰 앤드 텔레그라프 캄파니
Publication of KR880700451A publication Critical patent/KR880700451A/ko
Application granted granted Critical
Publication of KR940011101B1 publication Critical patent/KR940011101B1/ko
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/01Manufacture or treatment
    • H10B12/02Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03Making the capacitor or connections thereto
    • H10B12/038Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00Resistors, capacitors or inductors
    • H10D1/60Capacitors
    • H10D1/62Capacitors having potential barriers
    • H10D1/66Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
    • H10D1/665Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1408Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
    • H10P32/1414Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/109Memory devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
KR1019860700510A 1984-11-30 1985-11-11 Dram 셀용 고성능 트렌치 커패시터 Expired - Lifetime KR940011101B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US676,677 1984-11-30
US06/676,677 US4694561A (en) 1984-11-30 1984-11-30 Method of making high-performance trench capacitors for DRAM cells
PCT/US1985/002234 WO1986003333A2 (en) 1984-11-30 1985-11-11 High-performance trench capacitors for dram cells

Publications (2)

Publication Number Publication Date
KR880700451A KR880700451A (ko) 1988-03-15
KR940011101B1 true KR940011101B1 (ko) 1994-11-23

Family

ID=24715497

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860700510A Expired - Lifetime KR940011101B1 (ko) 1984-11-30 1985-11-11 Dram 셀용 고성능 트렌치 커패시터

Country Status (7)

Country Link
US (1) US4694561A (https=)
EP (1) EP0203960B1 (https=)
JP (1) JPH0691210B2 (https=)
KR (1) KR940011101B1 (https=)
CA (1) CA1244143A (https=)
DE (1) DE3579454D1 (https=)
WO (1) WO1986003333A2 (https=)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5023196A (en) * 1990-01-29 1991-06-11 Motorola Inc. Method for forming a MOSFET with substrate source contact
TW214610B (en) * 1992-08-31 1993-10-11 Siemens Ag Method of making contact for semiconductor device
US5627092A (en) * 1994-09-26 1997-05-06 Siemens Aktiengesellschaft Deep trench dram process on SOI for low leakage DRAM cell
US5652170A (en) * 1996-01-22 1997-07-29 Micron Technology, Inc. Method for etching sloped contact openings in polysilicon
US5793075A (en) * 1996-07-30 1998-08-11 International Business Machines Corporation Deep trench cell capacitor with inverting counter electrode
US6057216A (en) * 1997-12-09 2000-05-02 International Business Machines Corporation Low temperature diffusion process for dopant concentration enhancement
US6001704A (en) * 1998-06-04 1999-12-14 Vanguard International Semiconductor Corporation Method of fabricating a shallow trench isolation by using oxide/oxynitride layers
US6498381B2 (en) * 2001-02-22 2002-12-24 Tru-Si Technologies, Inc. Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same
US6835977B2 (en) * 2002-03-05 2004-12-28 United Microelectronics Corp. Variable capactor structure
US7989922B2 (en) * 2008-02-08 2011-08-02 International Business Machines Corporation Highly tunable metal-on-semiconductor trench varactor
KR102258769B1 (ko) 2011-10-14 2021-06-01 지엘팜텍주식회사 장용소화효소제 및 그 제조방법
TWI691052B (zh) * 2019-05-07 2020-04-11 力晶積成電子製造股份有限公司 記憶體結構及其製造方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3387286A (en) * 1967-07-14 1968-06-04 Ibm Field-effect transistor memory
US3928095A (en) * 1972-11-08 1975-12-23 Suwa Seikosha Kk Semiconductor device and process for manufacturing same
US3969746A (en) * 1973-12-10 1976-07-13 Texas Instruments Incorporated Vertical multijunction solar cell
DE2449688C3 (de) * 1974-10-18 1980-07-10 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Herstellung einer dotierten Zone eines Leitfähigkeitstyps in einem Halbleiterkörper
JPS5856266B2 (ja) * 1977-02-03 1983-12-14 テキサス インスツルメンツ インコ−ポレイテツド Mosメモリ
FR2426335A1 (fr) * 1978-05-19 1979-12-14 Radiotechnique Compelec Dispositif semi-conducteur monolithique comportant une pluralite de cellules photosensibles
EP0009910B1 (en) * 1978-09-20 1985-02-13 Fujitsu Limited Semiconductor memory device and process for fabricating the device
US4274892A (en) * 1978-12-14 1981-06-23 Trw Inc. Dopant diffusion method of making semiconductor products
US4353086A (en) * 1980-05-07 1982-10-05 Bell Telephone Laboratories, Incorporated Silicon integrated circuits
DK145585C (da) * 1980-05-09 1988-07-25 Schionning & Arve As Taetningsring
JPS5937406B2 (ja) * 1980-07-28 1984-09-10 ダイキン工業株式会社 冷凍装置
JPS58137245A (ja) * 1982-02-10 1983-08-15 Hitachi Ltd 大規模半導体メモリ
US4472212A (en) * 1982-02-26 1984-09-18 At&T Bell Laboratories Method for fabricating a semiconductor device
JPS58154256A (ja) * 1982-03-10 1983-09-13 Hitachi Ltd 半導体装置
JPS58171832A (ja) * 1982-03-31 1983-10-08 Toshiba Corp 半導体装置の製造方法
US4471524A (en) * 1982-06-01 1984-09-18 At&T Bell Laboratories Method for manufacturing an insulated gate field effect transistor device
JPS59117258A (ja) * 1982-12-24 1984-07-06 Hitachi Ltd 半導体装置の製造方法
JPS59184555A (ja) * 1983-04-02 1984-10-19 Nippon Telegr & Teleph Corp <Ntt> 半導体集積回路装置およびその製造方法
US4569701A (en) * 1984-04-05 1986-02-11 At&T Bell Laboratories Technique for doping from a polysilicon transfer layer

Also Published As

Publication number Publication date
CA1258539C (https=) 1989-08-15
US4694561A (en) 1987-09-22
WO1986003333A2 (en) 1986-06-05
KR880700451A (ko) 1988-03-15
DE3579454D1 (de) 1990-10-04
EP0203960A1 (en) 1986-12-10
JPH0691210B2 (ja) 1994-11-14
JPS62500972A (ja) 1987-04-16
EP0203960B1 (en) 1990-08-29
CA1244143A (en) 1988-11-01
WO1986003333A3 (en) 1986-07-17

Similar Documents

Publication Publication Date Title
US4742018A (en) Process for producing memory cell having stacked capacitor
US6171923B1 (en) Method for fabricating a DRAM cell structure on an SOI wafer incorporating a two dimensional trench capacitor
US5336912A (en) Buried plate type DRAM
US5547893A (en) method for fabricating an embedded vertical bipolar transistor and a memory cell
KR100320332B1 (ko) 반도체 장치 및 그 제조 방법
US5780338A (en) Method for manufacturing crown-shaped capacitors for dynamic random access memory integrated circuits
US5792689A (en) Method for manufacturing double-crown capacitors self-aligned to node contacts on dynamic random access memory
EP0430404B1 (en) Method of manufacturing a capacitor for a DRAM cell
US5716862A (en) High performance PMOSFET using split-polysilicon CMOS process incorporating advanced stacked capacitior cells for fabricating multi-megabit DRAMS
US5523542A (en) Method for making dynamic random access memory cell capacitor
US5027172A (en) Dynamic random access memory cell and method of making thereof
US5025295A (en) Three-dimensional one-dimensional cell arrangement for dynamic semiconductor memories and method for the manufacture of a bit line contact
KR940011101B1 (ko) Dram 셀용 고성능 트렌치 커패시터
US5429979A (en) Method of forming a dram cell having a ring-type stacked capacitor
US5326714A (en) Method of making a fully used tub DRAM cell
US6872629B2 (en) Method of forming a memory cell with a single sided buried strap
JPH06125054A (ja) メモリセル及びその製造方法
US5795804A (en) Method of fabricating a stack/trench capacitor for a dynamic random access memory (DRAM)
US6489646B1 (en) DRAM cells with buried trench capacitors
US5396456A (en) Fully used tub DRAM cell
JPH0715949B2 (ja) Dramセル及びその製造方法
KR100566411B1 (ko) 반도체기억장치및그제조방법
US5534457A (en) Method of forming a stacked capacitor with an &#34;I&#34; shaped storage node
US5429976A (en) Self-aligned method for forming polysilicon word lines on top of gate electrodes to increase capacitance of a stacked capacitor in a DRAM cell
EP0376685B1 (en) Semiconductor memory having an increased cell capacitance in a restricted cell area

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

G160 Decision to publish patent application
PG1605 Publication of application before grant of patent

St.27 status event code: A-2-2-Q10-Q13-nap-PG1605

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 10

FPAY Annual fee payment

Payment date: 20041115

Year of fee payment: 11

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 11

EXPY Expiration of term
PC1801 Expiration of term

St.27 status event code: N-4-6-H10-H14-oth-PC1801

Not in force date: 20051112

Ip right cessation event data comment text: Termination Category : EXPIRATION_OF_DURATION

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000