KR940010569B1 - Ldd-transistor and manufacturing method thereof - Google Patents
Ldd-transistor and manufacturing method thereof Download PDFInfo
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- KR940010569B1 KR940010569B1 KR1019910024204A KR910024204A KR940010569B1 KR 940010569 B1 KR940010569 B1 KR 940010569B1 KR 1019910024204 A KR1019910024204 A KR 1019910024204A KR 910024204 A KR910024204 A KR 910024204A KR 940010569 B1 KR940010569 B1 KR 940010569B1
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- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000012535 impurity Substances 0.000 claims abstract description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 150000004767 nitrides Chemical class 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 3
- 238000005530 etching Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 7
- 230000005684 electric field Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
Description
제 1a~c 도는 종래 LDD트랜지스터의 제조공정도.1a to c is a manufacturing process diagram of a conventional LDD transistor.
제 2a~f 도는 본발명에 따른 LDD트랜지스터의 제조공정도.2a to f is a manufacturing process of the LDD transistor according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 기판 21, 22, 26 : 산화막10: substrate 21, 22, 26: oxide film
23 : 게이트폴리 24, 30 : 측벽산화막23: gate poly 24, 30: sidewall oxide film
25 : 질화막 27, 29, 31 : 불순물영역25 nitride film 27, 29, 31 impurity region
28 : 폴리실리콘 측벽28: polysilicon sidewall
본 발명은 LDD(Lightly Doped Drain) 트랜지스터의 구조와 그 제조방법에 관한 것으로, 특히 핫 캐리어 효과(hot carrier effect)와 GIDL(Gate Induced Drain Leakage : 게이트에 의한 드레인 누설전류) 및 전류 드라이빙(currentdriving)을 개선한 LDD트랜지스터의 구조와 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a LDD (Lightly Doped Drain) transistor and a method of manufacturing the same. In particular, the hot carrier effect and the gate induced drain leakage (GIDL) and current driving are shown. It relates to a structure of the LDD transistor with improved quality and a method of manufacturing the same.
제 1 도는 종래 LDD트랜지스터의 제조공정도로서, 먼저 제 1a 도에 도시한 바와 같이 p형 기판(10) 상에 국부산화막(LOCOS : LoCal Oxidation of Silicon)공정을 이용하여 필드산화막(11)을 성장시키고, 게이트 산화막(12)을 성장시킨 다음 문턱 전압(Vth: threshold voltage) 조절을 위한 이온 주입을 실시한다.FIG. 1 is a manufacturing process diagram of a conventional LDD transistor. First, as shown in FIG. 1A, a field oxide film 11 is grown on a p-type substrate 10 using a local oxide film (LOCOS: LoCal Oxidation of Silicon) process. After the gate oxide layer 12 is grown, ion implantation is performed to adjust the threshold voltage (V th ).
그 다음에 제 1b 도와 같이 상기 게이트 산화막(12)위에 폴리실리콘을 도포한 다음 식각하여 게이트(13)를 형성하고, 상기 p형 기판(10)과 상기 게이트(13)에 소스 및 드레인영역을 위한 n-를 주입하여 n-불순물영역(14)을 형성한다.Then, as shown in FIG. 1B, polysilicon is coated on the gate oxide layer 12 and then etched to form a gate 13, and the source and drain regions of the p-type substrate 10 and the gate 13 are formed. n − is implanted to form n − impurity region 14.
그후에 제 1c 도에 도시한 바와같이 상기 p형 기판(10)과 상기 게이트(13)상에 산화막을 도포하여 에치백(etch back)한후 게이트(13)의 양측에 측벽산화막(15)을 형성하고, n+을 주입하여 n+불순물영역(16)을 형성함으로써 종래의 LDD구조를 갖는 트랜지스터가 제조된다.Thereafter, as shown in FIG. 1C, an oxide film is applied and etched back on the p-type substrate 10 and the gate 13, and sidewall oxide films 15 are formed on both sides of the gate 13. , implanting n + to form the n + impurity region 16 is made by a transistor having a conventional LDD structure.
그러나 상기와 같이 제조되는 종래의 LDD 구조를 갖는 트랜지스터는 N-의 농도와 측벽산화막(15)의 길이를 조절하는 것만으로는 핫 캐리어 효과를 개선하는데 한계가 있으며, n-의 농도를 높이면 전계가 증가하게 되고 n-의 농도를 낮추면 저항의 증가로 전류가 감소하게 되는 문제점이 있었다.However, the transistor having the conventional LDD structure manufactured as described above has a limitation in improving the hot carrier effect only by adjusting the concentration of N − and the length of the sidewall oxide film 15, and increasing the concentration of n − may result in an electric field. Increasing the concentration of n − decreases the current due to the increase in resistance.
본 고안은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로서, 게이트의 양측에 2중으로 두개의 측벽을 형성하여 게이트로 동작하도록 함으로써 핫 캐리어 효과와 전류 드라이빙 및 게이트 중첩 캐퍼시턴스(gate overlap capacitance)을 개선하는 LDD트랜지스터의 구조와 제조방법을 제공하는데 목적이 있다.The present invention has been made to solve the above problems, by forming two sidewalls on both sides of the gate to operate as a gate to reduce the hot carrier effect, current driving and gate overlap capacitance (gate overlap capacitance) An object of the present invention is to provide a structure and a manufacturing method of an improved LDD transistor.
상기와 같은 목적을 달성하기 위하여 게이트 양측에 2중으로 두개의 측벽을 형성하고 세번의 이온 주입을 해하여 n영역과 n-영역 및 n+영역을 형성하고 게이트 산화막을 두껍게 성장시킨 본 발명을 첨부한 도면에 의해 보다 상세히 설명하면 다음과 같다.In order to achieve the above object, two sidewalls are formed on both sides of the gate and two ion implantation are performed to form n region, n − region, and n + region, and the gate oxide layer is thickly grown. When described in more detail by the drawings as follows.
제 2f 도는 본 발명에 따른 LDD트랜지스터의 완성도로서 도시한 바와같이 p형기판(20)상의 소정 부위에 게이트 산화막(22)와 게이트폴리(23)가 차례로 적층되고, 게이트폴리(23) 및 기판상에 열산화막(26)이 형성되고, 상기 게이트 폴리(23)의 양측에 폴리실리콘 측벽(28)과 측벽산화막(30)이 형성되고, 상기 측벽(28)(30) 하부의 게이트폴리(23) 양측 p형 기판(20)에 게이트폴리(23)의 인접부에서 차례로 중농도, 저농도, 고농도 불순물영역(27, 29, 31)이 형성되고, 소자간의 분리를 위해 필드산화막(21)이 형성된 구조로 되어 있다.2F shows a gate oxide film 22 and a gate poly 23 are sequentially stacked on a predetermined portion on the p-type substrate 20 as shown in the completeness of the LDD transistor according to the present invention. A thermal oxide film 26 is formed on the gate poly 23, polysilicon sidewalls 28 and sidewall oxide films 30 are formed on both sides of the gate poly 23, and the gate poly 23 is disposed below the side walls 28 and 30. Medium, low, and high concentration impurity regions 27, 29, and 31 are sequentially formed on both sides of the p-type substrate 20 adjacent to the gate poly 23, and the field oxide film 21 is formed to separate the elements. It is.
상기와 같은 구조를 갖는 본 발명에 따른 LDD트랜지스터의 제조공정을 살펴보자. 제 2a~f 도는 본발명에 따른 LDD트랜지스터의 제조공정도로서, 제 2a 도에 도시한 바와같이 p형 기판(20)상에 활성영역과 필드영역을 정의하여 필드영역에 국부산화 공정으로 필드산화막(21)을 성장시키고, 활성영역에 게이트 산화막(22)을 성장시킨 다음 문턱전압(Vth) 조절을 위한 이온주입을 실시한다.Let's look at the manufacturing process of the LDD transistor according to the present invention having the structure as described above. 2A to 2F are manufacturing process diagrams of the LDD transistor according to the present invention, and as shown in FIG. ), The gate oxide layer 22 is grown in the active region, and ion implantation is performed to adjust the threshold voltage (V th ).
그후 제 2b 도에 도시한 바와같이 폴리실리콘을 도포하여 식각하고, 게이트 폴리(23)를 형성한 후에 산화막을 도포하고 에치백(etch back)함으로서 상기 게이트 폴리(23)의 양측에 측벽산화막(24)을 형성한다.Thereafter, as shown in FIG. 2B, polysilicon is applied and etched, and after forming the gate poly 23, an oxide film is applied and etched back, so that sidewall oxide films 24 are formed on both sides of the gate poly 23. FIG. ).
다음에 제 2c 도와 같이 질화막(25)을 도포하고 에치백하여 필드산화막(21)과 측벽산화막(24) 사이의 활성영역을 질화막(25)으로 덮는다.Next, the nitride film 25 is coated and etched back as shown in FIG. 2C to cover the active region between the field oxide film 21 and the sidewall oxide film 24 with the nitride film 25.
제 2d 도에 도시한 바와같이 측벽산화막(24)을 제거하고, 상기 게이트폴리(23)에 게이트 산화막(22)보다 더 두껍게 열산화막(26)을 성장시킨후에 게이트폴리(23)와 질화막(25) 사이의 기판(20)에 n형 불순물을 1018~1019atoms/cm2의 농도로 주입하여 중농도의 n불순물영역(27)을 형성한다.As shown in FIG. 2D, the sidewall oxide film 24 is removed, and the thermal oxide film 26 is grown on the gate poly 23 thicker than the gate oxide film 22, and then the gate poly 23 and the nitride film 25 are formed. The n-type impurity is implanted into the substrate 20 between the layers at a concentration of 10 18 to 10 19 atoms / cm 2 to form an n-impurity region 27 having a medium concentration.
그후 제 2e 도와 같이 질화막(25)을 제거하고, 폴리실리콘을 도포한 뒤 이방성 식각하여 게이트폴리(23) 측벽에 폴리실리콘 측벽(28)을 형성한 다음 n형 불순물을 1016~1017의 농도로 주입하여 상기 중농도 n불순물영역(27)옆에 저농도 n-불순물영역(29)을 형성한다.Thereafter removing the first 2e help as the nitride film 25 and the poly to form a polysilicon side wall 28 to the gate poly 23, the side walls by applying a silicone after the anisotropic etching and then an n-type impurity 10 16 ~ 10 17 The concentration of To form a low concentration n − impurity region 29 next to the medium concentration impurity region 27.
제 2f 도에 도시한 바와같이 산화막을 도포하고 이방성 식각하여 상기 폴리실리콘 측벽(28)의 옆으로 측벽산화막(30)을 형성하고 n형 불순물을 1020~1021의 농도로 주입하여 고농도 n+불순물영역(31)을 형성함으로서 본 발명의 LDD트랜지스터가 제조된다.As shown in FIG. 2F, an oxide film is coated and anisotropically etched to form a sidewall oxide film 30 next to the polysilicon sidewall 28, and n-type impurities are implanted at a concentration of 10 20 to 10 21 to give a high concentration n +. The LDD transistor of the present invention is manufactured by forming the impurity region 31.
상기와 같이 제조되는 본 발명의 LDD트랜지스터에서 게이트폴리(23)가 폴리실리콘측벽(28)은 열산화막(26)에 의해 직류적으로는 격리되었지만 교류적으로는 격리가 되어 있지 않으므로 폴리실리콘 측벽(28)은 게이트로 동작하게 되며, 결과적으로 게이트가 중첩된 LDD의 효과를 나타내게 된다.In the LDD transistor of the present invention manufactured as described above, the polysilicon sidewall 28 of the polysilicon sidewall 28 is isolated by DC thermal insulation layer 26 but is not isolated by alternating current. 28) acts as a gate, resulting in the LDD overlapping gates.
또 중농도 n불순물영역(27)은 저항을 줄이는 역할을 하며 저농도 n-불순물영역보다 더 높은 농도이므로 게이트(23)와 중첩되는 부분이 상대적으로 적더라도 기판전류를 증가시키지 않는다.In addition, since the medium concentration impurity region 27 serves to reduce resistance and is higher than the low concentration n − impurity region, even if the portion overlapping with the gate 23 is relatively small, the substrate current is not increased.
한편 저농도 N-불순물영역(29)은 소오스 및 드레인의 전계를 줄이는데 폴리실리콘 측벽(28)의 밑에 존재하므로 저항이 크게 문제되지 않는다.On the other hand, since the low concentration N − impurity region 29 exists under the polysilicon sidewall 28 to reduce the electric fields of the source and drain, resistance does not matter significantly.
따라서 상기한 바와같은 본 발명은 다음과 같은 효과가 있다.Therefore, the present invention as described above has the following effects.
첫째, 중농도 n불순물영역과 저농도 n-불순물영역의 조합에 의해 전계를 감소시키고 게이트가 소오스 및 드레인과 충분히 중첩되며 게이트의 밑에서 전계의 최고치(peat)가 존재함에 따라 핫 캐리어 효과를 개선한다. 둘째, 고농도의 n+액티브 영역과 게이트의 중첩에 의해 전류 드라이빙이 개선된다. 셋째, 두꺼운 열산화막에 의해 게이트 중첩 캐퍼시턴스를 감소시키는 효과가 있다.First, the electric field is reduced by the combination of the medium concentration n impurity region and the low concentration n − impurity region, and the gate is sufficiently overlapped with the source and drain, and the hot carrier effect is improved as there is a peak of the electric field under the gate. Second, the current driving is improved by overlapping the gate with a high concentration of n + active region. Third, there is an effect of reducing the gate overlap capacitance by the thick thermal oxide film.
Claims (4)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910024204A KR940010569B1 (en) | 1991-12-24 | 1991-12-24 | Ldd-transistor and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019910024204A KR940010569B1 (en) | 1991-12-24 | 1991-12-24 | Ldd-transistor and manufacturing method thereof |
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| Publication Number | Publication Date |
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| KR930015087A KR930015087A (en) | 1993-07-23 |
| KR940010569B1 true KR940010569B1 (en) | 1994-10-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910024204A KR940010569B1 (en) | 1991-12-24 | 1991-12-24 | Ldd-transistor and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR940010569B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100567047B1 (en) * | 1999-06-28 | 2006-04-04 | 주식회사 하이닉스반도체 | Menufacturing method for mos transistor |
| CN102456554A (en) * | 2011-11-11 | 2012-05-16 | 上海华力微电子有限公司 | Method for reducing GIDL (gate-induced drain leakage) effect of MOS IO (metal oxide semiconductor input-output) apparatus |
-
1991
- 1991-12-24 KR KR1019910024204A patent/KR940010569B1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100567047B1 (en) * | 1999-06-28 | 2006-04-04 | 주식회사 하이닉스반도체 | Menufacturing method for mos transistor |
| CN102456554A (en) * | 2011-11-11 | 2012-05-16 | 上海华力微电子有限公司 | Method for reducing GIDL (gate-induced drain leakage) effect of MOS IO (metal oxide semiconductor input-output) apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| KR930015087A (en) | 1993-07-23 |
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