KR940009852A - Bank-level high-speed access processing unit in the administrative computer main computer (TICOM) - Google Patents

Bank-level high-speed access processing unit in the administrative computer main computer (TICOM) Download PDF

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Publication number
KR940009852A
KR940009852A KR1019920019194A KR920019194A KR940009852A KR 940009852 A KR940009852 A KR 940009852A KR 1019920019194 A KR1019920019194 A KR 1019920019194A KR 920019194 A KR920019194 A KR 920019194A KR 940009852 A KR940009852 A KR 940009852A
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KR
South Korea
Prior art keywords
bank
buffer
output
ticom
access processing
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Application number
KR1019920019194A
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Korean (ko)
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KR100243032B1 (en
Inventor
김용
Original Assignee
이헌조
주식회사 금성사
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Priority to KR1019920019194A priority Critical patent/KR100243032B1/en
Publication of KR940009852A publication Critical patent/KR940009852A/en
Application granted granted Critical
Publication of KR100243032B1 publication Critical patent/KR100243032B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Dram (AREA)

Abstract

본 발명은 행정 전신망 주 전산기(TICOM)에서 주기억 장치의 액세스 속도를 고속으로 처리하기 위한 뱅크 레벨 고속 액세스 처리장치에 관한 것이다. 이를 위하여 본 발명은 기존의 회로 구성에 입, 출력 뱅크 버퍼와 DMC를 부가 설치하여 뱅크 레벨로 인터리빙을 행하므로서 주기억 장치의 액세스 속도를 고속으로 처리할 수가 있는 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bank level fast access processing apparatus for processing the access speed of a main memory device at high speed in an administrative telegraph network main computer (TICOM). To this end, in the present invention, an input / output bank buffer and a DMC are installed in an existing circuit configuration to interleave at the bank level, thereby enabling the access speed of the main memory device to be processed at high speed.

Description

행정 전산망 주 전산기(TICOM)에서의 뱅크 레벨고속 액세스 처리장치Bank-level high-speed access processing unit in the administrative computer main computer (TICOM)

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 고속액세스 처리장치의 블록구성도.2 is a block diagram of a high speed access processing apparatus according to the present invention.

Claims (1)

메모리 응답 인터 페이스 회로(1)의 출력을 DMC(7)의 제어하에 입력 버퍼(3)와 출력 버퍼(6)에 데이타가 차 있는 경우 입력 큐(2)와 출력 큐(8)에서 홀딩하고 데이타가 차 있지 않은 경우 입력 버퍼(3)와 출력버퍼(6)로 데이타를 전송하여 각 뱅크(4),(5)에 가해주는 행정전산망 주전산기의 뱅크레벨 액세스 처리 장치에 있어서, 상기 입력 버퍼(3)와 출력 버퍼(6)에 각각 또하나의 입력 뱅크 버퍼(3B)와 출력 뱅크 버퍼(6B)를 부가하고, 이들의 데이타 상태를 감시하는 DMC(7)에 또 하나의 제2DMC(7B)를 부가하여 뱅크 레벨로 인터리빙을 행하도록 함을 특징으로 하는 행정전산망 중 전산기(TICOM)에서의 뱅크 레벨 고속 액세스 처리장치.When the output of the memory response interface circuit 1 is filled in the input buffer 3 and the output buffer 6 under the control of the DMC 7, the data is held in the input queue 2 and the output queue 8 and the data is held. In the bank level access processing apparatus of the administrative computer main computer which transfers data to the input buffer 3 and the output buffer 6 and applies them to each of the banks 4 and 5 when the data is not filled, the input buffer 3 ) Adds another input bank buffer 3B and output bank buffer 6B to the output buffer 6, and another second DMC 7B to the DMC 7 that monitors And interleaving at a bank level, wherein the bank level fast access processing apparatus in a computer (TICOM) of the administrative computer network. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920019194A 1992-10-19 1992-10-19 Bank-level high speed access processing apparatus in ticom KR100243032B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920019194A KR100243032B1 (en) 1992-10-19 1992-10-19 Bank-level high speed access processing apparatus in ticom

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920019194A KR100243032B1 (en) 1992-10-19 1992-10-19 Bank-level high speed access processing apparatus in ticom

Publications (2)

Publication Number Publication Date
KR940009852A true KR940009852A (en) 1994-05-24
KR100243032B1 KR100243032B1 (en) 2000-02-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920019194A KR100243032B1 (en) 1992-10-19 1992-10-19 Bank-level high speed access processing apparatus in ticom

Country Status (1)

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KR (1) KR100243032B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100712505B1 (en) * 2005-02-12 2007-05-02 삼성전자주식회사 A Memory address generating circuit and a controller using the circuit

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KR100243032B1 (en) 2000-02-01

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