KR940015863A

KR940015863A - Decoder method and apparatus therefor for high speed input / output device

Info

Publication number: KR940015863A
Application number: KR1019920026837A
Authority: KR
Inventors: 윤찬식
Original assignee: 백중영; 금성통신 주식회사
Priority date: 1992-12-30
Filing date: 1992-12-30
Publication date: 1994-07-21

Abstract

여러종류의 I/O디바이스가 다수개 접속되어 있는 경우에도 입출력 처리시간을 최소로 하여 성능을 향상시키기 위한 고속 I/O디바이스들을 위한 방법 및 그 장치를 제공 여러개의 I/O디바이스들로 구성된 시스템에서 I/O디바이스들의 종류가 같거나 다르거나에 관계없이 I/O디바이스에 내장된 데이타 레지스터들을 하나의 블럭에 연속적으로 재배치함으로써, I/O디바이스들에 대한 입력/출력 요구가 발생한 시점부터 모든 I/O디바이스들의 입력/출력 작업에 걸리는 시간을 단축함으로써, 고성능의 CPU로 교체하거나 CPU의 속도를 증가시키지 않고도 많은 수의I/O디바이스를 수용할 수 있고I/O디바이스들의 입력/출력 처리 소프트웨어가 간략하게 되며 고속의 CPU를 사용함에 따라 클럭의 주파수가 높아져 발생하는 EMI노이즈를 피할수 있어 시스템의 가격을 낮출 수 있는 효과가 있다.Provides method and apparatus for high speed I / O devices to improve performance by minimizing input / output processing time even when multiple types of I / O devices are connected. System composed of multiple I / O devices By sequentially relocating the data registers embedded in an I / O device into one block, regardless of whether the I / O devices are of the same type or different types, all of the input / output requests to the I / O devices occur from the point in time. By reducing the time required for I / O devices to perform input / output operations, a large number of I / O devices can be accommodated without changing to a high performance CPU or increasing the speed of the CPU, and processing the input / output of I / O devices. The software is simplified, and the use of a high-speed CPU reduces the price of the system by avoiding EMI noise caused by the clock frequency being higher. That there is an effect.

Description

Decoder method and apparatus therefor for high speed input / output device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명에 따른 디코더의 블럭 구성도, 제6도는 본 발명에 따른 롬의 어드레스 변환 테이블 구성도, 제7도는 본 발명에 따른 디코더의 동작 순서도.4 is a block diagram of a decoder according to the present invention, FIG. 6 is a diagram of an address translation table of a ROM according to the present invention, and FIG. 7 is a flowchart of an operation of the decoder according to the present invention.

Claims

A ROM 420 to which an address signal A1, A2, ..., An + 4 of a CPU (not shown) is applied to an input terminal, and an I / O block selection signal G is applied to a chip enable terminal; Partial data (Cn + 1, Cn + 2, Cn + 3) of the output data (C1, C2 ..., Cn + 3) 3 of the ROM 420 is applied to an input terminal and the I / O block is selected at an enable terminal. A decoder 410 to which the signal G is applied and some data C1, C2, ..., Cn of the output data C1, C2, ..., Cn + 3 of the ROM 420 are applied to the address input terminal. A high speed input / output characterized in that it comprises an I / O device (401, 402, ..., 408) and a wait signal generator (430) for receiving the I / O block selection signal (G) and generating a wait signal (wait). Decoder device for the device.

Receiving and storing an address signal from a CPU; A selection signal generating step of selecting an input / output block when outputting address data in the storing step; And detecting an overload state in the input / output block to generate a standby signal to the CPU.

※ Note: The disclosure is based on the initial application.