KR970056364A

KR970056364A - Transmission Utopia Device

Info

Publication number: KR970056364A
Application number: KR1019950052684A
Authority: KR
Inventors: 서정욱
Original assignee: 양승택; 한국전자통신연구원; 이준; 한국전기통신공사
Priority date: 1995-12-20
Filing date: 1995-12-20
Publication date: 1997-07-31
Also published as: KR0175446B1

Abstract

본 발명은 초고속 정보 통신망에서 전송 선로로 ATM셀을 송출하는 데 있어서, ATM층으로부터 물리층으로 공급되는 송신 클럭과 물리층 클럭이 비동기이기 때문에 생길 수 있는 클럭 충돌을 방지하기 위한 송신 UTOPLA 장치에 관한 것으로, 하나의 송신용 ATM셀을 순차적으로 저장하기 위한 n개의 FIFO 수단; 상기 FIFO 수단과 FIFO 제어수단을 선택하기 위한 FIFO 선택수단; 및 상기 각 FIFO 수단의 상태를 나타내기 위한 쓰기용 FIFO 상태 표시수단으로 구성되는 것을 특징으로 한다.The present invention relates to a transmission UTOPLA apparatus for preventing a clock collision that may occur due to asynchronous transmission clock and physical layer clock supplied from the ATM layer to the physical layer in transmitting an ATM cell in a transmission line in a high-speed information communication network, N FIFO means for sequentially storing one transmitting ATM cell; FIFO selecting means for selecting the FIFO means and FIFO control means; And write FIFO status display means for indicating the status of each FIFO means.

Description

Transmission Utopia Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 다양한 비동기 클럭을 처리하기 위한 송신 UTOPIA 장치의 기능 블럭도.1 is a functional block diagram of a transmitting UTOPIA apparatus for processing various asynchronous clocks in accordance with the present invention.

제2도는 본 발명에 따른 제1FIFO 제어회로의 기능 블록도.2 is a functional block diagram of a first FIFO control circuit in accordance with the present invention.

제3도는 본 발명에 따른 제1FIFO 제어회로의 회로도.3 is a circuit diagram of a first FIFO control circuit according to the present invention;

제4도는 본 발명에 따른 쓰기용 FIFO 상태 표시회로의 회로도.4 is a circuit diagram of a write FIFO status display circuit according to the present invention.

Claims

N FIFO means for sequentially storing one transmitting ATM cell; N FIFO control means for controlling reading and writing data of each FIFO means; FIFO selecting means for selecting the FIFO means and FIFO control means; And write FIFO status display means for indicating the status of each FIFO means.

2. The apparatus of claim 1, wherein the FIFO control means comprises: write FIFO address generating means for generating a write FIFO address; Reading FIFO address generating means for generating a reading FIFO address; Reading counter enable generating means for generating a counter enable signal of said reading FIFO address generating means; And TXCKP impulse prevention means for preventing a malfunction due to a clock collision between an output of the read counter enable generation means and a clock used in the read FIFO address generation means.

※ Note: The disclosure is based on the initial application.