KR960043647A - Cell transport interface logic between each layer - Google Patents

Cell transport interface logic between each layer Download PDF

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Publication number
KR960043647A
KR960043647A KR1019950013209A KR19950013209A KR960043647A KR 960043647 A KR960043647 A KR 960043647A KR 1019950013209 A KR1019950013209 A KR 1019950013209A KR 19950013209 A KR19950013209 A KR 19950013209A KR 960043647 A KR960043647 A KR 960043647A
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KR
South Korea
Prior art keywords
state
transmission
layer
logic
interface logic
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KR1019950013209A
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Korean (ko)
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KR100235654B1 (en
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전윤호
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정장호
Lg 정보통신 주식회사
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Publication of KR960043647A publication Critical patent/KR960043647A/en
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Publication of KR100235654B1 publication Critical patent/KR100235654B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/321—Interlayer communication protocols or service data unit [SDU] definitions; Interfaces between layers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5619—Network Node Interface, e.g. tandem connections, transit switching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
    • H04L2012/5653—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM adaptation layer [AAL]

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Security & Cryptography (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)

Abstract

본 발명은 에이티엠 계층 처리부와 에이티엠 적응계층처리부와의 데이타 전송수단과 관련된 것으로서, 종래에는 이러한 시스템들 간의 데이타 전송 시에 전송방식이 다른 경우 이를 적절히 적응시켜 줄 수 있도록 한 마땅한 수단이 구비되어져 있지 않아 문제가 되어왔다.The present invention relates to the data transmission means of the ATM layer processing unit and the ATM adaptation layer processing unit. In the related art, when the transmission method is different in the data transmission between these systems, a proper means for adapting it is provided. It has not been a problem.

본 발명은 이러한 종래 기술의 문제점을 개선할 수 있도록 상기 에이티엠 계층처리부(2)와 에이티엠 적층계층 처리부(3) 사이에는 이들 사이에 연결되어져서 이들 사이의 데이타 전송방식이 상호 다를 경우 이를 조절하여 주는 인터페이스로직(1)이 구비되어져 있는 구성을 특징으로 하는 에이티엠 각 계층 사이의 셀 전송 인터페이스 로직을 제공하는데 있다.The present invention is connected between the ATM layer processing unit 2 and the ATM layer processing unit 3 so as to improve the problems of the prior art, and if the data transmission method between them is different, it is controlled It is to provide the cell transfer interface logic between each layer characterized by the configuration that the interface logic (1) is provided.

Description

에이티엠 각 계층 사이의 셀 전송 인터페이스 로직Cell transport interface logic between each layer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명이 구비된 비동기 통신모드(ATM;Asynchronous Transfer Mode)시스템에서의 시스템 회로블럭도, 제2도는 제1도예의 인터페이스 로직에서 수신 스테이트 머신(Machine) 로직을 나타내는 일예도, 제4도는 제1도예의 인터페이스 로직에서 송신 스테이트 머신 로직의 일예도.FIG. 1 is a system circuit block diagram of an Asynchronous Transfer Mode (ATM) system equipped with the present invention. FIG. 2 is an example diagram showing a reception state machine logic in the interface logic of FIG. Or an example of transmit state machine logic in the interface logic of FIG.

Claims (7)

에이티엠 계층 처리부(2)와 에이티엠 적응 계층 처리부(2) 사이의 데이터 전송 수단에 있어서, 상기 에이티엠 계층 처리부(2)와 에이티엠 적응계층처리부(3) 사이에는 이들 사이에 연결되어져서 이들 사이의 데이타 전송방식이 상호 다른 경우 이를 조절하여 주는 인터페이스 로직(1)이 구비되어져 있는 구성을 특징으로 하는 에이티 엠 각 계층 사이에 셀 전송 인터페이스 로직.In the data transmission means between the ATM layer processing unit 2 and the ATM adaptation layer processing unit 2, between the ATM layer processing unit 2 and the ATM adaptation layer processing unit 3 are connected therebetween. Cell transfer interface logic between each layer characterized by the configuration that is provided with interface logic (1) for adjusting the data transfer method between the different. 제1항에 있어서, 상기 인터 페이스 로직(1)은 수, 송신 스테이트 머신 로직(11,13)과; 리드, 라이트 신호 생성회로(12,14)와; 플래그 생성회로(15)를 포함한 구성을 특징으로 하는 에이티 엠 각 계층 사이에 셀 전송 인터페이스 로직.2. The apparatus of claim 1, wherein the interface logic (1) comprises: a number, transmission state machine logic (11, 13); Lead and write signal generation circuits 12 and 14; Cell transmission interface logic between each layer characterized by a configuration including a flag generation circuit (15). 제2항에 있어서, 상기 수신 스테이트 머신 로직(11)은 수신대기(11a)와 수신 활성화(11b)상태와의 사이에서 수신대기(11a)상태에서상태이면 수신대기(11a)상태로 가고, atm-avl*＆ cel-avl-flag상태이면 수신활성화(11a)상태로며, 수신 활성화(11b)상태에서이면 다시 수신활성화(11b)상태로 가고, 수신활성화(11b)상태에서이면 수신대기 (11a) 상태로 가는 로직으로 이뤄져 있는 것을 특징으로 하는 에이티 엠 각 계층 사이에 셀 전송 인터페이스 로직.3. The reception state machine logic (11) according to claim 2, wherein the reception state machine logic (11) is in the reception standby (11a) state between the reception standby (11a) and the reception activation (11b) state. If the state is in the reception standby (11a) state, if the atm-avl * & cel-avl-flag state is in the reception activation (11a) state, in the reception activation (11b) state If so, it goes back to the reception activation (11b) state, Cell transfer interface logic between each layer, characterized in that it consists of logic going to the receive standby (11a) state. 제2항에 있어서, 상기 리드신호 생성 회로(12)는 시스템에서의 aal-clk 신호와 rx-cell-state==rx-active 신호를 논리곱하여 atm-rd*를 생성하는 게이트(12a)로 이뤄져 있는 것을 특징으로 하는 에이티 엠 각 계층 사이에 셀 전송 인터페이스 로직.3. The read signal generation circuit (12) of claim 2 comprises a gate (12a) for generating atm-rd * by ANDing the aal-clk signal and the rx-cell-state == rx-active signal in the system. Cell transmission interface logic between each layer. 제2항에 있어서, 상기 송신 스테이트 머신 로직(13)은 송신대기(13a)와 송신 활성화(13b) 상태와의 사이에서 송신대기(13a) 시에 논리식이이면 다시 송신대기(13a)상태로 가고, aal-avl*이면 송신활성화(13b)상태로 가며, 송신활성화(13b)상태에서송신 대기 상태(13a)로 가고, 송신활성화(13b) 상태에서이면 다신 송신 활성화(13b)상태로 가는 로직으로 이뤄져 있는 것을 특징으로 하는 에이티엠 각 계층 사이에 셀 전송 인테페이스 로직.3. The transmission state machine logic (13) according to claim 2, wherein the transmission state machine logic (13) is logically expressed at the time of transmission wait (13a) between the transmission wait (13a) and the transmission activation (13b) states. If it is, it goes to transmission standby (13a) state again, and if it is aal-avl *, it goes to transmission activation (13b) state, Go to the transmission standby state 13a, and in the transmission activation 13b state Cell transmission interface logic between each layer, characterized in that it consists of logic to go back to the transmit activation (13b) state. 제2항에 있어서, 상기 라이트 신호 생성회로(14)는 시스템에서의 aal-clk 신호를 인버팅하여 낸드게이트(14b)의 한 입력으로 제공하는 인버터(14b)와, 이 인버터(14a)출력과 tx-cell-state==tx-active 신호를 두 입력으로 하여 atm-wr* 신호를 생성하는 낸드게이트(14b)로 이뤄져 있는 것을 특징으로 하는 에이티 엠 각 계층 사이에 셀 전송 인터페이스 로직.3. The write signal generation circuit (14) according to claim 2, wherein the write signal generation circuit (14) includes an inverter (14b) for inverting the aal-clk signal in the system and providing it to one input of the NAND gate (14b), and the output of the inverter (14a). Cell transfer interface logic between each layer of the ATM M, characterized in that the NAND gate (14b) for generating the atm-wr * signal with two inputs tx-cell-state == tx-active signal. 제2항에 있어서, 상기 플래그 생성회로(15)는 시스템에서 에이티엠 계층 데이타 전송펄스가 가해지는 53바이트 카운터(15a)와, 이 53 바이트 카운터(15a)의 출력에서 이어져서 cel-avl-flag 신호를 생성하는 1 셀 카운터(15a)와로 이뤄져 있는 것을 특징으로 하는 에이티 엠 각 계층 사이에 셀 전송 인터페이스 로직.3. The flag generating circuit (15) according to claim 2, wherein the flag generating circuit (15) is connected to the 53-byte counter (15a) to which the AT layer data transmission pulse is applied in the system, and is connected to the output of the 53-byte counter (15a) to cel-avl-flag. Cell transmission interface logic between each layer, characterized in that it consists of one cell counter (15a) for generating a signal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950013209A 1995-05-25 1995-05-25 Cell transfer interface logic between atm layers KR100235654B1 (en)

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KR1019950013209A KR100235654B1 (en) 1995-05-25 1995-05-25 Cell transfer interface logic between atm layers

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KR960043647A true KR960043647A (en) 1996-12-23
KR100235654B1 KR100235654B1 (en) 1999-12-15

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