PT84811A - Interface circuitry for communicating by means of messages - Google Patents

Interface circuitry for communicating by means of messages

Info

Publication number
PT84811A
PT84811A PT8481187A PT8481187A PT84811A PT 84811 A PT84811 A PT 84811A PT 8481187 A PT8481187 A PT 8481187A PT 8481187 A PT8481187 A PT 8481187A PT 84811 A PT84811 A PT 84811A
Authority
PT
Portugal
Prior art keywords
bit
message
messages
communicating
available
Prior art date
Application number
PT8481187A
Other languages
Portuguese (pt)
Other versions
PT84811B (en
Inventor
Guido Remi Marcel Gallopyn
Original Assignee
Gte Atea Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from BE2/60976A external-priority patent/BE904702A/en
Application filed by Gte Atea Nv filed Critical Gte Atea Nv
Publication of PT84811A publication Critical patent/PT84811A/en
Publication of PT84811B publication Critical patent/PT84811B/en

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  • Multi Processors (AREA)

Abstract

Two buffer circuits of FIFO type, connected together in anti-parallel mode, form a bi-directional message buffer. Communications between the processors is via data busses and input/output circuits. The unit contains two status registers and two command registers. Each status register operates on 8-bit words, the first bit of which indicates whether a message from its associated processor is available. Each command register operates on an 8-bit word. the second bit of which indicates that a meassage has been received. When the message received bit is set it automatically resets the message available bit in the status register.
PT8481187A 1986-04-30 1987-04-30 Interface circuitry for communicating by means of messages PT84811B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
BE2/60976A BE904702A (en) 1986-04-30 1986-04-30 Interface unit for communication between two data processors - provides rapid switching by use of interrupt-driven buffers

Publications (2)

Publication Number Publication Date
PT84811A true PT84811A (en) 1987-05-01
PT84811B PT84811B (en) 1989-06-19

Family

ID=3865807

Family Applications (1)

Application Number Title Priority Date Filing Date
PT8481187A PT84811B (en) 1986-04-30 1987-04-30 Interface circuitry for communicating by means of messages

Country Status (4)

Country Link
CN (1) CN87103247A (en)
IN (1) IN164427B (en)
PT (1) PT84811B (en)
ZA (1) ZA873067B (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1293739C (en) * 2002-06-15 2007-01-03 华为技术有限公司 High speed link control protocol transmission processing/module and data processing/method
CN100401731C (en) * 2002-06-15 2008-07-09 华为技术有限公司 High speed data link control protocol receiving processing module and data processing/method
CN100359457C (en) * 2004-12-16 2008-01-02 华为技术有限公司 Method for realizing normal working of communication interface based on sending interruption
CN100419723C (en) * 2005-12-30 2008-09-17 北京中星微电子有限公司 Multi-interruption cache device and method
TWI699656B (en) * 2018-12-27 2020-07-21 新唐科技股份有限公司 Switchable i2s interface

Also Published As

Publication number Publication date
IN164427B (en) 1989-03-18
ZA873067B (en) 1987-12-30
CN87103247A (en) 1987-12-30
PT84811B (en) 1989-06-19

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