CN100419723C - Multi-interruption cache device and method - Google Patents
Multi-interruption cache device and method Download PDFInfo
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- CN100419723C CN100419723C CNB2005101374436A CN200510137443A CN100419723C CN 100419723 C CN100419723 C CN 100419723C CN B2005101374436 A CNB2005101374436 A CN B2005101374436A CN 200510137443 A CN200510137443 A CN 200510137443A CN 100419723 C CN100419723 C CN 100419723C
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- 230000003139 buffering effect Effects 0.000 claims abstract description 4
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- 230000005540 biological transmission Effects 0.000 claims description 10
- 230000001960 triggered effect Effects 0.000 abstract 1
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Abstract
The present invention discloses a multiple interruption buffering device and a method. The device comprises a memory, a memory controlling unit and an interruption occurring unit, and necessarily, an interruption generating unit register can be allocated to an interruption generating unit, so the interruption generating unit is controlled to generate interruption. The method comprises following steps that the present invention is provided with a plurality of interruption generating condition register; the interruption occurring unit enables the register to send data; when a storing unit reaches a certain specific position, the interrupt occurring unit is triggered; the interruption occurring unit generates interruption to corresponding equipment; the corresponding equipment judges whether the interruption is processed or not according to the priority of the interruption; the interruption is processed, and the data is sent or received. The present invention can fully use the space of the memory, reduces the working interference for the equipment and simultaneously avoids the clogging and the idle placement of the memory and the waiting of the equipment.
Description
Technical field
The present invention relates to data transmission technology, relate in particular to a kind of improved buffer storage and method that is used for data transmission.
Background technology
Have in the system design of data transmission, in system design, selected different equipment, because different equipment has different data processing data, caused the inharmonious of data transmission between each equipment, in order to address this problem, all selected for use the mode of buffering to coordinate this problem at present a lot of system designs.
In system design adopted interruption, DMA and passage control technology make can concurrent working between each equipment in the system.But the unmatched problem of the processing speed of equipment is an outwardness.This has limited the quantity that connects between the equipment.
The unmatched problem of equipment and device rate can adopt the method that buffer zone is set to solve.After being provided with buffer zone, data output apparatus (hereinafter to be referred as transmit leg) process can at first output to buffer zone to data, continue to carry out the work of back then, data receiver (hereinafter to be referred as the take over party) then can take out data from buffer zone and operate.Do not influence mutually between two equipment.
Adopt the Buffer of ping-pong structure in the system that has, structural drawing as shown in Figure 1.By two identical one-port memories, the total volume of supposing ping-pong buffer is M (unit is a storage unit) in this structure, these two storeies that physically separate, and the capacity of each is respectively M/2.Buffer1 and Buffer2 are two same block storages among the figure, and two port bindings of two storeies constitute the input interface and the output interface of the Buffer buffer storage of ping-pong structure jointly to together.
Distinct device transmits data by table tennis Buffer structure, and when Buffer had a semispace for sky, it was disconnected in the air to send Buffer to transmit leg, and transmit leg fills up this half Buffer space with new data; When Buffer has a semispace when full, sending Buffer to the take over party completely interrupts, and reciever is taken the new data of this half Buffer away.
Owing in the existing method, have only a half-full interruption of storer, and this interruption must be in a position in the numerous Interrupt Process of take over party, the problem below having produced:
If this interrupt priority level is very high, when reading the storer interruption so, the take over party must stop ongoing work, does not respond other interruptions of take over party, and goes reading of data.At this moment number is write for transmit leg in the storer space that also has half, when possible take over party took the data of half Buffer away, second half storer is also far short of what is expected just to be write completely, causes the waste of storage space, has influenced other work of take over party on the other hand again; Equally, for transmit leg, when write store interrupted, transmit leg must stop ongoing work, does not respond other interruptions of transmit leg, and goes to write data.Equally, at this moment storer also has the space of half to read for the take over party, has caused the waste of storage space, has also influenced other work of transmit leg simultaneously.
If this interrupt priority level is very low, when storer interrupted so, the take over party may handle more senior interruption and can't respond, and caused peek untimely, and storer is filled, and transmit leg enters wait; When perhaps interrupting owing to storer, transmit leg may be handled more senior interruption and can't respond, and causes storer to be got sky, and the take over party enters wait, has influenced the coordination each other of take over party and transmit leg.
Summary of the invention
In view of this, not high in order to solve the storer utilization factor, problems such as interruption that equipment is not interrupted by not emergency and good tension dashes in/peeks, the present invention proposes a kind of apparatus and method of using the multiple interrupt buffer memory.
A kind of buffer storage is characterized in that: comprising:
Storer is used for the part that the data of data transmission procedure are temporarily deposited;
Memory control unit is used for control store and outside operation, comprises that read-write operation is forbidden read-write operation or the like;
Interrupt generating unit, be used for producing interruption according to different interruption generation values.
Can produce one according to the different state of storer when further, this buffer storage produces a plurality of the interruption interrupts or different a plurality of interruptions; These interruptions can be same priority levels, come constantly to send application to equipment, also can be according to other interruption of state generation different priorities of storer; As shown in Figure 2, multiple interrupt interruption generating unit is made up of a plurality of condition register and corresponding a plurality of comparers, can form corresponding a plurality of interruptions, and these interruptions can be provided with flexibly by the memory control unit upper layer software (applications).
Further, interruption generating unit in this buffer storage can be divided into the take over party and interrupt generating unit, also can interrupt generating unit for interrupting transmit leg, also can have two to interrupt generating unit simultaneously, one interrupts generating unit for interrupting transmit leg, and one interrupts generating unit for the take over party.
Further, can be two with interrupting that generating unit fixedly install, one interrupts generating unit for the take over party, and one is transmit leg interruption generating unit.Be equipped with an interruption generating unit enable register but interrupt generating unit, can control these two interruption generating units according to these two interruption generating unit enable register and whether use to each.Even, when take over party's reading speed generally than comparatively fast, and under the general slow situation of transmit leg writing speed, can interrupt generating units with two and all forbid.Like this, dispose the multiple interrupt buffer storage that interrupts the generating unit enable register and can be used as a kind of general device, be applicable to various equipment.
Further, the described storer of this buffer storage can also can be the FIFO of a storage unit for the table tennis Buffer of polylith storage unit splicing.
A kind of data buffering method is characterized in that: may further comprise the steps:
A., interrupt condition is set produces register;
B is provided with and interrupts the generating unit enable register;
C sends data;
The capacity of D storage unit stores data arrives different interruption generation values, triggers to interrupt generating unit, and its corresponding equipment is given in the interruption of interrupting generating unit generation different priorities;
The E corresponding device is judged according to priority of interrupt whether handle this interruption;
The F handling interrupt sends or receives data.
Further, the priority that the interruption of these different interruption generation value correspondences can distribute different stage in this method; These different interruption generation values can be provided with flexibly by the memory control unit upper layer software (applications).
Further, two among the step B in this method interrupt that the generating unit enable register can all be set to need not.
By the present invention, can solve the situation of in the prior art memory resource being wasted, improved the storer utilization ratio; Provide sufficient time processing thing separately for sending and receive both sides simultaneously, do not caused to handle and stagnate, reduced influence both sides' work because of data transmission problems; Avoid the obstruction of storer and vacant, improved the efficient of data transmission.
Description of drawings
Fig. 1 prior art table tennis Buffer buffer storage synoptic diagram;
Generating unit structure and connection diagram are interrupted in Fig. 2 multiple interrupt.
Fig. 3 multiple interrupt buffer storage of the present invention synoptic diagram;
Fig. 4 the present invention has the buffer storage synoptic diagram that interrupts taking place enable register;
Embodiment
Key of the present invention is to have proposed interruption generating unit 200 can produce a plurality of interruptions.As shown in Figure 2, memory control unit upper layer software (applications) 203 can be provided with each condition register 2001, condition register 2002 and condition register 2003 by software, after memory control unit 202 reads the information of storer, compare by comparer 20011, comparer 20022 and comparer 20033 and condition register 2001, condition register 2002 and condition register 2003, meet that condition and just produce corresponding interruption.
As shown in Figure 3, with the storer on the ordinary meaning is example, suppose that in this buffer storage transmit leg interrupts generating unit 212 and take over party and interrupts generating unit 222 and can produce three interruptions, first is when four/for the moment of the capacity of storage data arrival storer 201, interrupt generating unit 212 by transmit leg and produce an interruption to transmit leg 211, this priority of interrupt is made as senior, simultaneously, the take over party is interrupted generating unit 222 and is produced an interruption to take over party 221, and this priority of interrupt is made as rudimentary; Second is when two/for the moment of the capacity of storing data arrival storer 201, interrupt generating unit 212 by transmit leg and produce an interruption to transmit leg 211, this priority of interrupt is made as regular grade, the take over party is interrupted interruption of generating unit 222 generations to take over party 221 simultaneously, and this priority of interrupt is made as regular grade; The 3rd be when the storage data arrive storer 201 capacity 3/4ths the time, interrupt generating unit 212 by transmit leg and produce an interruption to transmit leg 211, this priority of interrupt is made as rudimentary, the take over party is interrupted interruption of generating unit 222 generations to take over party 221 simultaneously, and this priority of interrupt is made as senior.
Arrive when data storage storer 201 capacity four/for the moment, storer 201 provides the read-write pointer to memory control unit 202, memory control unit 202 calculates storer 201 existing valid data and remaining space size according to the read-write pointer, offers transmit leg interrupt generating unit 212 and take over party's interrupt generating unit 222 respectively.Transmit leg interrupt generating unit 212 is interrupted generation value with remaining space size and each and is compared, if the remaining space size greater than 3/4ths this interrupt generation values, high level interrupt produces, the high level interrupt of transmit leg 211 has just produced; The take over party is interrupted generator 222 and valid data sizes and each are interrupted generation value is compared, if the valid data size greater than certain 1/4th this interrupt generation values, low level interrupts produces, take over party 221 low level interrupts has produced.After transmit leg 211 receives this high level interrupt, the priority of the incident of handling with oneself is compared, think that the priority ratio of this high level interrupt is higher, so just begin writing under the control that enables to storer 201 transmission data, because data are got sky in the storer 201, and the situation that causes take over party 221 to enter wait takes place to prevent; Take over party 221 the low level interrupts side of being received 221 receives simultaneously, take over party 221 compares with the priority of the incident of oneself handling, think that the priority level of this low level interrupts is lower, so do not respond this interruption, proceed the incident oneself handled, guaranteed the continuity of take over party's 221 processing transactions.When data storage to the capacity of storer 201 3/4ths the time, the low level interrupts of transmit leg 211 and take over party's 221 high level interrupt has produced, after transmit leg 211 receives this low level interrupts, the priority of the incident of handling with oneself is compared, think that the priority ratio of this low level interrupts is lower, do not respond this interruption, proceed the incident oneself handled, guaranteed the continuity of transmit leg 211 processing transactions; Simultaneously, take over party 221 the high level interrupt side of being received 221 receives, take over party 221 compares with the priority of the incident of oneself handling, think that the priority level of this high level interrupt is than higher, so just begin under the control of reading to enable, to read the data in the storer 201, prevent because after transmit leg 211 fills up storer 201, enter waiting status.Equally in data storage to two/for the moment of the capacity of storer 201, produced two regular interrupt of transmit leg 211 and take over party 221 equally, they are according to just carrying out suitable processing in the priority of processing events separately.
After the high level interrupt response finishes, it is same because the minimizing of data or increase can cause interruption again, and the thing that this interruption is being handled before might being lower than, so just stop to write/read operation of data, carry out current prior thing, so just guaranteed that transmit leg 211 or take over party 221 handle main thing vacateing more time.Rather than interrupted by the thing of data transmission.
As shown in Figure 4, distribute transmit leg interrupt generating unit enable register 213 for transmit leg interrupt generating unit 212, distribute take over party's interrupt generating unit enable register 223 for take over party's interrupt generating unit 222, so just can interrupt whether taking place in different occasion control.Before system's operation, interrupt the setting of generating unit enable register earlier, after the interruption generating unit receives the pointer of memory control unit 202, determine whether interrupting in interruption generating unit enable register according to oneself.All the other processes are with above-mentioned process.
The ping-pong structure of forming by Buffer A 101 and Buffer B 102 when storer 201, two Buffer of original state all are in dummy status, with full, interrupt generating unit 222 and send low priority interrupt to take over party 221 by the take over party with Buffer A 101 for transmit leg 211; Because Buffer B 102 is empty, transmit leg 211 continues to write Buffer B 102.When writing full Buffer B 102 1 semispaces, the take over party is interrupted generating unit 222 and is sent high-priority interrupt to take over party 221; Transmit leg 211 continues to write Buffer B 102, and take over party 221 begins to read Buffer A 101; When transmit leg 211 was write full BufferB 102, if take over party 221 has read sky Buffer A 101, transmit leg 211 can continue to write Buffer B 102, otherwise transmit leg 211 will enter waiting status.
The above, only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, so protection domain of the present invention is as the criterion with the protection domain of claims.
Claims (9)
1. buffer storage is characterized in that: comprising:
Storer is used for the part that the data of data transmission procedure are temporarily deposited;
Described storer is the table tennis Buffer of polylith storage unit splicing or the FIF0 of a storage unit;
Memory control unit is used for control store and interrupts generating unit, comprises the read-write pointer control to storer, the calculating of storer usage space;
Interrupt generating unit, form, be used for producing the interruption of different priorities according to different interruption generation values by a plurality of condition register and corresponding a plurality of comparers.
2. according to the described buffer storage of claim 1, it is characterized in that: described interruption generating unit, each interrupts generating unit, and one or more interruption can take place.
3. according to the described buffer storage of claim 2, it is characterized in that: a plurality of interruptions that described interruption generating unit takes place can be disposed the priority level of different stage.
4. according to the described buffer storage of claim 2, it is characterized in that: a plurality of interruptions that described interruption generating unit takes place can be provided with different generation conditions by the programming of memory control unit upper layer software (applications).
5. according to the described buffer storage of claim 1, it is characterized in that: described interruption generating unit interrupts generating unit for the take over party, or for interrupting transmit leg interruption generating unit, or there are two to interrupt generating unit simultaneously, one interrupts generating unit for interrupting transmit leg, and one interrupts generating unit for the take over party.
6. according to the described buffer storage of claim 1, it is characterized in that: described interruption generating unit is two, one interrupts generating unit for the take over party, one is transmit leg interruption generating unit, each interrupts generating unit and is equipped with an interruption generating unit enable register, can install use occasion according to this and specifically be provided with.
7. data buffering method is characterized in that: may further comprise the steps:
A. dispose each and interrupt producing condition register;
B is provided with and interrupts the generating unit enable register;
C sends data;
The capacity that the table tennis Buffer of D polylith storage unit splicing or the FIF0 of a storage unit store data arrives different interruption generation values, triggers and interrupts generating unit, and its corresponding equipment is given in the interruption of interrupting generating unit generation different priorities;
The E corresponding device is judged according to priority of interrupt whether handle this interruption;
The F handling interrupt sends or receives data.
8. according to the described method of claim 7, it is characterized in that: the interruption generating unit enable register among the step B can all be set to need not.
9. according to the described method of claim 7, it is characterized in that: the priority that the interruption of the different interruption generation value correspondence among the step D can distribute different stage, these interrupt the generation value and can be provided with by the memory control unit upper layer software (applications).
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2005101374436A CN100419723C (en) | 2005-12-30 | 2005-12-30 | Multi-interruption cache device and method |
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| CNB2005101374436A CN100419723C (en) | 2005-12-30 | 2005-12-30 | Multi-interruption cache device and method |
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| CN1804822A CN1804822A (en) | 2006-07-19 |
| CN100419723C true CN100419723C (en) | 2008-09-17 |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102855156B (en) * | 2011-06-30 | 2015-05-27 | 重庆重邮信科通信技术有限公司 | Interrupt controller and interrupt controlling method |
| CN103345873B (en) * | 2013-07-19 | 2015-08-19 | 南京财经大学 | A kind of demenstration method of chip microcomputer interruption priority level and device |
| KR20170032502A (en) * | 2015-09-14 | 2017-03-23 | 삼성전자주식회사 | Storage device and interrupt generation method thereof |
| CN108366372A (en) * | 2017-12-13 | 2018-08-03 | 国家电网公司 | The wireless telecommunication system and the means of communication of fault detector and hand-held maintenance tool |
| TWI676171B (en) | 2018-09-18 | 2019-11-01 | 華邦電子股份有限公司 | Memory apparatus and interrupt handling method thereof |
| CN111081295A (en) * | 2018-10-22 | 2020-04-28 | 华邦电子股份有限公司 | Memory device and interrupt processing method thereof |
| CN109947580A (en) * | 2019-03-27 | 2019-06-28 | 上海燧原智能科技有限公司 | Interruption processing method, device, equipment and storage medium |
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| CN87103247A (en) * | 1986-04-30 | 1987-12-30 | 阿特阿公司 | Interface circuitry for communicating by means of messages |
| JPH11202909A (en) * | 1998-01-13 | 1999-07-30 | Mitsubishi Electric Corp | Link unit for programmable controller |
| JP2001202255A (en) * | 2000-01-19 | 2001-07-27 | Hitachi Ltd | Nonmaskable interruption system |
| US20040001499A1 (en) * | 2002-06-26 | 2004-01-01 | Patella James Philip | Communication buffer scheme optimized for voip, QoS and data networking over a power line |
| CN1585373A (en) * | 2004-05-28 | 2005-02-23 | 中兴通讯股份有限公司 | Ping pong buffer device |
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2005
- 2005-12-30 CN CNB2005101374436A patent/CN100419723C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN87103247A (en) * | 1986-04-30 | 1987-12-30 | 阿特阿公司 | Interface circuitry for communicating by means of messages |
| JPH11202909A (en) * | 1998-01-13 | 1999-07-30 | Mitsubishi Electric Corp | Link unit for programmable controller |
| JP2001202255A (en) * | 2000-01-19 | 2001-07-27 | Hitachi Ltd | Nonmaskable interruption system |
| US20040001499A1 (en) * | 2002-06-26 | 2004-01-01 | Patella James Philip | Communication buffer scheme optimized for voip, QoS and data networking over a power line |
| CN1585373A (en) * | 2004-05-28 | 2005-02-23 | 中兴通讯股份有限公司 | Ping pong buffer device |
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