KR930018895A - Communication control device - Google Patents

Communication control device Download PDF

Info

Publication number
KR930018895A
KR930018895A KR1019930001901A KR930001901A KR930018895A KR 930018895 A KR930018895 A KR 930018895A KR 1019930001901 A KR1019930001901 A KR 1019930001901A KR 930001901 A KR930001901 A KR 930001901A KR 930018895 A KR930018895 A KR 930018895A
Authority
KR
South Korea
Prior art keywords
communication data
buffer memory
transmission
sending
communication
Prior art date
Application number
KR1019930001901A
Other languages
Korean (ko)
Other versions
KR960015864B1 (en
Inventor
고이치 다나카
Original Assignee
사토 후미오
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 사토 후미오, 가부시키가이샤 도시바 filed Critical 사토 후미오
Publication of KR930018895A publication Critical patent/KR930018895A/en
Application granted granted Critical
Publication of KR960015864B1 publication Critical patent/KR960015864B1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9021—Plurality of buffers per packet

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)
  • Small-Scale Networks (AREA)

Abstract

본 발명은 통신제어장치내의 버퍼 메모리의 용량을 가능한 한 적게 억제하면서 긴 프레임의 후에 복수개의 짧은 프레임이 연속해서 링크되는 바와 같은 불균일한 프레임 구조의 데이터를 송출하는 경우에도 고속처리가 가능한 통신제어장치를 제공하는 것을 목적으로 한다.The present invention provides a communication control device capable of high-speed processing even when transmitting data having an uneven frame structure such that a plurality of short frames are continuously linked after a long frame while suppressing the capacity of the buffer memory in the communication control device as little as possible. The purpose is to provide.

상기한 목적을 달성하기 위해 본 발명은, 당해 장치외부의 송신원(3)으로부터의 통신데이터를 검사하는 검사수단(9)과, 통신데이터를 유지하는 제1버퍼 메모리(11), 당해 장치외부의 통신망으로 송출하는 통신데이터를 취입 유지하는 제2버퍼 메모리(14), 통신망으로 통신데이터를 송출하는 송출수단(15), 송출종료시의 상태를 송신원(3)으로 되돌려 기입하는 송신상태 기입복귀수단(17) 및 검사수단(9)의 결과에 기초해서 정상적인 통신데이터만을 상기 제2버퍼 메모리(14)에 취입하고,송출처리 및 기입복귀처리의 제어를 수행하는 버퍼 관리수단(12)을 갖추어서 구성되어 있다.In order to achieve the above object, the present invention provides an inspection means 9 for inspecting communication data from a transmission source 3 outside the device, a first buffer memory 11 for holding communication data, A second buffer memory 14 for holding and holding the communication data sent to the communication network, a sending means 15 for sending the communication data to the communication network, and a transmission state write return means for returning and writing the state at the end of the sending to the transmission source 3 ( 17) and a buffer management means 12 which imports only normal communication data into the second buffer memory 14 on the basis of the result of the inspection means 9 and controls the sending process and the write return process. It is.

Description

통신제어장치Communication control device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 제1실시예에 따른 통신제어장치의 구성도.1 is a block diagram of a communication control device according to a first embodiment of the present invention.

제2도는 공유통신 데이터 메모리에서의 프레임 구조도.제2도(1)은 프레임버퍼(FB)의 데이타구조를 나타낸 도면.2 is a frame structure diagram of a shared communication data memory. FIG. 2 is a diagram showing a data structure of a frame buffer FB.

제2도(2)는 프레임 디스크립터(FD)의 데이터구조를 나타낸 도면.2 shows a data structure of a frame descriptor FD.

제2도(3)은 1개의 프레임 구성예를 나타낸 도면.2 is a diagram showing an example of one frame configuration.

제2도(4)는 3개의 프레임이 링크된 구성에를 나타낸 도면.2 is a diagram showing a configuration in which three frames are linked.

제3도는 제1실시예의 통신제어장치에서의 버퍼 관리부의 상세구성도.3 is a detailed configuration diagram of a buffer management unit in the communication control device of the first embodiment.

Claims (5)

당해 장치외부의 송신원(3,33)으로부터 송출되어 오는 통신데이터를 검사하는 검사수단(9,21)과, 상기 통신데이터를 유지하는 제1버퍼 메모리(11), 당해 장치외부의 통신망으로 송출하는 통신데이터를 취입해서 유지하는 제2버퍼 메모리(14,25), 상기 제2버퍼 메모리로부터 상기 통신망으로 통신데이터를 송출하는 송출수단(15), 송출종료시의 상태를 상기 송신원으로 되돌려 기입하는 송신상태 기입복귀수단(17) 및, 상기 검사수단의 결과에 기초해서 정상적인 통신 데이터만을 상기 제2버퍼 메모리에 취입하고, 상기 송출수단에 의한 송출처리 및 상기 송신상태 기입복귀수단에 의한 기입복귀처리의 제어를 수행하는 버퍼 관리수단(12,23)을 갖춘 것을 특징으로 하는 통신제어장치.Inspection means (9, 21) for inspecting the communication data sent from the source (3, 33) outside the apparatus, the first buffer memory (11) for holding the communication data, and the transmission to the communication network outside the apparatus Second buffer memories 14 and 25 for receiving and holding communication data, sending means 15 for sending communication data from the second buffer memory to the communication network, and a transmission state for writing the state at the end of sending back to the transmitting source Based on the write return means 17 and the result of the inspection means, only normal communication data is taken into the second buffer memory, and the sending process by the sending means and the control of the write return processing by the transmission state write return means are performed. Communication control device characterized in that it comprises a buffer management means (12, 23) for performing. 제1항에 있어서, 상기 버퍼 관리수단(12,33)이, 상기 검사수단(9,21)에서 정상이라고 판단된 통신데이터를 상기 제2버퍼 메모리(14,25)로 취입하기 위한 제어정보, 상기 송출수단(15)에 의한 그 통신데이터 송출에서의 송출종료시의 상태를 상기 송신원(3,33)으로 되돌려 기입하기 위한 제어정보 및 송출상태를 나타내는 데이터를 상기 송신원으로부터 송출되는 복수개의 통신데이터 각각에 대해 유지하는 제어데이터 유지수단(12-1,23-1)을 갖추고 있고, 상기 검사수단(9,21)에 의한 헤더검사, 상기 제2버퍼 메모리(14,25)로의 통신데이터의 취입, 상기 송출수단(15)에 의한 통신데이터의 송출 및 상기송신상태 기입복귀수단(17)에 의한 상기 송신원(3,33)으로의 제어정보 및 종료상태 데이터의 기입복귀의 각각의 처리가 병행해서 수행되는 것을 특징으로 하는 통신제어장치.2. The control information according to claim 1, wherein the buffer management means (12, 33) control the communication data determined to be normal by the check means (9, 21) to the second buffer memory (14, 25), The plurality of communication data transmitted from the transmission source, the control information for returning and writing the status at the end of transmission in the transmission of the communication data by the transmission means 15 to the transmission sources 3 and 33, and the data indicating the transmission status, respectively. Control data holding means (12-1, 23-1) held in relation to each other, the header checking by the checking means (9, 21), the import of communication data into the second buffer memory (14, 25), The processing of sending out communication data by the sending means 15 and writing back of the control information to the transmitting sources 3 and 33 by the sending state write return means 17 and the end state data are performed in parallel. Communication control, characterized in that Value. 제1항 또는 제2항에 있어서, 상기 제2버퍼 메모리(14,25)가 상기 송신원(3,33)으로부터 송출되는 복수개의 통신데이터를 유지하는 것을 특징으로 하는 통신제어장치.The communication control device according to claim 1 or 2, wherein the second buffer memory (14, 25) holds a plurality of communication data transmitted from the transmission source (3,33). 제1항 또는 제2항에 있어서, 상기 검사수단(9,21)이, 상기 제2버퍼 메모리(14,25)에 검사해야 할 통신데어터를 취입할 여유가 있을 때에는 그 통신데이터를 제2버퍼 메모리(14,25)에 취입시키고, 여유가 없을 때에는 상기 제1버퍼 메모리(11)에 취입시키는 것을 특징으로 하는 통신제어장치.The second buffer according to claim 1 or 2, wherein when the inspection means (9, 21) can afford to insert communication data to be inspected into the second buffer memory (14, 25). And a memory in the first buffer memory (11) when there is no space. 제1항 또는 제2항에 있어서, 상기 제1및 제2버퍼 메모리(11;14,25)가 1개의 버퍼메모리로 구성되고, 상기 송신원(3,33)으로부터 송신되어 오는 통신데이터 및 상기 통신망으로 송출하는 통신데이터가 각각 다른 소정의 기억영역에 유지되는 것을 특징으로 하는 통신제어장치.The communication data and the communication network according to claim 1 or 2, wherein the first and second buffer memories (11; 14,25) are constituted by one buffer memory, and are transmitted from the transmission sources (3,33). And communication data to be sent to each other are held in different predetermined storage areas. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930001901A 1992-02-14 1993-02-12 Control device in communication KR960015864B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP92-027879 1992-02-14
JP4027879A JPH0821971B2 (en) 1992-02-14 1992-02-14 Communication control device

Publications (2)

Publication Number Publication Date
KR930018895A true KR930018895A (en) 1993-09-22
KR960015864B1 KR960015864B1 (en) 1996-11-22

Family

ID=12233183

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930001901A KR960015864B1 (en) 1992-02-14 1993-02-12 Control device in communication

Country Status (2)

Country Link
JP (1) JPH0821971B2 (en)
KR (1) KR960015864B1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2002065709A1 (en) * 2001-02-14 2004-06-17 川崎マイクロエレクトロニクス株式会社 Network switching equipment
JP4629775B2 (en) * 2005-06-21 2011-02-09 エヌエックスピー ビー ヴィ Parallel testing method of data integrity of PCI Express device

Also Published As

Publication number Publication date
JPH0821971B2 (en) 1996-03-04
JPH0637852A (en) 1994-02-10
KR960015864B1 (en) 1996-11-22

Similar Documents

Publication Publication Date Title
KR910019369A (en) Method and apparatus for performing media access control / host system interface
KR920704222A (en) High-Speed, Flexible Source / Destination Data Burst Direct Memory Access Controller
KR890006019A (en) Network system using token passing bus method
KR880010366A (en) Microcomputer for communication control
KR970062934A (en) Data processing method and data processing device
KR910010506A (en) Semiconductor devices
KR890007173A (en) Address bus controller
EP0752669B1 (en) Apparatus for communicating between a plurality of function modules installed in a local bus unit and an external ARINC 629 bus
AU5062293A (en) A re-sequencing unit
KR930018895A (en) Communication control device
KR970700968A (en) A METHOD AND APPARATUS FOR COMMUNICATING BETWEEN NODES IN A COMMUNICATIONS NETWORK
FR3057127A1 (en) PROCESSOR ADAPTED FOR ETHERNET NETWORK DETERMINISTIC SWITCH
KR920008602A (en) Computer system with multiple input / output devices sharing address space and communication management method between input / output device and processor
KR850002721A (en) Vehicle information transmission device
KR920702117A (en) Communication systems
KR930008501B1 (en) Apparatus and method for transmitting and receiving message
KR920018610A (en) Character resource management system
KR960001269B1 (en) Buffer control method
KR940002722A (en) Data transfer and synchronization method between CPUs in a system consisting of two CPUs
JPS6478361A (en) Data processing system
ATE128301T1 (en) APPARATUS AND METHOD FOR ACCESSING A FACSIMILE STORAGE AND TRANSMISSION NETWORK.
JPS6031668A (en) Method for controlling distributed information processing system
KR900010590A (en) Information processing system
KR900019048A (en) Test circuit of semiconductor memory device
KR970056322A (en) Efficient Cell Receiving Processing Method and Device in Asynchronous Transmission Mode

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20031030

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee