KR940009740B1 - Power cut-off signal generating circuit for computer peripherals - Google Patents

Abstract

The circuit generates the power-down signal of the peripheral when a job is stopped during a given time and removes the power-down signal when a job is executed again. The circuit comprises a jumper adjusting serial port detection signal and address selection signal; an I/O detection PAL determining whether the I/O unit is used now or not; an internal operation detection PAL outputting delay signal and hardware disable signal; a power-down signal generation PAL; a counter.

Description

Power cutoff signal generating circuit of computer peripheral

Figure is a detailed circuit diagram of a power off signal generation circuit of a computer peripheral device according to an embodiment of the present invention.

The present invention relates to a power cutoff signal generating circuit of a computer peripheral device, and more specifically, to automatically cut off an AC input power applied to a peripheral device when a user stops working for a predetermined time while working with a computer. The present invention relates to a power cutoff signal generating circuit of a computer peripheral that generates a signal and releases a power cutoff signal in order to supply AC input power back to a peripheral when the user works again using a computer.

As the spread of personal computers spreads, the demand for peripheral devices such as monitors and printers, which are almost essential for the proper use of personal computers, is also increasing.

Conventional peripherals, such as the monitor or printer, if the user stops working for a while while working with a computer, if the user forgets to turn off the power switch to cut off the AC input power to the peripheral device As a result, AC input power is continuously applied. This disadvantage causes a problem that power is wasted by the peripherals despite the user not using the peripherals.

In order to solve such a disadvantage, a technology for a circuit for preventing the waste of power by automatically turning off the power supply when a video signal is not input to the monitor is disclosed in Korean Utility Model Application Publication No. 91-3424 (application date) : "Automatic power supply control circuit of TV" of December 31, 1987 AD, or "Automatic power off circuit of monitor" of Publication No. 91-3423 (Application date: December 31, 1987 AD); No. 90-8961 (filed November 29, 1985 AD), "Automatic Monitor Power-Off Circuit".

The " automatic power control circuit of the TV " controls the on / off operation of the switching transistor of the switching mode power supply (SMPS) according to the presence or absence of a video signal applied to the video input terminal of the monitor. Has an operating characteristic to automatically turn off the monitor, and the " automatic power off circuit of the monitor " has an operating characteristic to automatically turn off the monitor when an image signal is not output from a computer connected to the monitor, and One "monitor's automatic power off circuit" automatically shuts off power to the monitor when the keyboard is not input for a certain period of time while the system is in use, and reapplies the power to the monitor when the keyboard is input again. Has characteristics.

However, since the conventional "automatic power control circuit of the TV" cuts off the power of the monitor provided by the switching mode power supply when the video signal is not input, unlike the TV, and inputs data through the input device Although not, the video signal is difficult to apply to a computer having a characteristic that is continuously input to the monitor, and also has a disadvantage that it is difficult to apply to a monitor that is not a switching mode power supply.

In addition, unlike the TV, the " monitor auto-off circuit " also cuts off the power when the video signal is not input. Therefore, the video signal is continuously inputted to the monitor even though data is not input through the input device. It is meaningless to apply to a computer having a characteristic, and it is also difficult to apply to a device in which data is transmitted in parallel, such as a printer, because it is applicable only to a device in which data is transmitted in series such as a monitor.

In addition, the "monitor automatic power off circuit" relates to the configuration of a circuit for detecting only when data is not input from the keyboard for a predetermined time, and other input / output devices connected to a mouse or a serial communication port and a parallel communication port in addition to the keyboard. If the data is not input for a certain time from the disadvantage that it does not detect. This disadvantage causes a problem that the monitor is powered off because data is not input from the keyboard while the user is working with another input / output device such as a mouse.

Therefore, an object of the present invention is to solve the above-mentioned disadvantages, and the user does not have to cut off the AC input power directly applied to the peripheral device when the user stops working for a predetermined time while working with the pressure device. Generate a signal to automatically cut off the AC power applied to the peripheral device, and supply it back to the AC input power peripheral device when the user inputs data to the computer system through the input device to resume work using the computer. To provide a power off signal generating circuit of a computer peripheral device for releasing the power off signal.

A configuration of the present invention for achieving the above object is a jumper (jumper) connected between the ground and the serial port detection enable signal line and the address selection signal line respectively to allow the user to arbitrarily adjust the serial port detection and address selection signal; ; An input / output detection PAL (Programmable Array Logic) for detecting whether an input / output device is currently used or not from a serial port detection enable signal and an address selection signal line and an address signal and an address enable signal; A jumper for arbitrarily adjusting a delay time signal by a user connected between the other terminal of the pull-up resistor connected to the power supply voltage and the ground; An internal operation detection PAL that detects an internal state and an operation from a chip select signal, a data signal, a delay time signal, and a state signal of the input / output detection PAL and outputs a delay time signal and a hardware disable signal; I / O detection PAL I / O device usage detection signal and internal operation detection PAL Delay time signal, hardware disable signal, reset signal and I / O device read signal are detected when the I / O device is not used for a certain period of time. It is composed of a control PAL outputting a signal and a counter for clearing when a counter clear signal is input from the control PAL and continuing a counting operation and transmitting a current counting value signal to the control PAL.

With reference to the accompanying drawings, a preferred embodiment that can easily implement this invention by the above-described configuration will be described in detail.

Figure is a detailed circuit diagram of a power off signal generating circuit of a computer peripheral device according to an embodiment of the present invention. As shown in the figure, the configuration of the power-off signal generating circuit of the computer peripheral device according to the embodiment of the present invention is provided between the power supply voltage Vcc and the serial port detection enable signal line SIOSELN and the address select signal lines ASEL1 and ASEL2. A jumper (JP11 to JP13) connected between the pull-up resistors R11 to R13, ground (GND) and the serial port sense enable signal line (SIOSELN) and the address select signal lines (ASEL1 and ASEL2), and a serial port sense in, respectively. Input / output sensing PAL 10 having an input terminal connected to the enable signal line SIOSELN, the address select signal lines ASEL1 and ASEL2, the address signal lines SA0 to SA9, and the address enable signal line / AEN, and a power supply voltage Vcc. Pull-up resistors R21 to R24 each having one terminal connected to each other, jumper JP21 to JP24 connected between the other terminal of the pull-up resistors R21 to R24 and ground GND, and pull-up resistors R21 to R24 respectively. Connection point and delay time of jumper JP21-JP24 Resistors R25 to R28 connected between the arc lines / TSEL1 to / TSEL4, the chip select signal line / SCRTYCS and the data signal lines SD0 to SD7 of the input / output sensing PAL 10, and the delay time signal lines / TSEL1 to, respectively. / TSEL4) and the internal operation detection PAL (20) connected to the status signal lines (/ STATE1, / STATE2), the input / output device detection signal line (KBDCS) of the input / output detection PAL (10) and the internal operation detection PAL (20). A control PAL 30 having an input terminal connected to a delay time signal line / TSEL1 to / TSEL4, a hardware disable signal line / DISHW, a reset signal line RESET, and an input / output device readout signal line IORN, and a control PAL ( An input terminal is connected to the counter clear signal line / CLCNTN of 30, and an output terminal includes a counter 40 connected to the counting value signal lines CSEL1 to CSEL4 of the control PAL 30.

The operation of the power interruption signal generating circuit of the computer peripheral device according to the embodiment of the present invention by the above configuration is as follows.

In general, information transmission between the input / output unit and the central processing unit is performed by exchanging address signals, data signals, and control signals with each other through a system bus.

Therefore, whether the input / output device is currently used or not can be found by detecting a signal transmitted through the system bus.

The input / output detection PAL 10 detects whether the keyboard, the first serial port, and the second serial port are currently used by sensing the address signals SA0 to SA0 and the address enable signal AEN of the system bus.

That is, the input / output detection PAL 10 has a high input / output device when the address signals SA0 to SA9 transmitted through the system bus have 60H, 3F8H, and 2F8H values, and the address enable signal AEN is low. By outputting the usage detection signal (/ KBDCS) to the outside, it is detected that the input / output device is currently in use.

In this case, the address signal 60H is the designated address of the keyboard, the address signal 3F8H is the designated address of the first serial port, and the address signal 3F8H is the designated address of the second serial port.

The user can selectively determine whether the first and second serial ports are sensed by determining the on / off state of the jumper JP11. That is, when the user turns on the jumper JP11, the sense enable signal SIOSELN of the serial port in the low state is input, thereby detecting whether the serial port is used by the input / output detection PAL 10, and on the contrary, the user When the JP11 is turned off, the serial port detection enable signal SIOSELN is inputted so that the input / output detection PAL 10 does not detect whether the serial port is used.

In addition, the input / output detection PAL 10 determines the chip select signal / SCRTYCS based on the address signals SA0 to SA9 of the jumpers JP12 and JP13 and outputs them to the outside. That is, the address selection signals ASEL1 and ASEL2 are all high and the address signals SA0 to SA9 are low and the address selection signals ASEL1 and ASEL2 are respectively low and high and the address signals SA0 to SA9 are 110H or 100H. Or the address select signals ASEL1 and ASEL2 are high and low, respectively, and the address signals SA0 to SA9 are 120H, or the address select signals ASEL1 and ASEL2 are all low and the address signals SA0 to SA9 are In the case of 130H, the input / output detection PAL 10 outputs the chip select signal / SCRTYCS in the high state to the outside.

The internal structural formula of the input / output sensing PAL 10 operating as described above is as follows.

CHIP U1 PAL16L8

SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 GND

SA0 SCRTYCS KBDCS NC AEN ASEL1 ASEL2 SIOSELN NC VCC

Equations

/ KBDCS: = / AEN * / SA9 * / SA8 * / SA7 * SA6 * SA5 * / SA4

* / SA3 * / SA2 * / SA1 * / SA0; 60H (keyboard port)

+ / SIOSELN * / AEN * SA9 * SA8 * SA7 * SA6 * SA5 * SA4

* SA3 * / SA2 * / SA1 * / SA0; 3F8H (1st serial port)

+ / SIOSELN * / AEN * SA9 * / SA8 * SA7 * SA6 * SA5 * SA4

* SA3 * / SA2 * / SA1 * / SA0; 2F8H (2nd serial port)

/ SCRTYCS: = ASEL1 * ASEL2 * / AEN * / SA9 * SA8 * / SA7 * / SA6

* SA5 * SA4 * / SA3 * / SA2 * / SA1 * / SA0; 100H

+ / ASEL1 * ASEL2 * / AEN * / SA9 * SA8 * / SA7 * / SA6

* / SA5 * SA4 * / SA3 * / SA2 * / SA1 * / SA0; 110H

+ ASEL1 * / ASEL2 * / AEN * / SA9 * SA8 * / SA7 * / SA6

* SA5 * / SA4 * / SA3 * / SA2 * / SA1 * / SA0; 120H

+ / ASEL1 * / ASEL2 * / AEN * / SA9 * SA8 * / SA7 * / SA6

* SA5 * SA4 * / SA3 * / SA2 * / SA1 * / SA0; 130H

The internal motion detection PAL 20 determines whether to disable the hardware logic by detecting an internal state and an operation when a high chip select signal / SCRTYCS is input from the input / output detection PAL 10. Accordingly, the hardware disable signal (/ DISHW) is output to the outside.

That is, when the chip select signal / SCRTYCS of the high state is input, the internal motion detection PAL 20 has both the state signals / STATE1 and / STATE2 high and the data signals SD0 to SA7 are 91H. In this case, a high hardware disable signal (/ DISHW) is output.

The above state signal / STATE1 has the previous state signals / STATE1 and / STATE2 low, and the data signals SD0-SD7 are 37H, or the previous state signals / STATE1, / STATE2 low, respectively. State is high when the data signals SD0 to SD7 are 29H, and the above state signal / STATE2 is the high state and low state of the previous state signals / STATE1 and / STATE2, respectively. The signal becomes high when the SD0 to SD7 are 73H or the previous state signals / STATE1 and / STATE2 are low and the data signals SD0 to SD7 are 29H, respectively.

In addition, the internal motion detection PAL 20 detects an internal state and an operation and outputs the delay time signals / TSEL1 to / TSEL4.

That is, when the chip select signal / SCRTYCS of the high state is input from the input / output detection PAL 10, the internal operation detection PAL 20 has the state signals / STATE1 and / STATE2 low, high, and data signals, respectively. When (SD0) is 0H or when the chip select signal / SCRTYCS in the low state is input from the input / output detection PAL 10, the previous delay time signal / STEL1 is high or the state signal / STATE1 is high. High delay time signal / TSEL1 when the previous delay time signal / TSEL1 is high or the previous delay time signal / TSEL1 is high when the state signal / STATE2 is low. )

The internal motion detection PAL 20 has a status signal / STATE1 and / STATE2 that are low and high when the chip select signal / SCRTYCS of the high state is input from the input / output detection PAL 10, respectively, and the data signal ( SD1) is 0H, the previous delay time signal / TSEL2 is high when the chip select signal / SCRTYCS in the low state is input from the input / output detection PAL 10, or the state signal / STATE1 is high. When the previous delay time signal / TSEL2 is high or the status signal / STATE2 is low when the previous delay time signal / TSEL2 is high, the delay time signal / TSEL2 is high. Outputs

The internal motion detection PAL 20 has a status signal / STATE1 and / STATE2 that are low and high when the chip select signal / SCRTYCS of the high state is input from the input / output detection PAL 10, and the data signal ( SD2) is 0H, or the previous delay time signal / TSEL3 is high when the chip select signal / SCRTYCS in the low state is input from the input / output detection PAL 10, or the state signal / STATE1 is high. If the previous delay time signal / TSEL3 is high or the status signal / STATE2 is low, the previous delay time signal / TSEL3 is high, Output

The internal motion detection PAL 20 has a status signal / STATE1 and / STATE2 that are low and high when the chip select signal / SCRTYCS of the high state is input from the input / output detection PAL 10, and the data signal ( SD3) is 0H, or the previous delay time signal / TSEL4 is high when the chip select signal / SCRTYCS in the low state is input from the input / output detection PAL 10, or the state signal / STATE1 is high. If the previous delay time signal / TSEL4 is high or the status delay signal / STATE2 is low, and the previous delay time signal / TSEL4 is high, the delay time signal / TSEL4 is high. Outputs

In this case, the user can arbitrarily determine the output of the delay time signals / TSEL1 to / TSEL4 by determining the on / off states of the jumpers JP21 to JP24.

The internal structural formula of the internal motion detection PAL 20 operating as described above is as follows.

CHIP U2 PAL16R6

CLK SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 GND

OE DISHWN TSWL1 TSEL2 TSEL3 TSEL4 STATE1 STATE2 SCRTYCS VCC

Equations

/ DISHW: = / SCRTYCS * / STATE1 * / STATE2 * SD7 * / SD6 * / SD5 * SD4 * / SD3 * /

SD2 * SD1 * SD0

/ STATE1: = / SCRTYCS * STATE1 * STATE2 * / SD7 * / SD6 * SD5 * SD4 * SD3 *

SD2 * SD1 * SD0

+ / SCRTYCS * STATE1 * STATE2 * / SD7 * / SD6 * SD5 * SD4 * SD3 * /

SD2 * / SD1 * SD0

/ STATE2: = / SCRTYCS * / STATE1 * STATE2 * / SD7 * SD6 * SD5 * SD4 * / SD3 * /

SD2 * SD1 * SD0

+ / SCRTYCS * STATE1 * STATE2 * / SD7 * / SD6 * SD5 * / D4 * SD3 * /

SD2 * / DE1 * SD0

/ TSEL1: = / SCRTYCS * STATE1 * / STATE2 * / SD0

+ SCRTYCS * / TSEL1

+ / STATE1 * / TSEL1

+ STATE2 * / TSEL1

/ TSEL2: = / SCRTYCS * STATE1 * / STATE2 * / SD1

+ SCRTYCS * / TSEL2

+ / STATE1 * / TSEL2

+ STATE2 * / TSEL2

/ TSEL3: = / SCRTYCS * STATE1 * / STATE2 * / SD2

+ SCRTYCS * / TSEL3

+ / STATE1 * / TSEL3

+ STATE2 * / TSEL3

/ TSEL4: = / SCRTYCS * STATE1 * / STATE2 * / SD3

+ SCRTYCS * / TSEL4

+ / STATE1 * / TSEL4

+ STATE2 * / TSEL4

The control PAL 30 clears the counter in the high state when the input / output device read signal IORN of the system bus is low when the input / output device detection signal / KBDCS of the high state is input from the input / output detection PAL 10. The signal / CLCNTN is output to the counter 40.

The counter 40 resets the counting value to 0 when the counter clear signal / CLCNTN in the high state is input from the control PAL 30 and starts a new counting operation from zero. In this case, the current counting value that is continuously changing by the operation of the counter 40 is output to the control PAL 40 through the counting value signal lines CSEL1 to CSEL4.

The control PAL 30 compares the counting value signals CSEL1 to CSEL4 input from the counter 40 with the delay time signals / TSEL1 to / TSEL4 input from the internal motion detection PAL 20 to the external input / output device. Generate a power off signal (/ VOFF).

That is, the control PAL 30 has all of the delay time signals / TSEL1 to / TSEL4 input from the internal operation detection PAL 20 high or the input / output device usage detection signal (high) from the input / output detection PAL 10. When / KBDCS) is input, the auxiliary signal (/ DUMMY) is high when the I / O device read signal (IORN) of the system bus is low, or when the previous power off signal (/ VOFF) is high. When the set signal RESET is high, the high power cutoff signal / VOFF is output to the external input / output device.

The auxiliary signal / DUMMY has a delay time signal / TSEL4 high and a counting value signal CSEL4 high, or a delay time signal / TSEL4 low and a counting value signal CSEL4 low. State, delay time signal / TSEL3 is high and counting value signal CSEL3 is high, delay time signal / TSEL3 is low, counting value signal CSEL3 is low, or delay time signal (/ TSEL2) is low and the counting value signal CSEL2 is high, the delay time signal / TSEL2 is low and the counting value signal CSEL2 is low, or the delay time signal / TSEL1 is high. State and the counting value signal CSEL1 is high, or the delay time signal / TSEL1 is the serial port and the counting value signal CSEL1 is the high voltage signal.

In addition, the control PAL 30 has a hardware disable signal (/ DISHW) input from the internal operation detection PAL 20 low, and the reset signal RESET of the system bus is low, or a previous software enable. When the signal / ENSWN is high and the reset signal RESET is low, the software enable signal / ENSWN in the high state is output.

As described above, the internal structural formula of the control PAL 30 for controlling the operation is as follows.

CHIP U3 PAL16R4

CLK TSEL4 TSEL3 TSEL2 TSEL1 CSEL4 CSEL3 CSEL2 CSEL1 GND

OE IORN RESET CLCNTN CUMMY VOFF ENSWN DISHW KBDCS VCC

Equations

/ CLCNTN: = / KBDCS * / IORN

/ VOFF: = / TSEL4 * / TSEL3 * / TSEL2 * / STEL1

+ / KBDCS + / IORN

/ VOFF * / DUMMY

+ RESET

/ DUMMY: = / TSEL4 = CSEL4

+ TSEL4 * / CSEL4

+ / TSEL3 * / CSEL3

+ TSEL3 * / CSEL4

+ / TSEL2 * CSEL2

+ TSEL2 * / CSEL2

+ / TSEL1 * CSEL1

+ TSEL1 * / CSEL1

/ ENSWN: = / RESET * DISHW

+ / RESET * / ENSWN

As described above, in the embodiment of the present invention, when the user stops the work for a predetermined time while working with the input device, the AC power supplied to the peripheral device does not need to cut off the AC input power directly applied to the peripheral device. Generates a signal to automatically cut off the power supply and supplies a power off signal to supply AC input power back to the peripheral device when the user inputs data to the computer system through the input device in order to restart work using the computer. It is possible to provide a power cutoff signal generating circuit of a computer peripheral device having an effect of releasing it. This effect of the present invention can be used in the field to prevent unnecessary power consumption of the computer and peripherals.

Claims (4)

A jumper connected between ground and the serial port sense enable signal line and the address select signal line, respectively, to allow a user to arbitrarily adjust the serial port sense signal and the address select signal; An input / output detection PAL for detecting whether an input / output device is currently used or not from a serial port detection enable signal and an address selection signal line and an address signal and an address enable signal; A jumper for arbitrarily adjusting a delay time signal by a user connected between the other terminal of the pull-up resistor connected to the power supply voltage and the ground; An internal operation detection PAL that detects an internal state and an operation from a chip select signal, a data signal, a delay time signal, and a state signal of the input / output detection PAL and outputs a delay time signal and a hardware disable signal; I / O detection PAL input / output device usage detection signal and internal operation detection PAL delay time signal, hardware disable signal, reset signal and I / O device read signal are detected when the input / output device is not used for a certain time to external I / O device. Control PAL to output; And a counter for clearing when a counter clear signal is input from the control PAL, continuing a counting operation, and transmitting a current count value signal to the control PAL. The method of claim 1, wherein the input and output detection PAL, / KBDCS: = / AEN * / SA9 * / SA8 * / SA7 * / SA6 * / SA5 * / SA4 * / SA3 * / SA2 * / SA1 * / SA0; 60H (keyboard port) + / SIOSELN * / AEN * SA9 * SA8 * SA7 * SA6 * SA5 * SA4 * SA3 * / SA2 * / SA1 * / SA0; 3F8H (1st serial port) + / SIOSELN * / AEN * SA9 * / SA8 * SA7 * SA6 * SA5 * SA4 * SA3 * / SA2 * / SA1 * / SA0; 2F8H (2nd serial port) / SCRTYCS: = ASEL1 * AESL2 * / AEN * / SA9 * SA8 * / SA7 * / SA6 * SA5 * SA4 * / SA3 * / SA2 * / SA1 * / SA0; 100H + / ASEL1 * ASEL2 * / AEN * / SA9 * SA8 * / SA7 * / SA6 * SA5 * SA4 * / SA3 * / SA2 * / SA1 * / SA0; 110H + ASEL1 * / ASEL2 * / AEN * / SA9 * SA8 * / SA7 * / SA6 * SA5 * / SA4 * / SA3 * / SA2 * / SA1 * / SA0; 120H + / ASEL1 * / ASEL2 * / AEN * / SA9 * SA8 * / SA7 * / SA6 * SA5 * SA4 * / SA3 * / SA2 * / SA1 * / SA0; 130H A circuit for generating power cutoff signal of a computer peripheral, characterized in that consisting of the structural formula. The method of claim 1, wherein the internal motion detection PAL, / DISHW: = / SCRTYCS * / STATE1 * / STATE2 * SD7 * / SD6 * / SD5 * SD4 * / SD3 * / SD2 * SD1 * SD0 / STATE1: = / SCRTYCS * STATE1 * STATE2 * / SD7 * / SD6 * SD5 * SD4 * SD3 * SD2 * SD1 * SD0 + / SCRTYCS * STATE1 * STATE2 * / SD7 * / SD6 * SD5 * SD4 * SD3 * / SD2 * / SD1 * SD0 / STATE2: = / SCRTYCS * / STATE1 * STATE2 * / SD7 * SD6 * SD5 * SD4 * / SD3 * / SD2 * SD1 * SD0 + / SCRTYCS * STATE1 * STATE2 * / SD7 * SD6 * SD5 * / SD4 * / SD3 * / SD2 * / SD1 * SD0 / TSEL1: = / SCRTYCS * STATE1 * / STATE2 * / SD0 + SCRTYCS * / TSEL1 + / STATE1 * / TSEL1 + STATE2 * / TSEL1 / TSEL2: = / SCRTYCS * STATE1 * / STATE2 * / SD1 + SCRTYCS * / TSEL2 + / STATE1 * / TSEL2 + STATE2 * / TSEL2 / TSEL3: = / SCRTYCS * STATE1 * / STATE2 * / SD2 + SCRTYCS * / TSEL3 + / STATE1 * / TSEL3 + STATE2 * / TSEL3 / TSEL4: = / SCRTYCS * STATE1 * / STATE2 * / SD3 + SCRTYCS * / TSEL4 + / STATE1 * / TSEL4 + STATE2 * / TSEL4 Power off signal generation circuit of a computer peripheral device, characterized in that consisting of the structural formula. The method of claim 1, wherein the control PAL, / CLCNTN: = / KBDCS * / IORN / VOFF: = / TSEL4 * / TSEL3 * / TSEL2 * / STEL1 + / KBDCS + / IORN / VOFF * / DUMMY + RESET / DUMMY: = / TSEL4 * CSEL4 + TSEL4 * / CSEL4 + / TSEL3 * / CSEL3 + TSEL3 * / CSEL4 + / TSEL2 * CSEL2 + TSEL2 * / CSEL2 + / TSEL1 * CSEL1 + TSEL1 * / CSEL1 / ENSWN: = / RESET * DISHW + / RESET * / ENSWN Power off signal generation circuit of a computer peripheral device, characterized in that consisting of the structural formula.