KR930000482Y1 - Selecting circuit of transmission port using keyboard - Google Patents

Abstract

No content.

Description

Transmission port selection circuit using keyboard

1 is a conventional transmission port selection circuit diagram.

Figure 2 is a detailed view showing an embodiment of the transmission port selection circuit of the present invention.

* Explanation of symbols for main parts of the drawings

1: input / output decoder 2: input / output controller

3: Serial port 4: Parallel port

5: Interrupt signal output section

SW1, SW2: Serial and Parallel Port Enable Switch

SW3, SW4: Serial and parallel port selector switch

BF1-BF4: Buffer EOR1, EOR2: Exclusive Oagate

: Address enable signal A9-A3: Address signal

KS1, KS2: Port Selection Signal : Control signal

INT3-INT5, INT7: Interrupt signal

The present invention relates to a transmission port selection circuit using a keyboard for selecting a transmission port using a keyboard in a personal computer of the IBM compatible type.

Personal computers of the IBM compatible type have a transmission port that transfers data to and from the internal central processing unit and the external peripheral period as shown in Table 1 below.

TABLE 1

That is, two serial ports and two parallel ports are defined, and each serial port and the parallel port are assigned with their own interrupt numbers and input / output addresses.

When designing a personal computer with one serial port and one parallel port among these transmission ports, only one fixed port can be used and the port operation must be stopped when expanding by giving the same address and interrupt to other peripherals. It became. That is, FIG. 1 is a conventional transmission port selection circuit diagram having one serial port and one parallel port.

Here, reference numeral 1 denotes an input / output decoder. In this input / output decoder 1, the connection point of the resistor R1 and the serial port enable switch SW1 connected in series with the operating power source B + and the connection point of the resistor R2 and the parallel port enable switch SW2 are connected in series. Port Enable Terminal ( ) And parallel port enable terminal ( ) Are respectively connected to the address enable signal ( ) And address signals A9-A3 are input. 2 is an input / output controller. A serial port 3 and a parallel port 4 are connected to the input / output controller 2, and a control signal SI0 (PIO) output from the input / output decoder 1 and applied to the control terminal CSO CS1. The serial port 3 and the parallel port 4 are connected to a data bus so that the CPU and external peripherals can transmit data (D7-D0).

The transmission port selection circuit having such a configuration connects the switch SW1 to the serial port enable terminal ( Low potential is applied to the low potential address enable signal ( When the address signals A9-A3 set in the serial port 3 are input while the input signal is input, the input / output decoder 1 is connected to the control terminal (2) of the input / output controller 2. Low-potential control signal ( ) Will be printed. Then, the input / output controller 2 selects the serial port 3, and the external device and the central processing unit connected to the serial port 3 transmit data to each other.

Also, by connecting the switch SW2, the parallel port enable terminal ( Low potential is applied to the low potential address enable signal ( When the input signal A9-A3 set to the parallel port 4 is input while the input signal is input, the input / output decoder 1 is connected to the control terminal (2) of the input / output controller 2. High control signal ( ) Will be printed. Then, the input / output controller 2 selects the parallel port 4, and the external device and the central processing unit connected to the parallel port 4 transmit data to each other.

Then, open all the switches SW1 and SW2 so that the serial port enable terminal ( ) And parallel port enable terminal ( When the high potential is applied to the address enable signal ( ) And the address signals A9-A3, the input / output decoder 1 receives the control signal ( ) ( ), The input / output controller 2 does not select both the serial port 3 and the parallel port 4.

However, the conventional transmission port selection circuits as described above cannot use the parallel port 3 and the parallel port 4 provided only one in a fixed state, and also provide the serial port 3 and the parallel port to other input / output devices. (4) In case of applying the same address and interrupt as the address and interrupt given in (4), the switches SW1 and SW2 are opened to disable the operation of the serial port 3 and the parallel port 4. There was a problem to be done.

Therefore, it is an object of the present invention to provide a transmission port selection circuit that allows a serial port and a parallel port, which are provided one by one, to be used as if two are provided according to the operation of the keyboard.

The present invention having such a purpose is provided with a separate serial port selection switch and a parallel port selection switch, so that the keyboard BIOS unit outputs the port selection signal according to pressing a specific key of the keyboard. And. The I / O decoder is controlled by the I / O controller according to the switching of the port selection signal, address enable signal and address signal output from the keyboard BIOS unit, serial port selection switch, parallel port selection switch, serial port enable switch and parallel port enable switch. Outputs a signal to allow the input / output controller to select a transmission port and to output an interrupt signal.

In addition, the port selection signal output from the keyboard bias unit and the interrupt signal output unit determine the selected transmission port, and outputs the interrupt signal of the selected transmission port according to the determination signal.

Therefore, according to the present invention, the input / output decoder controls the input / output controller according to the switch switching, the address enable signal, the address signal, and the port selection signal to select a transmission port, and output an interrupt signal according to the selected transmission port. The interrupt signal output unit separates the interrupt signal output from the I / O controller according to the switching state of the selection signal and the switch, and uses the serial port and the parallel port each having two serial ports.

Hereinafter, with reference to the drawings of Figure 2 showing a preferred embodiment of the present invention will be described in detail, where the same parts as in the prior art.

As shown in FIG. 2, the switching of the switches SW1 and SW2, the address enable signal ( ) And a control signal output by the input / output decoder 1 in accordance with the address signals A9-A3 ) ( In the transmission port selection circuit in which the input / output controller 2 selects the serial port 3 and the parallel port 4 and selectively outputs an interrupt signal to the interrupt terminals IT0 and IT1, The port selection signals KS1 and KS2 outputted by the keyboard BIOS unit are output to the first serial port selection terminal SP1 and the first parallel port selection terminal PP1 of the input / output decoder 1 in response to pressing a key set in advance. The connection points of the resistor R3 and the serial port selector switch SW3 and the connection point of the resistor R4 and the parallel port selector switch SW4 connected in series with each other and connected to the power supply B + are connected to the input / output decoder 1. Connected to the second serial port selection terminal SP2 and the second parallel port selection terminal PP2.

Then, the interrupt terminal ITO (IT1) of the input / output controller 2 is connected to the input terminals of the buffers BF1, BF2 (BF3, BF4), and the connection point and the port selection signal of the resistor R3 and the switch SW3. (KS1) is connected to the control terminals of the buffers BF1 and BF2 via the exclusive orifice EOR1 so that the interrupt signals INT3 and INT4 are output from the output terminals of the buffers BF1 and BF2 and the resistors The connection point of the switch R4 and the switch SW4 and the port selection signal KS2 are connected to the control terminals of the buffers BF3 and BF4 via an exclusive ore gate EOR2, and at the output terminals of the buffers BF1 and BF2. The interrupt signal output section 5 is configured to output interrupt signals INT5 and INT7.

The input / output decoder 1 is a PAL (Programmable Array Logic) and a control signal ( ) ( Program the output to.

= A9 * A8 * A7 * A6 * A5 * A4 * A3 * * * * ; 3F8-3FF, INT4 A9 * * A7 * A6 * A5 * A4 * A3 * * SP1 * * ; 2F8-2FF, INT3 A9 * * A7 * A6 * A5 * A3 * * * SP2 * ; 2F8-2FF, INT3 A9 * A8 * A7 * A6 * A5 * A4 * A3 * * SP1 * SP2 * ; 3F8-3FF, INT4 = A9 * A8 * A7 * A6 * A5 * A4 * A3 * * * * ; 378-37F, INT7 A9 * * * A6 * A5 * A4 * A3 * * PP1 * * ; 278-27F, INT5 A9 * * A7 * A6 * A5 * A4 * A3 * * PP1 * * ; 278-27F, INT7 A9 * A8 * * A6 * A5 * A4 * A3 * * PP1 * PP2 * ; 378-37F, INT7

The operation of the present invention configured as described above will be described by dividing the switching state FH of the switches SW1-SW4.

[One. When the switch (SW1, SW3) is connected.]

Since the low potential is applied to the input terminals of the exclusive ore (EOR1) at the initial time when the operating power (B +) is turned on, the exclusive oragate (EOR1) outputs the low potential to the buffer (BF2). ) Will work.

At this time, the serial port enable terminal of the input / output decoder 1 ) And the serial port select terminals SP1 and SP2 are all low potential.

In this state, when the CPU transmits data through the serial port 3, a low potential address enable signal ( ) And 3F8-3FF (Hex) address signals (A9-A3) are outputted, the input / output decoder 1 outputs A9 * A8 * A7 * A6 * A5 * A4 * A3 * * * * The low potential control signal ( ) And the control terminal of the input / output controller 2 Is applied.

Therefore, the input / output controller 2 selects the serial port 3 and outputs a high potential interrupt signal to the interrupt terminal ITO. The interrupt signal is interrupt signal of the "serial port 1" through the buffer BF2. Output as (INT4).

Then, the CPU executes an interrupt routine according to the interrupt signal INT4 and transmits data with the peripheral device through the serial port 3, that is, by transmitting data through the "serial port 1".

If the transmission port is changed in such a state, when the key of the keyboard is pressed to output the high potential port selection signal KS1 from the keyboard BIOS unit, the high potential is output from the exclusive oragate EOR1 and the buffer BF1 is output. ) Becomes the operating state.

When the central processing unit outputs the low-potential address enable signal AEN and outputs the address signals A9-A3 of 2F8-2FF (Hex), the input / output decoder 1 outputs A9 *. * A7 * A6 * A5 * A4 * A3 * SP1 * * The low potential control signal ( ) And the control terminal of the input / output controller 2 Is applied.

Therefore, the input / output controller 2 selects the serial port 3 and outputs a high potential interrupt signal to the interrupt terminal ITO. The interrupt signal is interrupt signal of the "serial port 2" through the buffer BF1. Output as (INT3).

Then, the CPU executes an interrupt routine according to the interrupt signal INT3 and transmits data with the peripheral device through the serial port 3, that is, by transmitting data through the "serial port 2".

[2. When switch SW1 is connected and switch SW3 is open.]

Since the high potential and low potential are applied to the input terminal of the exclusive ore (EOR1) at the initial time when the operating power (B +) is turned on, the exclusive oragate (EOR1) outputs the high potential and buffers the input voltage. (BFI) is activated.

At this time, the serial port enable terminal of the input / output decoder 1 ) And the serial port select terminals SP1 and SP2 are all supplied with low potentials, and the serial port select terminals SP2 are applied with high potentials.

In this state, when the CPU transmits data through the serial port 3, a low potential address enable signal ( ) And 2F8-2FF (Hex) address signals A9-A3 are outputted, the input / output decoder 1 generates A9 *. * A7 * A6 * A5 * A4 * A3 * * * SP2 * The low potential control signal ( ) And the control terminal of the input / output controller 2 Is applied.

Therefore, the input / output controller 2 selects the serial port 3 and outputs a high potential interrupt signal to the interrupt terminal 170. The interrupt signal is interrupt signal of the "serial port 2" through the buffer BF1. Output as (INT3).

Then, the CPU executes an interrupt routine according to the interrupt signal INT3 and transmits data with the peripheral device through the serial port 3, that is, by transmitting data through the "serial port 2".

When changing the transmission port in such a state, when the key of the keyboard is pressed to output the high potential port selection signal KS1 from the keyboard BIOS unit, the high potential is output from the exclusive oragate EOR1 and the buffer BF2. Becomes the operating state.

The central processing unit then performs a low potential address enable signal ( In addition to outputting the address signal A9-A3 of 3F8-3FF (Hex), the input / output decoder 1 outputs A9 * A8 * A7 * A6 * A5 * A4 * A3 *. * SP1 * SP2 * Since the logic condition of the input / output decoder 1 is satisfied, the low potential control signal ( ) And the control terminal of the input / output controller 2 Is applied.

Therefore, the input / output controller 2 selects the serial port 3 and outputs a high potential interrupt signal to the interrupt terminal IT0. The interrupt signal is interrupt signal of the "serial port 1" through the buffer BF2. Output as (INT4).

Then, the CPU executes an interrupt routine according to the interrupt signal INT4 and transmits data with the peripheral device through the serial port 3, that is, by transmitting data through the "serial port 1".

[3. When the switch (SW2, SW4) is connected.]

Since the low potential is applied to all the input terminals of the exclusive ore (EOR2) at the initial time when the operating power (B +) is turned on, the exclusive oragate (EOR2) outputs the low potential to the buffer (BF4). ) Will work.

At this time, the parallel port enable terminal of the input / output decoder 1 ) And the parallel port select terminals PP1 and PP2 are all low potential.

In this state, the central processing unit transmits data through the parallel port 4 so as to enable a low potential address enable signal ( And the address signals A9-A3 of 378-37F (Hex) are outputted, the input / output decoder 1 generates A9 * A8 *. * A6 * A5 * A4 * A3 * * * * Since the logical condition of the input / output decoder 1 is satisfied, the low-potential control signal ( ) And the control terminal of the input / output controller 2 Is applied.

Therefore, the input / output controller 2 selects the parallel port 4 and outputs a high potential interrupt signal to the interrupt terminal 171. The interrupt signal is interrupt signal of the "parallel port 1" through the buffer BF4. Output as (INT7).

Then, the CPU executes an interrupt routine according to the interrupt signal INT7 and transmits data with the peripheral device through the parallel port 4, that is, by transmitting data through the "parallel port 1".

When changing the transmission port in such a state, when the key of the keyboard is pressed to cause the high-potential port selection signal KS2 to be output from the keyboard BIOS unit, the exclusive OA gate EOR2 outputs the high potential and the buffer BF3. ) Becomes the operating state.

The central processing unit then performs a low potential address enable signal ( ) And the address signals A9-A3 of 278-27F (Hex) are outputted. * A7 * A6 * A5 * A4 * A3 * * * PP2 * Since the logic condition of the input / output decoder 1 is satisfied, the low potential control signal ( ) And the control terminal of the input / output controller 2 Is applied.

Therefore, the input / output controller 2 selects the parallel port 4 and outputs a high potential interrupt signal to the interrupt terminal IT1. The interrupt signal is interrupt signal of the "parallel port 2" through the buffer BF3. Output as (INT).

Then, the CPU executes an interrupt routine according to the interrupt signal INT3 and transmits data with the peripheral device through the parallel port 4, that is, by transmitting data through the "parallel port 2".

[4. When switch SW2 is connected and switch SW4 is opened.]

Since the high potential and low potential are applied to the input terminal of the exclusive oar (EOR2) at the initial time when the operating power (B +) is turned on, the exclusive oragate (EOR2) outputs a high potential to buffer (BF3) is activated.

At this time, the parallel port enable terminal of the input / output decoder 1 ) And the parallel port select terminal PP1 are all applied with a low potential, and the parallel port select terminal PP2 is applied with a high potential.

In this state, the central processing unit transmits data through the parallel port 4 so as to enable a low potential address enable signal ( ) And 278-27F (Hex) address signals A9-A3 are outputted, the input / output decoder 1 outputs A9 *. * A7 * A6 * A5 * A4 * A3 * * * The low potential control signal ( ) And the control terminal of the input / output controller 2 Is applied.

Therefore, the input / output controller 2 selects the parallel port 4 and outputs a high potential interrupt signal to the interrupt terminal IT1. The interrupt signal is interrupt signal of the "parallel port 2" through the buffer BF3. Outputted as (INT5).

Then, the CPU executes an interrupt routine according to the interrupt signal INT5 and transmits data with the peripheral device through the parallel port 4, that is, by transmitting data through the "parallel port 2".

When changing the transmission port in such a state, if the key of the keyboard is pressed to output the high potential port selection signal KS2 from the keyboard BIOS unit, the exclusive OA gate EOR2 outputs the high potential and the buffer BF4. Becomes the operating state.

The central processing unit then performs a low potential address enable signal ( ) And the address signals A9-A3 of 378-37F (Hex) are outputted. * A6 * A5 * A4 * A3 * * PP1 * PP2 * Since the logic condition of the input / output decoder 1 is satisfied, the low potential control signal ( ) And the control terminal of the input / output controller 2 Is applied.

Therefore, the input / output controller 2 selects the parallel port 4 and outputs a high potential interrupt signal to the interrupt terminal IT1, and the interrupt signal is interrupt signal of the "parallel port 1" through the buffer BF4. Output as (INT7).

Then, the CPU executes an interrupt routine according to the interrupt signal INT7 and transmits data with the peripheral device through the parallel port 4, that is, by transmitting data through the "parallel port 1".

[5. When both switches SW1 and SW2 are opened.]

When both switches SW1 and SW2 are opened, the switch SW3 and SW4 are switched and the address enable signal ( ) And the address signals A9-A3, the input / output decoder 1 receives the control signal ( ) ( ), The I / O controller 2 does not select the transmission port, does not output the interrupt signal, and the data cannot be transmitted.

As described in detail above, the present invention can transmit data using the serial port and the parallel port, which are provided one by one using a keyboard, as well as by providing two same ports and interrupts to other peripheral devices. In the case of expansion, the expansion becomes very easy.

Claims (2)

Serial and parallel port enable switches SW1 and SW2, which designate the enable of the serial port 3 and the parallel port 4, respectively, serial and parallel port selector switches SW3 and SW4, and the switch ( SW1) (SW2) (SW3) (SW4) switching and address enable signal ( ), The control signal of the selected port by decoding the port selection signal KS1 (KS2) output from the keyboard BIOS unit according to the address signals A9-A3 and the keyboard operation. ) ( And an input / output decoder 1 for outputting the control signal ) ( I / O controller 2 for selecting the serial port 3 and the parallel port 4 to transmit data and outputting an interrupt signal to the interrupt terminals IT0 and IT1, and the switch SW3 ( SW4) and the port selection signal KS1 (KS2) are used to determine the selected port, and the interrupt signals output from the interrupt terminals IT0 and IT1, respectively, are interrupted by the "serial port 1" and "serial port 2". A transmission port using a keyboard comprising a signal INT4 (INT3) and an interrupt signal output section 5 for outputting an interrupt signal INT7 (INTS) of "parallel port 1" and "parallel port 2". Selection circuit. 2. The interrupt signal output section (5) according to claim 1, wherein the interrupt signal output section (5) is in parallel with a serial port respectively selected by the switching and port selection signal (KS1) of the switch (SW3) and the switching and port selection signal (KS2) of the switch (SW4). The OA gate EOR1 and EOR2 for determining a port and the output signal of the exclusive OOR1 EOR1 are selectively operated to generate an interrupt signal of the interrupt terminal IT0, respectively. And an interrupt terminal (IT1) while being selectively operated according to the buffer (BF2) (BF1) for outputting the interrupt signal (INT4) (INT3) of the "serial port 2" and the output signal of the exclusive oragate (EOR2). And a buffer (BF4) (BF3) for outputting the interrupt signals of the "parallel port 1" and the "parallel port 2" as interrupt signals (INT7) and (INT5), respectively.