JPH04128912A - Reset signal generation circuit - Google Patents

Reset signal generation circuit

Info

Publication number
JPH04128912A
JPH04128912A JP2250871A JP25087190A JPH04128912A JP H04128912 A JPH04128912 A JP H04128912A JP 2250871 A JP2250871 A JP 2250871A JP 25087190 A JP25087190 A JP 25087190A JP H04128912 A JPH04128912 A JP H04128912A
Authority
JP
Japan
Prior art keywords
reset
signal
slave
master
reset signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2250871A
Other languages
Japanese (ja)
Inventor
Yasumasa Ota
太田　康昌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP2250871A priority Critical patent/JPH04128912A/en
Publication of JPH04128912A publication Critical patent/JPH04128912A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent a work content at a slave side from being dissipated by providing a means which validates the reset switch of a master in a state where none of a plurality of slaves has been logged in. CONSTITUTION:When log-in from either slave is performed, a reset permission signal 5 is inactivated, and the reset switch outside the cabinet of the master is turned on, and a reset signal 6 is not activated even by activating a reset switch-on signal 1, and no reset operation is performed. Thereby, no reset signal is generated even by depressing the reset of the master when the log-in from the slave is performed, therefore, it is possible to prevent the work content at the slave side from being dissipated.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、リセット信号発生回路に関し、特にマルチ・
プログラミング・マシンのマスター・スレーブ方式に用
いるリセット信号発生回路に間する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a reset signal generation circuit, and particularly to a multi-channel
It is connected to the reset signal generation circuit used in the master-slave system of programming machines.

〔従来の技術〕[Conventional technology]

従来、この種のマスター・スレーブ方式に用いられてい
るリセット信号発生回路では、マスターのリセット・ス
イッチが押されると必ずリセット信号を発生する構成と
なっていた。Conventionally, reset signal generation circuits used in this type of master-slave system have been configured to generate a reset signal whenever the master's reset switch is pressed.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のリセット信号発生回路では、マスターの
リセット・スイッチが押されると必ずリセット信号を発
生する構成となっているので、スレーブからログ・イン
されている状態でマスターのリセット・スイッチが押さ
れるとスレーブ側の作業内容が失われてしまうという欠
点がある。The conventional reset signal generation circuit described above is configured to generate a reset signal whenever the master's reset switch is pressed, so the master's reset switch is pressed while the slave is logged in. This has the disadvantage that the work content on the slave side is lost.

本発明の目的は、スレーブからログ・インされている時
はマスターのリセットが押されてもリセット信号が発生
しないリセット信号発生回路を提供することにある。An object of the present invention is to provide a reset signal generation circuit that does not generate a reset signal even if the master's reset button is pressed when logged in from a slave.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のリセット信号発生回路は、複数のスレーブのい
ずれもログ・インしていない状態でのみマスターのリセ
ットスイッチが有効となる手段を有することを特徴とす
る。The reset signal generating circuit of the present invention is characterized by having means for making the reset switch of the master valid only when none of the plurality of slaves is logged in.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する、第１図
はスレーブを３つとした場合の実施例を示す回路精成図
である。いずれかのスレーブからログ・インしている状
態では、リセット許可信号５が非アクティブであり、マ
スターの筐体外側のリセット・スイッチをオンして、リ
セット・スイッチ・オン信号１がアクティブになっても
リセット信号６はアクティブにならず、リセット動作は
しない。Next, the present invention will be described with reference to the drawings. FIG. 1 is a detailed circuit diagram showing an embodiment in which there are three slaves. When logged in from one of the slaves, the reset enable signal 5 is inactive, and when the reset switch on the outside of the master's case is turned on, the reset switch on signal 1 becomes active. In this case, the reset signal 6 is not activated and no reset operation is performed.

第２図は、第１図に示す第１の実施例に、強制リセット
・スイッチを付加し、リセット許可信号が非アクティブ
に固定する等のトラブルに備え、強制的にリセット信号
を発生できるようにした他の実施例である０強制リセッ
ト・スイッチは、筐体内側に設け、容易にオンできない
ようにする。Fig. 2 shows a configuration in which a forced reset switch is added to the first embodiment shown in Fig. 1 so that a reset signal can be forcibly generated in case of troubles such as the reset permission signal being fixed inactive. In another embodiment, the 0 force reset switch is provided inside the housing so that it cannot be easily turned on.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、マスター・スレーブ方式
のコンピュータシステムにおいて、どのスレーブからも
ログ・インしていない状態で、かつリセット・スイッチ
が押された得の゛みリセット信号を発生する機能を有す
ることにより、スレーブからログ・インされている時、
マスターのリセットが押されてもリセット信号は発生せ
ず、スレーブ側の作業内容が失われてしまうことを防止
できる効果がある。As explained above, the present invention provides a function in a master-slave computer system to generate a reset signal when the reset switch is pressed while no slave is logged in. When logged in from the slave by having
Even if the reset button on the master is pressed, no reset signal is generated, which has the effect of preventing the contents of work on the slave side from being lost.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本発明の一実施例を示す回路精成図、第２図
は本発明の他の実施例を示す回路精成図である。 １・・・リセット・スイッチ・オン信号、２・・・スレ
ーブ１０グ・イン状態信号、３・・・スレーブ２０グ・
イン状態信号、４・・・スレーブ３０グ・イン状態信号
、５・・・リセット許可信号、６・・・リセット信号、
７・・・強制リセット・スイッチ・オン信号。FIG. 1 is a completed circuit diagram showing one embodiment of the present invention, and FIG. 2 is a completed circuit diagram showing another embodiment of the present invention. 1...Reset switch on signal, 2...Slave 10g-in status signal, 3...Slave 20g-in state signal
In state signal, 4...Slave 30-in state signal, 5...Reset permission signal, 6...Reset signal,
7... Forced reset switch on signal.

Claims (1)

【特許請求の範囲】[Claims] 複数のスレーブのいずれもログ・インしていない状態で
のみマスターのリセットスイッチが有効となる手段を有
することを特徴とするリセット信号発生回路。1. A reset signal generation circuit comprising means for making a master reset switch effective only when none of the plurality of slaves is logged in.
JP2250871A 1990-09-20 1990-09-20 Reset signal generation circuit Pending JPH04128912A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2250871A JPH04128912A (en) 1990-09-20 1990-09-20 Reset signal generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2250871A JPH04128912A (en) 1990-09-20 1990-09-20 Reset signal generation circuit

Publications (1)

Publication Number Publication Date
JPH04128912A true JPH04128912A (en) 1992-04-30

Family

ID=17214251

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2250871A Pending JPH04128912A (en) 1990-09-20 1990-09-20 Reset signal generation circuit

Country Status (1)

Country Link
JP (1) JPH04128912A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5433478A (en) * 1992-07-02 1995-07-18 Toyota Jidosha Kabushiki Kaisha Impact-absorbing structure of a door trim
US5857702A (en) * 1996-01-31 1999-01-12 Toyota Jidosha Kabushiki Kaisha Impact energy absorbing member suitable for a vehicle door
US5925435A (en) * 1994-10-04 1999-07-20 Sumitomo Chemical Company, Limited Impact energy absorptive structures
US6170902B1 (en) 1996-12-19 2001-01-09 Nissan Motor Co., Ltd. Door trim covering a door for a vehicle

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5433478A (en) * 1992-07-02 1995-07-18 Toyota Jidosha Kabushiki Kaisha Impact-absorbing structure of a door trim
US5925435A (en) * 1994-10-04 1999-07-20 Sumitomo Chemical Company, Limited Impact energy absorptive structures
US6080463A (en) * 1994-10-04 2000-06-27 Sumitomo Chemical Co., Ltd. Impact energy absorptive structures
US5857702A (en) * 1996-01-31 1999-01-12 Toyota Jidosha Kabushiki Kaisha Impact energy absorbing member suitable for a vehicle door
US6170902B1 (en) 1996-12-19 2001-01-09 Nissan Motor Co., Ltd. Door trim covering a door for a vehicle

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