KR940009207B1 - Brushless dc motor - Google Patents

Abstract

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Description

Rectifierless DC Motor

1 is a block diagram of a non-commutator DC motor according to a first embodiment of the present invention.

2 is a circuit diagram of the electric motor and power supply circuit shown in FIG.

3 is a signal waveform diagram output from each of the circuit elements shown in FIG.

4 is a circuit diagram of the counter electromotive force detection circuit shown in FIG.

5 is a signal waveform diagram output from each of the circuit elements shown in FIG.

6 is a circuit diagram of the pulse generation circuit shown in FIG.

FIG. 7A is a signal waveform diagram outputted from each of the circuit elements shown in FIG. 6 in the normal rotation of the motor.

FIG. 7B is a signal waveform diagram output from each of the circuit elements shown in FIG. 6 at the time of starting of the motor. FIG.

8 is a circuit diagram showing another example of the pulse generation circuit shown in FIG.

FIG. 9A is a signal waveform diagram outputted from each of the circuit elements shown in FIG. 8 during normal rotation. FIG.

Fig. 9B is a signal waveform diagram outputted from each of the circuit elements shown in Fig. 8 at startup.

FIG. 10 is a circuit diagram showing another example of the pulse generation circuit shown in FIG.

FIG. 11A is a signal waveform diagram outputted from each of the circuit elements shown in FIG. 10 during normal rotation.

FIG. 11B is a signal waveform diagram outputted from each of the circuit elements shown in FIG. 10 at startup.

12 is a circuit diagram of the logic pulse generation circuit shown in FIG.

13 is a signal waveform diagram output from each of the circuit elements shown in FIG. 12 and a signal waveform diagram output from each of the circuit elements shown in FIG.

FIG. 14 is a circuit diagram of the selection signal generating circuit shown in FIG.

FIG. 15 is a circuit diagram of the position signal forming circuit shown in FIG.

FIG. 16 is a signal waveform diagram output from each of the circuit elements shown in FIG.

FIG. 17 is a circuit diagram showing another example of the pulse generating circuit shown in FIG.

FIG. 18 is a signal waveform diagram outputted from each of the circuit elements shown in FIG. 17 during normal rotation. FIG.

FIG. 19 is a signal waveform diagram outputted from each of the circuit elements shown in FIG. 17 at startup.

20 and 21 are vector diagrams showing the starting sequence of the rectifier motor shown in FIG.

* Explanation of symbols for main parts of the drawings

(1): back electromotive force detection circuit (2): logic pulse generating circuit

(3): pulse generating circuit (4): position signal forming circuit

(5): power supply circuit (6): selection signal generating circuit

(11), (12), (13): Stator winding (41): First counter

(42): second counter (43): transmission circuit

(44): Clock pulse generating circuit (100): Inclined waveform signal generating circuit

101 to 106: signal synthesis circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-rectifying direct current motor, and more particularly to a non-commutator direct current motor that does not include a position sensor for detecting a rotational position of a permanent magnet rotor.

Recently, since the rectifier DC motor does not make mechanical contact like a conventional rectifier DC motor, it is widely used in industrial equipment, audio or video, which not only reduces noise generation but also improves effective life, and thus requires high reliability. have.

In order to prevent the energization state of the stator winding of the motor, conventional non-commutator DC motors mostly use a rotor position sensor (for example, a Hall element) instead of using a commutator.

However, the rotor position sensor itself is not inexpensive, difficult to adjust the position to attach, and the number of wiring increases, so the price of the non-commutator DC motor is more expensive than the DC motor having a commutator.

In addition, there are structural restrictions in attaching the rotor position sensor to the inside of the motor. As industrial devices, audio or video are miniaturized, the thickness and size of electric motors are also miniaturized, so that the compartment space occupied by the rotor position sensor such as hall element is getting considerably smaller. Therefore, for example, various kinds of non-commutator DC motors without a rotor position sensor such as a hall element have been proposed.

As one of them, for example, the non-commutator DC motor disclosed in Japanese Patent Laid-Open No. 55-160980 is based on a so-called half-wave driving method of supplying a current in a single direction to the stator winding of the rotor. In this way, the counter electromotive force induced in the two stator windings which are stopped among the stator windings of three phases is detected, and the process of determining the next conducting phase of the detected signal is continuously supplied to the stator windings in a single direction. However, in this method, since the rotor is stopped when the electric motor is started, no counter electromotive force is generated in each stator winding. Therefore, the above-mentioned non-commutator DC motor according to the prior art is specifically provided with a starting circuit to excite a specific stator winding, thereby determining the initial position of the rotor in advance. However, in this case, even if only one phase of the stator winding is excited to determine the initial position of the rotor, the starting time is long because the rotor and the position are difficult to vibrate and stabilize.

In addition, since the conventional rectifier DC motor is based on the half-wave driving method in which current is supplied to the stator winding in a single direction, the structure of the starting circuit is not simple, and the utilization rate and efficiency of the stator winding are bidirectional to the stator winding. As compared with the non-commutator DC motor based on the radio wave driving method of supplying electric current, the generated torque is small.

In addition, for example, the non-commutator DC motor disclosed in Japanese Patent Laid-Open No. 62-260586 is based on a so-called radio wave driving method of supplying a current in both directions to a stator winding. The current flowing through the stator winding is forcibly rectified continuously when it is started by the start pulse signal output from the start pulse generating circuit, thereby driving the motor. The monostable multivibrator delays the output signal for a certain time by detecting the zero cross point of the counter electromotive force when the rotational speed of the motor is accelerated and the counter electromotive force is induced in the stator winding. Therefore, although the timing at which the current is energized is determined, in this case, even when the stator winding is forcibly and continuously switched by the pulse signal output from the starting circuit at the start, the rotor rotates while vibrating. Therefore, the zero cross point of each counter electromotive force can be properly detected by the detection circuit. However, the recross point of the counter electromotive force induced in the stator winding is detected from the starting mode in which the stator winding is continuously forcibly switched to drive the rotor. Conversion to the normal position detection mode for driving the rotor is difficult. That is, the timing of switching from the starting mode of the rotor to the normal position detection mode is technically difficult, so that the starting time of the motor is increased.

In addition, the above-described conventional rectifier DC motor uses a monostable multivibrator to delay the pulse signal generated at the zero cross point of the counter electromotive force induced in each of the stator windings for a predetermined period. I use the method of making a decision.

However, in this case, since the delay time is constant irrespective of the rotational speed of the electric motor, it is not suitable for the application field in which the rotational speed is to be changed, and thus lacks flexibility of melting.

In general, in a non-commutator DC motor without a rotor position sensor, the rotor is in a stopped state at the start, and no counter electromotive force is generated in each of the stator windings. As a result, since the conduction phase is not determined in the initial stage, there is a problem that the starting characteristics are significantly lower than a DC motor having a rotor position sensor without a rotor position sensor.

In addition, the phase-changing frequency suitable for the start-up is forcibly performed at the start-up, and the frequency of the phase-changing suitable for the start-up is largely changed depending on the load applied to the motor and the inertia of the rotor. Can be regarded as a type of synchronous motor. In either case, since the zero cross point of the counter electromotive force induced in each of the stator windings is not permanently detected properly, the zero cross point of each counter electromotive force is removed from the start mode in which the stator winding is continuously forced to switch the rotor. A problem has been pointed out that it is difficult to properly switch to the normal position detection mode for detecting and driving the rotor.

In the conventional rectifier DC motor as described above, the current flowing through the stator windings for driving is a square wave having a conducting width of about 120 ° at an electric angle. Therefore, in order to reduce the spike voltage induced by the phase switching, a filter circuit having a capacitor having a relatively large capacity must be provided in the energizing terminal of the stator winding in practice. In addition, the current flowing through the stator winding allows the on-off operation to have a steepness, thereby causing a problem of easily generating vibration and noise during startup, and the problem is accelerated as the rotational speed of the motor is increased.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a non-commutator DC motor which can obtain a good starting characteristic without using a specific starting circuit even though a position sensor is not provided.

Another object of the present invention is to provide a non-commutator DC motor driven by a radio wave driving method capable of supplying current to each of the stator windings in both directions.

Still another object of the present invention is to have a filter circuit having a large-capacity capacitor used in a non-commutator DC motor according to the prior art, and to generate a vibration and noise even when rotating at a high speed. To provide.

In order to achieve the above object, the non-commutator DC motor according to the present invention includes a plurality of stator windings and a counter electromotive force selected in response to a selection signal from the back electromotive force continuously induced in each of the plurality of stator windings to generate a pulse signal sequence. A counter electromotive force detection circuit that detects a zero cross point of? And generates a delay pulse signal that is delayed by a time proportional to or approximately proportional to the period of the pulse signal string when within a specific range, and generates a pseudo output pulse signal when exceeding a specific range. A pulse generator circuit for generating a plurality of phase signals in response to the pulse signal string output from the counter electromotive force detection circuit and a pseudo output pulse signal, and a plurality of phase selection signals in response to the delay pulse signal; A selection signal generating circuit and the logic pulse generating circuit And a position signal for forming a position signal of the rotor by an output pulse from the generating circuit, and in response to the position signals are formed as described above consists of a power supply circuit for supplying electric power to the stator windings on the plurality.

In the non-commutator DC motor according to the present invention configured as described above, the counter electromotive force detection circuit detects only the zero cross point of the counter electromotive force induced by the stator windings, so that each stator winding is bidirectionally without using a position sensor such as a hall element. It is possible to easily provide a non-commutator DC motor based on a radio wave driving method for supplying current. As a result, it is possible to provide an electric motor which is remarkably excellent in efficiency and generated torque in use of the stator winding as compared with the non-commutator DC motor based on the half-wave driving method of supplying current to each of the stator windings in a single direction.

In addition, since there is no need to use the rotor position sensor used in the conventional non-commutator DC motor, the non-commutator DC motor according to the present invention does not need to finely adjust the attachment position of the position sensor, and can also reduce the number of turns. Therefore, the cost can be reduced considerably.

In addition, since there is no need to provide a position sensor in the motor, structural restrictions are not followed, and thus the size and thickness of the motor can be reduced.

In the non-commutator DC motor according to the present invention, at start-up, even when the counter electromotive force detection circuit does not output a pulse signal, the pulse generating circuit outputs a pseudo output pulse to switch the energization phase of the stator winding continuously. As a result, the pseudo output pulse continuously switches the energization phase of the stator winding even without providing a specific starting circuit. When the counter electromotive force detection circuit detects a zero cross point of the counter electromotive force, the rotor is driven by detecting the zero cross point of the counter electromotive force induced in the stator winding in the start mode in which the stator winding is forcibly continuously switched to drive the rotor. Can be quickly switched to normal mode. In addition, at the time of starting the motor, the reverse electromotive force detection circuit can reliably detect the zero cross point of the counter electromotive force by switching the energized phase by a different cycle without switching the energized phase by a constant cycle. As a result, switching from the start mode to the normal mode can be reliably achieved. Therefore, it is possible to obtain a starting characteristic compatible with the starting characteristic obtained in a conventional electric motor having a rotor position sensor.

The non-commutator DC motor according to the present invention further includes a selection circuit for converting only the back electromotive force induced in the energized phase detected sequentially into a pulse signal string in response to the energized state of the stator winding. As a result, there is no malfunction in phase switching due to the detection error of the zero cross point of the counter electromotive force, and it can always be driven stably.

In addition, since the phase switching of the currents supplied to each of the stator windings can be performed fairly smoothly, it is not necessary to switch the current flowing through the stator windings into the on-off state rapidly. Therefore, since the filter circuit including the capacitor having a relatively large capacitance does not need to be connected to the energization terminal of the stator winding, the spike voltage generated due to phase switching can be reduced. As a result, it is possible to provide a non-commutator DC motor capable of driving in a state where vibration and noise are extremely small even when rotating at high speed.

EMBODIMENT OF THE INVENTION Hereinafter, the preferred embodiment by this invention is described, referring drawings.

1 is a block diagram of a non-commutator DC motor according to a first embodiment of the present invention. In Fig. 1, reference numeral 1 denotes a counter electromotive force induced by each of the three-phase stator windings 11, 12, and 13, and a counter electromotive force for receiving the six-phase selection signal output from the selection signal generation circuit 6. It is a detection circuit. The counter electromotive force detection circuit 1 detects the zero cross point of the three-phase counter electromotive force in response to the six-phase selection signal output from the selection signal generation circuit 6 and converts it into the pulse train m. The pulse train m represents each zero cross point of the three-phase counter electromotive force. The pulse string m output from the counter electromotive force detection circuit 1 is input to the logic pulse generating circuit 2 and the pulse generating circuit 3. The logic pulse generating circuit 2 divides the pulse string m output from the counter electromotive force detection circuit 1 into a frequency equal to the pulse signal of the counter electromotive force induced by the stator windings 11, 12, and 13. Outputs the 6-phase pulse signal. First, the pulse generation circuit 3 measures the period of the pulse train m, then delays the output pulse for approximately half of the measured period and outputs it to the selection signal generation circuit 6 as a delay pulse z. . In addition, when the measured period exceeds the specified range, the pulse generating circuit 3 outputs the pseudo output pulse t to the logic pulse generating circuit 2. The six-phase pulse signal generated by the logic pulse generating circuit 2 is transmitted to the position signal forming circuit 4 and converts the transmitted pulse signal into a rotation position signal of the permanent magnet rotor 27. These position signals are sent to the power supply circuit 5 which supplies electric power to the stator windings 11, 12, and 13. As shown in FIG. The power supply circuit 5 supplies current in both directions successively to the respective stator windings 11, 12, and 13 in response to the position signals output from the position signal forming circuit 4.

In the present invention configured as described above, the operation of the non-rectifying direct current motor will be described in detail below.

FIG. 2 is a circuit diagram of the power supply circuit 5 shown in FIG. In Fig. 2, reference numeral 27 denotes a permanent magnet rotor, reference numerals 11, 12, and 13 denote stator windings, respectively, reference numerals 21, 22, 23, 24, and 24 25 and 26 are drive transistors that supply power to the stator windings 11, 12, and 13 in response to on-off operations, respectively. Among these transistors, (21), (22) and (23) are PNP transistors, and (24), (25) and (26) are NPN transistors. Reference numeral 20 denotes a power source. Typically, the non-commutator direct current motors use six phase position signals obtained in response to the rotational position of the rotor 27 to drive transistors 21, 22, 23, 24, 25, and 26. By applying to each of the bases), the non- commutator DC motor is driven. First, power is applied to the transistors 21 and 25 so that current flows through the stator windings 11 and 12. Next, power is applied to the transistors 21 and 26 so that current flows through the stator windings 11 and 13.

The permanent magnet rotor 27 is rotated by continuously switching the phase as described above.

FIG. 3 shows signal waveforms output from each of the elements of the circuit 5 shown in FIG.

In FIG. 3, (a), (b), and (c) are waveforms of counter electromotive force induced in each of the stator windings 11, 12, and 13, and (d), (e), (f), (g), (h) and (i) are six-phase signals formed by the position signal forming circuit 4 and are the same as the six-phase position signals obtained in response to the rotational position of the rotor 27. . These signals are trapezoidal waveforms, and the method for obtaining these trapezoidal waveforms will be described later in detail with reference to the position signal forming circuit 4 of FIG. 15 and FIG.

Each of the six-phase position signals (d), (e), (f), (g), (h), and (i) corresponds to drive transistors 21, 22, 23, and 24 corresponding thereto. , (25) and (26). In this case, however, for each of the PNP transistors 21, 22, and 23, a signal is applied to the base of each transistor in the direction in which current flows, and the NPN transistors 24, 25 are used. Are applied to the base of each transistor in the direction in which current flows. The base current applied to each of the transistors is amplified and current is supplied to the collector corresponding to the base in proportion to each of the base currents. As a result, as shown in (j), (h), and (i) of FIG. 3, current is supplied to each of the stator windings 11, 12, and 13 in both directions. The permanent magnet rotor 27 is rotated by continuously switching the phase as described above.

A detailed description of the signal processing operation of each device according to the present embodiment will be given later.

4 is a circuit diagram of the counter electromotive force detection circuit 1 shown in FIG.

In Fig. 4, (14), (15), and (16) are resistors, and one end of the resistor is connected to the terminals of the stator windings (11), (12), and (13), respectively. The end is connected to a common connection point. Each of (31), (32), and (33) is a comparator, and one input terminal (+) of this comparator is connected to each of the stator windings (11), (12), (13), and the other of the comparator. The input terminal (-) of the side is connected to the common connection point of the resistors (14), (15) and (16), and (34), (35) and (36) are inverters. The output terminals of the comparators 31, 32, and 33 are connected to the input terminals of the inverters 34, 35, and 36, respectively. 71, 72, 73, 74, 75, and 76 are switches, and among these switches, one end of the switches 71, 73, 75 is an inverter 36 , (34), (35) are respectively connected to the output terminals, and one end of the switches (72), (74), (76) is connected to the output terminals of the comparators (32), (33), (31), respectively. . The other ends of the switches 71, 72, 73, 74, 75, and 76 are connected in common and are provided as output terminals of the counter electromotive force detection circuit 1.

The operation of the counter electromotive force detection circuit 1 shown in FIG. 4 will be described below with reference to FIG.

Since each of the resistors 14, 15, and 16 is connected to the stator windings 11, 12, and 13, the neutral points of the stator windings 11, 12, and 13 ( The same potential as 0) can be obtained at the common connection point of the resistors 14, 15 and 16. Therefore, as the electric motor, it is not necessary to take a signal line separately from the center points of the stator windings 11, 12, and 13. The counter electromotive force induced in the stator windings 11, 12, and 13 becomes a signal waveform as shown in Figs. 5A, 5B, and 5C, respectively. Each of these counter electromotive forces (a), (b), and (c) is input to the input terminals (+) of the comparators 31, 32, and 33 shown in FIG. 4, and the resistors 14, ( The potentials of the neutral points of the stator windings (11), (12), and (13) obtained at the common connection point of (15) and (16) are input to the input terminal (-) of the comparator. Therefore, the waveforms of the counter electromotive force (a), (b), and (c) are transformed from the output terminals of the comparators 31, 32, and 33 to (u), (v), and (w) in FIG. A pulse signal as shown is obtained. The pulse edges of the waveforms u, v, and w coincide with the zero cross points of the counter electromotive forces a, b, and c, respectively. In FIG. 5, (t1), (t2), (t3), (t4), (t5), and (t6) are six phases outputted from the selection signal generation circuit 6 to the counter electromotive force detection circuit 1. This signal is a selection signal waveform which delays the rising edge by approximately 30 degrees at an electric angle from the timing of the zero cross points of the counter electromotive force (a), (u), and (c). The switches 71, 72, 73, 74, 75, and 76 are switched on when these selection signals are "H" (high level), and the selection signals are " When it is L ”(low level), it is switched off. As a result, the signal waveform shown in (m) of FIG. 5 is obtained from the common connection point of the switches 71, 72, 73, 74, 75, and 76, whereby the counter electromotive force a ), a pulse string consisting of a pulse signal waveform having a rising edge coinciding with the zero cross point of (b) and (c) can be output. That is, by outputting a pulse at each of the zero cross points of the counter electromotive force (a), (b), and (c), six pulses (electric angles) for each period of the counter electromotive force (a), (b), and (c) are output. Outputs a pulse train m having 60 °).

Next, the operation of the pulse generating circuit 3 shown in FIG. 1 will be described in detail.

FIG. 6 is a circuit diagram of the pulse generating circuit 3 shown in FIG. 1, and FIG. 7A is a signal waveform showing signal waveforms output from each of the circuit elements shown in FIG. 6 at the time of the normal rotation of the motor. FIG. 7B is a signal waveform diagram outputted from each of the circuit elements shown in FIG. 6 at the time of starting of the electric motor.

In Fig. 6, reference numeral 41 denotes the first counter, 42 denotes the second counter, and 44 denotes the clock pulse generation circuit. The first counter 41 outputs a carry flag t when the count value is overflowed, and the second counter 42 outputs a zero flag z when the count value is zero. Reference numeral 43 denotes a transmission circuit which receives the pulse string m output from the counter electromotive force detection circuit 1 and the pulse signal t output from the first counter 41. The transmission circuit 43 outputs the reset pulse r for resetting the count value of the first counter 41 to the first counter 41 and loads the load pulse for loading the count value of the first counter 41. s) is output to the second counter 42. The reset terminal 45 has a set terminal 5 for receiving the pulse signal t output from the first counter 41 and a reset terminal for receiving the pulse string m output from the counter electromotive force detection circuit 1. It is a latch circuit having R). The output terminal Q of the latch circuit 45 outputs the switching signal sc to the clock pulse switching circuit 46. The clock pulse generator 44 has three types of clock pulses CK and 2CK (having a frequency twice as high as the clock pulse CK), and 4CK (4 times as the clock pulse CK). Has a). The clock pulses CK are output to the first counter 41, and the clock pulses 2CK and 4CK are output to the clock pulse switching circuit 46. The clock pulse switching circuit 46 selects the clock pulse 2CK or the clock pulse 4CK in response to the input switching signal sc, and uses the selected clock pulse as the clock signal cp as the second counter 42. Output to. In addition, the zero flag z output from the second counter 42 corresponds to the delay pulse z input to the selection signal generation circuit 6, and the pulse t output from the first counter 41. Corresponds to the pseudo output pulse t input to the logic pulse generating circuit 3.

The operation of the pulse generating circuit 3 shown in FIG. 6 during the normal rotation of the motor will be described below with reference to FIG. 7A. As shown in (m) and (t) of FIG. 7A, the counter electromotive force detection circuit 1 outputs a pulse string m at regular intervals, and since the first counter does not output a pulse t, the latch The output signal output from the output terminal Q of the circuit 45 can be reset, and the switching signal sc can remain at " L " as shown in Fig. 7A. When the switching signal sc is "L", the clock pulse switching circuit 46 selects the clock pulse 2CK and transmits it to the second counter 42 (DP = 2CK). The first counter 41 continuously counts up the clock pulse CK until the reset pulse r output from the transmission circuit 43 is received. The reset pulse r has a frequency equal to the frequency of the pulse train m output from the counter electromotive force detection circuit 1, and the count value of the first counter 41 is the pulse train m output from the counter electromotive force detection circuit 1. ) Cycles are counted.

The above state is shown analytically in Fig. 7A (P). The count value P of the first counter 41 is transmitted to the second counter 42 at the timing of the rope pulse s output from the transmission circuit 43. The second counter 42 down-counts the count value P obtained by measuring the period of the pulse train m to the clock pulse 2CK, so that the middle point of the pulse train of the load pulse s (or the pulse train m rises). In this case, the coefficient value can be zero. The state is shown analytically in Fig. 7A (q). Since the second counter 42 is configured to output a zero flag signal when the count value is 0, the second counter 42 can output a delay pulse z as shown in (z) of FIG. 7A. Zero cross of the counter electromotive force (a), (b), (c) induced in each of the stator windings (11), (12), and (13) by the rising edge of the pulse train (m) output from the counter electromotive force detection circuit (1) As the point is shown, the interval of the pulse train s output at the rising edge of the pulse train m corresponds to 60 ° in the electrical angle. Accordingly, the pulse signal z shown in FIG. 7A has a rising edge which is delayed by an electric angle by 30 ° from the zero cross points of the counter electromotive forces a, b, and c, and the selection signal generating circuit 6 Output as a delay pulse signal. Further, a relationship as shown in Fig. 7A exists between the phase of the load pulse signal s and the phase of the reset pulse signal r. By delaying the phase of the reset pulse r than the phase of the load pulse s, it is possible to reliably transmit the count value of the first counter 41 to the second counter 42. In the figure, the widths of the pulses s and r are each enlarged for convenience, but are actually considerably smaller than the pulse period.

Next, the operation of the pulse generating circuit 3 at the start of the motor will be described below with reference to FIG. 7B. The first counter 41 continues to count the clock pulse CK until the reset pulse r output from the transmission circuit 43 is received. In this case, however, since the rotor is stationary, the counter electromotive force detection circuit 1 does not output the pulse train m. As a result, the count value of the first counter 41 is monotonically increased as shown in Fig. 7B, and when the count value is overflowed, the first counter 41 transmits the pulse signal t to the transmission circuit. Output to the 43 and the latch circuit 45. The transmission circuit 3 receives the pulse signal t and outputs the reset pulse signal r and the load pulse signal s. By inputting the pulse signal t to the set terminal S of the latch circuit 45, the switching signal sc output from the latch circuit 45 is converted to " H " High level). When the switching signal sc becomes "H", the clock pulse switching circuit 46 selects the clock pulse 4CK from the clock pulse generating circuit 44 and sends it to the second counter 42 (CP = 4CK). . The second counter 42 loads the initial value with the load pulse s, down counts the count value, and when the count value down counts to '0', the zero flag (as a delay pulse) to the selection signal generating circuit 6. z).

The carry flag t is output to the logic pulse generating circuit 2 as a pseudo output pulse. When starting the motor, the counter electromotive force detection circuit 1 does not output the pulse train m, and the pseudo output pulse t performs the phase switching operation of the stator windings 11, 12, and 13 in sequence. It becomes a pseudo signal for this purpose, and the permanent magnet rotor 27 starts rotating by this pseudo output pulse signal t. At this time, as shown in FIG. 7B, when the pulse string m is output from the counter electromotive force detection circuit 1, the latch circuit 45 is reset by the pulse string m, and from this latch circuit 45 The switching signal sc outputted becomes "L". In this case, however, the second counter 42 counts down the pressure clock pulse remaining as the pressure pulse 2CK. The count value of this second counter 42 is as shown by the dotted line in (q) of FIG. 7B. As is apparent from the waveform shown by a dotted line in FIG. 7B, the second counter 42 down-counts the clock pulse so that the count value of the first counter 41 is transmitted before the count value becomes zero. Occurs. In this case, since the count value of the second counter 42 does not become zero, the delay pulse z is not output.

Therefore, since it is not shown in Fig. 7B, no delay pulse z is generated, so that the phase switching operation of the stator windings 11, 12, and 13 is forcibly executed by the pseudo output pulse t. Even in this case, the selection signal of the phase for detecting the zero cross point of induced back electromotive force cannot be output from the selection signal generation circuit 6, and thus the acceleration of the electric motor cannot be performed smoothly. Therefore, when the transmission circuit 43 receives the pulse signal t, pulse generation is performed so as to switch the clock pulse output from the clock pulse switching circuit 46 to the second counter 42 from 2CK to 4CK. The circuit 3 is constituted. As a result, the initial value transmitted to the second counter 42 is down counted with a clock pulse of (4CK), and this count value becomes zero at 1/2 time of the time required for down counting with a clock pulse of (2CK). . This is shown by the solid line in (q) of FIG. 7B. As a result, before the count value of the second counter 42 becomes zero, the count value of the first counter 41 is not transmitted to the second counter 42. This means that the count value of the second counter 42 is surely zero, as shown by the solid line in Fig. 7B, and outputs the delay pulse signal z. Thereafter, as shown in FIG. 7B, under the same conditions as in the normal rotation of the electric motor described above, the second counter 42 outputs the delay pulse signal z. The delay pulse signal z is transmitted to the selection signal generating circuit 6, and the power supply circuit 5 continuously switches the energized phase between the three-phase stator windings 11, 12, and 13. . Therefore, the motor is accelerated smoothly, so that a good starting characteristic of the motor is obtained.

8 is a circuit diagram of a pulse generation circuit showing still another example of the pulse generation circuit 3 shown in FIG. In the case of the normal rotation of the motor, the output waveform diagram from each of the components of the circuit shown in FIG. 8 is shown in FIG. 9A, and in the case of starting the motor, the waveform diagram of the output is 9B. It is shown in the figure. In this case, the same reference numerals are assigned to components having the same functions as those in FIG. 6, and are omitted in order to avoid duplication of detailed description thereof.

In FIG. 8, the first counter 41 is composed of an 8-bit digital counter, and the second counter 42 is composed of a 7-bit digital counter. The same clock pulse CK is input to each of the first counter 41 and the second counter 42. Reference numeral 47 is a switch transmission circuit composed of r switches, and is connected to the contact a or the contact b only for a short time by the load pulse signal s output from the transmission circuit 43. Further, the switch signal sc output from the latch circuit 45 is input to the switch transmission circuit 47, and when the load pulse s is input while the switching signal is "L", the switch transmission circuit 47 Is connected to the contact a, and the switch transmission circuit 47 is connected to the contact b when the switching signal is input under the state of "H". When the switch transmission circuit 47 is connected to the contact a, bits except for the least significant bit of the count value of the first counter 41 (upper 7 bits in the example of FIG. 9) are transmitted to the second counter 42. In addition, when the switch transmission circuit 47 is connected to the contact point b, the second bits (except the upper six bits in the example shown in FIG. 8) from the least significant bit of the count value of the first counter 41 are the second. It is transmitted to the counter 42, and "0" is transmitted to the most significant bit of the second counter 42.

The operation of the pulse generating circuit shown in FIG. 8 during the normal rotation of the permanent magnet rotor 27 will be described with reference to FIG. 9A.

During the normal rotation of the motor, the Q output signal of the latch circuit 45 is reset, and the switching signal sc is held at "L" as shown in FIG. 9A. As a result, when the load pulse s is input, the switch transmission circuit 47 is connected to the contact point a, and the second counter 42 removes the bits except the least significant bit of the count value P of the first counter 41. To send. Therefore, half of the count value P of the first counter 41 is given to the second counter 42 as an initial value. As a result, the second counter 42 down-counts the value of P / 2 corresponding to half of the count value obtained by counting the period of the pulse train m to the clock pulse CK, and pulse train of the load pulse s. At the midpoint of (or rising edge of pulse train m), the count value becomes zero. This state is shown analogically in (q) of FIG. 9A. When the count value of the second counter 42 becomes 0, the second counter 42 outputs a zero flag signal and outputs a delay pulse signal z as shown in FIG. 9A (z).

Next, the operation of the pulse generating circuit shown in FIG. 8 at the start of the motor will be described with reference to FIG. 9B. When the electric motor is started, the counter electromotive force detection circuit 1 does not output the pulse train m, and the first counter 41 continues to count the clock pulse CK. As a result, the count value of the first counter 41 is monotonically increased as shown in FIG. 9B, and when the count value is overflowed, the first counter 41 outputs the carry flag t and is transmitted. It transfers to the circuit 43 and the latch circuit 45. Therefore, the output signal from the latch circuit 45 becomes "H" as shown in Fig. 9B (sc). When the load pulse s is input under such a state, the switch transmission circuit 47 is connected to the contact point b to remove the bit except the one bit from the least significant bit of the count value P of the first counter 41. 2 is sent to the counter 42. Such a state is shown by the solid line in (q) of FIG. 9B. As apparent from (q) of FIG. 9B, a quarter value of the count value P of the first counter 41 is given to the second counter 42 as an initial value. In this case, however, as shown by a dotted line in (q) of FIG. 9B, when the pulse signal t is input to the transmission circuit 43, P / 2 corresponding to half of the count value of the first counter 41 is obtained. Is transmitted to the second counter 42 as an initial value as it is. Thereafter, as apparent from the waveform shown by the solid line in q of FIG. 9B, when the motor is started, the first counter 41 before the second counter 42 counts down the initial value and the count value becomes zero. The count of is transmitted to the second counter 42. In this case, since the count value of the second counter 42 does not become 0, the delay pulse z is not output.

As a result, as shown in Fig. 9B (z), no pulse signal X is generated. Therefore, since the phase reduction ring operation cannot be appropriately performed between the stator windings, acceleration of the electric motor cannot be performed smoothly. Therefore, when the transmission circuit 43 receives the carry flag signal t at the start of the motor, a value of P / 2 corresponding to half of the count value of the first counter 41 (in this case, except the least significant bit) 7 bits) are not directly transmitted to the second counter 42, but the switch transmission circuit 47 is connected to the contact point b for a short time at the time of transmission.

Therefore, a value of P / 4 (in this case, the upper 6 bits of the first counter 41) corresponding to one quarter of the count value of the second counter 42 is transmitted to the second counter, and this state is set to zero. It is shown by the solid line in (q) of FIG. 9b. As a result, the count value of the first counter 41 is not transmitted to the second counter 42 before the count value of the second counter 42 becomes zero. This is because the count value of the second counter 42 is surely zero and the zero flag signal z is output as a delay pulse signal. Thereafter, the second counter 42 outputs the delay pulse signal z as shown in Fig. 9B (z), similarly to the operation in the case where the electric motor is normally rotated. The delayed pulse signal z output in this manner is transmitted to the selection signal generating circuit 6, and the electric power supply circuit 5 supplies the energized phases of the stator windings 11, 12, and 13 of the three phases. Continue switching. Therefore, the motor is accelerated smoothly, so that a good starting characteristic of the motor is obtained. In the embodiment shown in FIG. 6, the clock frequencies supplied to the first counter 41 and the second counter 42 are different from each other. In this embodiment shown in FIG. Only frequency can be advantageously applied.

FIG. 10 is a circuit diagram of an essential part of the pulse generating circuit showing another example of the pulse generating circuit 3 shown in FIG. In the case of normal rotation of the motor, the waveforms of the circuit elements of the circuit shown in FIG. 10 are shown in FIG. 11A, and in the case of starting the motor, the waveforms are shown in FIG. 11B.

In addition, the same numerals are assigned to components having the same functions as those of FIG. 8, and detailed description thereof will be omitted in order to avoid duplication of description.

In FIG. 10, the first counter 41 is an 8-bit digital counter, and the second counter 42 is a 5-bit digital counter. The same clock pulse CK is input to the first counter 41 and the second counter 42, respectively. The first counter 41 up counts the clock pulse CK, and the second counter 42 down counts the clock pulse CK. The switch transmission circuit 47 is composed of five switches. The transmission circuit 43 (not shown) is connected to the contact a for a short time by the load pulse s, and the first counter 41 Bits except the least significant bit of the count value (5 bits in the example shown in FIG. 10) are transmitted to the second counter 42. In addition, when the count value of the first counter 41 overflows and outputs the carrier flag t, the switch transmission circuit 47 is connected to the contact point b for a short time, so that all of the second counter 42 Bit is set to "1".

The operation of the pulse generating circuit shown in FIG. 10 during the normal rotation of the permanent magnet rotor 27 will be described with reference to FIG. 11A.

The count value P of the first counter 41 is transmitted to the second counter 42 at the timing of the load pulse s output from the transmission circuit 43. In this case, however, since the bits other than the least significant bit of the first counter 41 are transmitted to the second counter 42, as shown in (q) of FIG. 11A, the second counter 42 has the first counter. Half of the count value P of 41 is transmitted as an initial value. Since the second counter 42 counts down the value of P / 2 corresponding to half of the count value obtained by counting the period of the pulse train s to the clock pulse CK, at the midpoint of the pulse train s. Thus, the count value down counted to zero. Therefore, the second counter 42 outputs the delay pulse signal z as shown in FIG. 11A. Therefore, as shown in FIG. 11A, the rising edge of the delay pulse signal z is delayed by an electric angle of 30 degrees from the zero point of back electromotive force (a), (b), (c).

Next, when the motor is started, the operation of the pulse generating circuit shown in FIG. 10 will be described with reference to FIG. 11B. Since the counter electromotive force detection circuit 1 does not output the pulse train m at the start of the motor, the first counter 41 continues to count up the clock pulse CK. As a result, the count value of the first counter 41 is monotonically increased as shown in Fig. 11B, and when the count value is overflowed, the first counter 41 outputs a carry flag t to switch. To the transmission circuit 47 and the transmission circuit 43 (not shown). The transmission circuit 43 receives the signal t and outputs the reset pulse r and the load pulse s. The second counter 42 has an initial value coded by this load pulse s. However, in this case, the transmission circuit 43 receives the signal t and sets the value of P / 2 (upper 7 bits) corresponding to half of the count value of the first counter 41 to (q) in FIG. 11B as it is. As shown in the figure, an initial value is sent to the second counter 42, which is a 7-bit counter. Therefore, as is apparent from the waveform shown by the dotted line in (q) of FIG. 11B, in this case, the first counter (42) down counts the value of P / 2 at the time of startup and before the count value becomes zero. The count value of 41 may be transmitted to the second counter 42. In this case, since the count value of the second counter 42 does not become zero, the delay pulse z cannot be output, and therefore, the pulse x as shown in (z) of FIG. 11 can be generated. none. Therefore, the pulse cannot be properly switched between the stator windings, so that the acceleration of the electric motor cannot be performed smoothly.

Therefore, when the electric motor is started, the transmission circuit 47 receives the signal t, and has a value of P / 2 equivalent to half of the count value of the first counter 41 (in this case, the count value of the first counter 41). Instead of sending the upper 7 bits except the least significant bit of < RTI ID = 0.0 > 1 < / RTI > A predetermined value (5 bits, in this case, all “1” s) smaller than the value of P / 2 corresponding to minutes is sent to the second counter 42. Therefore, as described above, in this case, before the count value of the second counter 42 becomes zero, the occurrence of the count value of the first counter 41 to the second counter 42 is prevented from occurring. can do. As a result, the count value of the second counter 42 is surely zero, and outputs the delay signal t. Therefore, the second counter 42 outputs the delay pulse z shown in Fig. 11 (z) in the same operation as when the electric motor rotates normally. This delay pulse z is transmitted to the selection signal generating circuit 6, and is continuously switched between the three-phase stator windings 11, 12, and 13 by the power supply rotation 5. Therefore, the vibrator is smoothly accelerated to obtain good starting characteristics.

In the embodiment shown in FIG. 8, at start-up, a value of P / 4 corresponding to 1/4 of the count value of the first counter 41 is sent to the second counter 42. On the other hand, in the embodiment shown in FIG. 10, at start-up, since a predetermined value (5 bits, which is all "1" in this case) smaller than the value of P / 2 is transmitted to the second counter 42, The number of bits sent to the two counters 42 can be advantageously reduced.

FIG. 12 is a circuit configuration diagram of the logic pulse generating circuit 2 shown in FIG. 1, and FIG. 13 is a diagram showing signal waveforms output from each of the components of the circuit shown in FIG.

In Fig. 12, reference numeral 82 denotes a two-input OR circuit that receives a pulse string m and a weft output pulse t output from the counter electromotive force detection circuit 1, and reference numeral 81 denotes an OR circuit 82 from the OR circuit 82. Six-phase ring counter that receives the output signal and outputs six-phase pulse signals p1, (p2), (p3), (p4), (p5), and (p6) from six terminals as shown in FIG. to be. Each pulse width of these signals is 60 ° in electrical angle. These six-phase pulse signals p1, p2, p3, p4, p5, and p6 are the position signal generation circuit 4 and the selection signal generation circuit 6 shown in FIG. Will be printed).

FIG. 14 is a circuit diagram of the selection signal generating circuit 6 shown in FIG. 1, and the signal waveforms of the respective parts are shown in FIG.

In Fig. 14, reference numerals 91, 92, 93, 94, 95, and 96 are D flip-flops, and the delayed pulse signal z output from the pulse generating circuit 3 is shown. Is input to the clock terminal C, and the six-phase pulse signals p1, (p2), (p3), (p4), (p5), and (p6) output from the logic pulse generation circuit 2 are input. The input terminal D is provided, respectively. As a result, each of the six-phase signals p1, (p2), (p3), (p4), and (p5), output from the logic pulse generating circuit 2, from each of the output terminals Q of the D flip-flop. Outputs the six phase signals t1, t2, t3, t4, t5, and t6 that delayed (p6) by the pulse width of each delay pulse signal z. Each of the waveforms of is indicated by (t1), (t2), (t3), (t4), (t5), and (t6) in FIG. These six-phase signals t1, t2, t3, t4, t5, and t6 are six-phase selection signals t1, t2, and t3 shown in FIG. , (t4), (t5), and (t6). The pulse width of this signal is 60 degrees at an electrical angle and is output to the counter electromotive force detection circuit 1.

FIG. 15 is a circuit diagram of the position signal forming circuit 4 shown in FIG. 1, and FIG. 16 is a signal waveform diagram showing signal waveforms output from each of the components of the circuit 4. As shown in FIG.

In Fig. 15, reference numeral 50 denotes a reset switch, and 51 denotes a charge / discharge capacitor for generating serrated waveform signals in response to an output signal from the logic pulse generating circuit 2. The reset switch 50 is for discharging the electric charge stored in the charging / discharging capacitor 51. Denoted at 52 is a constant current source circuit for supplying a charging current to the charge / discharge capacitor 51, and 54 is a buffer amplifier having an input terminal connected to the charge / discharge capacitor 51. The inclined waveform signal generating circuit 100 is constituted by the capacitor 51 for charge and discharge, the reset switch 50, the constant current source circuit 52, the buffer amplifier 54, and the like. Reference numeral 55 denotes a buffer amplifier having an input terminal connected to the reference voltage source 53, and reference numeral 56 denotes an inverting amplifier to which output signals from the buffer amplifiers 54 and 55 are input. Output signals of the respective buffer amplifiers 54, 55, and inverting amplifiers 56 are output to the signal forming circuits 101, 102, 103, 104, 105, and 106, respectively. do. However, in this case, since the signal forming circuits 101, 102, 103, 104, 105, and 106 have the same configuration, only the configuration of the signal forming circuit 101 is shown in FIG. Illustrated. In the signal forming circuit 101, 61, 62, and 63 are switches, and one end thereof is connected to the buffer amplifier 54, the buffer amplifier 55, and the inverting amplifier 56, The other end is commonly connected to the resistor 64. The voltage signal obtained through the resistor 64 is converted into a current signal by the current converting circuit 65 to become an output signal of the signal forming circuit 101.

Next, the operation of the position signal forming circuit 4 shown in FIG. 15 will be described below with reference to FIG.

When the switch 50 of the inclined waveform signal generating circuit 100 is opened, the constant current source circuit 52 is supplied with a constant current to the capacitor 51 for charging and discharging, and the charging and discharging is performed when the switch is closed. The electric charge stored in the capacitor 51 is discharged momentarily. In this case, however, the switch 50 is configured to close only for a short time of the rising edge timing of the pulse train m output from the potency power detecting circuit 1, so that the switch 50 is filled at the timing of the rising edge of the pulse train m. By discharging the electric charge stored in the dedicated capacitor 51 instantaneously, from the sawtooth image waveform signal generation circuit 100, as shown in Fig. 16 (st), an inclined waveform having the same phase as the pulse train m can be obtained. Can be. The signal waveform of the reference voltage source circuit 53 is shown in (sf) of FIG. 16, and the magnitude thereof is set equal to the peak value of the gradient waveform signal st.

The signal waveform output from the inverting amplifier 56 is shown in (sd) of FIG. The inverting amplifier 51 receives the signal sf output from the buffer amplifier 55 of the signal st output from the buffer amplifier 54, and as shown in (sd) of FIG. 16, the signal st. The signal (sd = sf-st) obtained by inverting is outputted. The switches 61, 62, and 63 constituting the signal forming circuit 101 operate in response to the pulse signals p1, p2, and p3 output from the logic pulse generating circuit 2. That is, when these signals are "H", they are switched on, and when these signals are "L", they are switched off, and output from the buffer amplifiers 54, 55, and inverting amplifiers 56, respectively. The signal is synthesized by the signal forming means 101. In addition, when the signals p1, p2, and p3 are all in the "L" region, the switches 61, 62, and 63 are all switched off, so that the potential of the resistor 64 is equal to the ground potential. Done. The synthesized voltage value obtained by this resistor 64 is converted into a current value (inflow current) by the current conversion circuit 65, and the position signal d of trapezoidal waveform as shown in (d) of FIG. output from d).

Similarly, the signal forming circuits 102, 103, 104, 105, and 106 are pulse signals p2, p3, p4, (p3, p4, p5), (p5, p6, p1). In response to (p6, p1, p2), the trapezoidal position signals e, (f), (g), (h), and (i) are respectively output from these output terminals. In this case, however, the position signals e, g, and i output from the signal forming circuits 102, 104, and 106, respectively, are the types through which current flows, and the circuit 103, The position signals f and (h) respectively outputted from the 105 are the types into which current flows in the same way as the signal d output from the circuit 101. The trapezoidal waveform signals (d), (e), (f), (g), (h), and (i) formed as shown in FIG. 16 become position signals of the permanent magnet rotor 27, It is input to the power supply circuit 5.

As is apparent from the above description, in the non-commutator DC motor of the present invention, the counter electromotive force detection circuit 1 includes six selection circuits t1, t2, t3, t4, t5, and t6. In response to this, only the zero cross points of the back EMFs (a), (b), and (c) induced in each of the stator windings (11), (12), and (13) are sequentially detected. Formulate with (m). When the vibrator is rotating normally, the logic pulse generating circuit 2 receives the pulse train m and receives the six-phase pulse signals p1, p2, p3, p4, p5, and p6. Occurs. In this case, however, since the counter electromotive force detection circuit 1 does not output the pulse string m at the time of starting of the motor, the logic pulse generating circuit 2 outputs from the pulse generating circuit 3 instead of receiving the pulse string m. The received pseudo output pulse t is generated to generate the six-phase pulse signals p1, p2, p3, p4, p5, and p6 as described above. These six-phase pulse signals p1, p2, p3, p4, p5, and p6 are output to the position signal forming circuit 4, respectively, and the position signals as shown in FIG. (d), (e), (f), (g), (h), and (i). Finally, the power supply circuit 5 sequentially stator windings 11, 12, in response to the position signals d, e, f, g, h, and i. As shown in Fig. 3 to (13), the drive currents j, k, and l are supplied in both directions, so that the permanent magnet rotor 27 is rotated.

Therefore, the DC motor of the present invention can provide an electronic drive motor capable of supplying current to each stator winding without using a position sensor such as a hall sensor in both directions, and without installing a special starting circuit. It is possible to provide an electric motor having good starting characteristics.

In the pulse generating circuit shown in FIG. 6, when the motor is rotating normally, the magnitude of the clock frequency of the signal input to the second counter is twice the magnitude of the clock frequency of the signal input to the first counter. Or an integer double thereof. In the pulse generating circuit shown in FIG. 8, when the motor rotates normally, the value transmitted to the second counter as an initial value was half the value of the counter value of the first counter. The value of / N times (N is an integer) may be sufficient.

As apparent from the above description, the pulse generating circuit 3 shown in Figs. 6, 8 and 10 is configured to repeatedly output the pseudo output pulse signal t at a constant cycle when the motor is operated. When the motor is started, the pulse generating circuit 3 supplies the switching pulses of a constant cycle to the logic pulse generating circuit 2 so that phase switching between the stator windings is forcibly performed at a constant frequency.

FIG. 17 is a circuit configuration diagram of the pulse generation circuit showing still another example of the pulse generation circuit 3 shown in FIG. This is constructed in accordance with the pulse generating circuit shown in FIG. 6, and repeatedly outputs the pseudo output signal t of another cycle to the logic pulse generating circuit 2 at the time of starting of the motor. FIG. 18 is a waveform diagram showing signal waveforms from each of the components of FIG. 17 before the normal circuit, and FIG. 19 is a waveform diagram showing signal waveforms from each of the components of FIG. 17 at the start of the motor. In Fig. 17, reference numeral 41 denotes a first counter, 42 denotes a second counter, and 44 denotes a clock pulse generation circuit. The clock pulse generation circuit 44 generates two types of clock pulses ck and 2ck, among which the clock pulses ck are input to the first counter 41 and the clock pulses 2ck (in this case) , The magnitude of the clock frequency is twice that of ck) is input to the second counter 42. The first counter 41 outputs the signal d2 of the most significant bit and the signal d1 of the intermediate bit, and these bit signals d1 and d2 thus output are transmitted to the data selector 145. The second counter 42 outputs a zero flag z when its count value is zero. The data selector 145 selects the bit signal d1 or the bit signal d2 in response to the selection signal C3 input thereto and outputs a pulse signal t. The transmission circuit 43 receives the pulse string m output from the counter electromotive force detection circuit 1 and the pulse signal t output from the data selector 145 to reset the count value of the first counter. The output pulse r is output to the second counter 42 to load the count value of the first counter 41 while outputting the reset pulse r to 41. The third counter 146 counts the number of pulses of the pulse signal t output from the data selector 145. The two types of bit outputs c2 and c3 output from the third counter 146 are input to the AND circuit 147. The AND circuit 47 is configured to output the bit output signals c2 and c3. If all are “H”, pulse signal qc of “H” is output. This pulse signal qc is a reset pulse of the third counter 146 for resetting the count value of the third counter. Further, the zero flag z output from the second counter 42 corresponds to the delay signal z input to the selection signal generation circuit 6, and the pulse signal t output from the data selector 145 is Corresponds to the pseudo output signal t input to the logic pulse generating circuit 2.

The operation of the pulse generating circuit 3 shown in FIG. 17 during the normal rotation of the motor will be described with reference to FIG.

The first counter 41 continues to count up the clock pulse ck until the reset pulse r output from the transmission circuit 43 is input. Since the reset pulse r is equal to the period of the pulse train m output from the counter electromotive force detection circuit 1, the count value of the first counter 41 is equal to the period of the pulse train m output from the counter electromotive force detection circuit 1. Count the period. This state is shown analytically in Fig. 18 (p). Since the period of the reset pulse signal r is sufficiently short when the motor is rotating normally, the bit output signals d1 and d2 output from the first counter 41 do not become “H”. In addition, the levels of the two signals d1 and d2 shown by dotted lines in FIG. 18 (p) are the counter values of the first counter 41 when the signals d1 and d2 are “H”, respectively. As shown, the data selector 145 does not output the pseudo output signal t as shown in (t) of FIG. The count value p of the first counter 41 is transmitted to the second counter 42 as an initial value at the timing of the load pulse s output from the transmission circuit 43. The second counter 42 counts down the count value p obtained by counting the period of the pulse train m output from the counter electromotive force detection circuit 1 to the clock pulse 2ck, so that the count value is the load pulse s. It becomes 0 at the midpoint of (or rising edge of pulse train m), and this state is shown analytically in (q) of FIG. The second counter 42 outputs a zero flag when the count value becomes 0, and outputs a pulse signal z to (z) in FIG.

The rising edges of the pulse train m of the counter electromotive force detection circuit 1 take the zero cross points of the counter electromotive forces a, b, and c induced in the stator windings 11, 12, and 13, respectively. The interval of the pulse is 60 ° in electrical angle. Therefore, the rising edge of the pulse signal z shown in (z) of FIG. 18 is delayed by an electric angle by 30 ° from the corresponding zero-closure points of the counter electromotive forces a, b, and c. The pulse signal z is output to the selection signal generation circuit 6 as a delay signal. Further, as shown in FIG. 18, there is a relationship between the reset pulse r and the phase of the load signal s. That is, since the reset pulse r is delayed from the load pulse s, the count value of the first counter 41 is reliably transmitted to the second counter 42. In Fig. 18, the pulse widths of the pulses r and s are shown in magnitude for convenience, but they are sufficiently small compared to the pulse period.

Next, the operation of the pulse generating circuit 3 shown in FIG. 17 at the time of starting the motor will be described with reference to FIG. The first counter 41 continuously counts up the clock pulse ck until the reset pulse r is input from the transmission circuit 43. In this case, however, the rotor 27 is in a stopped state, and the counter electromotive force detection circuit 1 does not output the pulse train m. Accordingly, the count value of the first counter 41 is monotonically increased as shown in Fig. 19 (p), and when the count value becomes a predetermined value (a portion shown by a dotted line in Fig. 19 (p)), The counter 41 outputs the bit output signals d1 and d2 to the data selector 145, which outputs the signal t to the transmission circuit 43. After receiving the signal t, the transmission circuit 43 outputs the reset pulse r and the load pulse s. The second counter 42 down loads the initial value with the load pulse s. When the count value down counted as above becomes 0, the second counter 42 outputs zero flag z as a delay pulse. At the start of the motor, the data selector 145 continuously outputs the pulse signal t without outputting the pulse string m of the counter electromotive force detection circuit 1. First, the data selector 145 selects the bit output signal d2 of the first counter 41 as the pulse signal t, and the third counter 146 counts the number of pulses of this signal d2. Here, the third counter 146 is constituted by a 3-bit counter, and counts the pulses as shown by (c1), (c2) and (c3) in FIG. When the third counter 146 sequentially counts the pulse signal t and the output signals c2 and c3 become “H” (that counts the pulse t six times), the AND circuit 147 The output signal qc of becomes "H". Therefore, this signal qc is transmitted to the third counter 146 to reset the input count value. Next, the above-described operation is repeated until the motor starts to rotate and the counter electromotive force detection circuit 1 outputs the pulse train m.

In this case, however, the output signal c3 from the third counter 46 is also used as the selection signal of the data selector 145, and the pulse signal t is counted four times as shown in (c3) in FIG. After that, it becomes “H”. As a result, the data selector 145 selects the bit output signal d1 of the first counter 41 as the pulse t at this time. Since the bit output signal d1 is an intermediate bit of the first counter 41, the count value of the first counter 41 is determined by the data selector 145 as shown in (p) of FIG. The second counter 42 is loaded in the second counter 42 in a shorter period than that obtained when the d2) is selected, and after loading the initial value with the load pulse s, the second counter 42 downcounts it and the second counter 42 The count value of is " zero " in a shorter period, and outputs a delay pulse signal z of a shorter period, as a result, a pulse z having a relatively long period is outputted four times. The other pulse z having a shorter period than that is repeatedly outputted twice, and these states are shown in (q) and (z) of FIG.

As described above, when the electric motor is started, the pulse generating circuit 3 shown in FIG. 17 repeatedly outputs a pulse having a relatively long cycle four times, and another pulse having a short cycle is repeatedly outputted twice. Output pseudo output pulse (t).

20 and 21 are vector diagrams of the pulse generating circuit 3 shown in FIG. 17 when the motor is started.

20 shows Φ of the synthesized current vector I of the motor and the permanent magnet rotor 27 when the logic pulse generating circuit 2 is continuously supplied with pseudo output pulses t of a certain period (this is a rotor ( 27) is a vector representing the position of the north pole. In FIG. 20, indicated by the dotted line is a position where the zero cross point of the counter electromotive force induced in the stator winding is subsequently detected, which is selected by the selection signal output from the selection signal generating circuit 6. As shown in FIG. That is, the counter electromotive force detecting circuit 1 detects the zero cross point of counter electromotive force when the magnetic pole vector Φ of the permanent magnetic flux rotor 27 passes through the dotted line shown in FIG. Outputs As is apparent from FIG. 20, the position where the zero cross point of the counter electromotive force is detected is also rotated in steps of 60 degrees each time in response to the output from the selection signal generating circuit 6. In this case, however, the magnetic pole vector Φ of the permanent magnet rotor 27 is already past the position for detecting the zero cross point of the counter electromotive force. In other words, this means that the counter electromotive force detection circuit 1 cannot permanently detect the zero cross point of the counter electromotive force. As a result, it is almost impossible to drive the motor by moving the normal position detection mode by detecting the zero cross point of the counter electromotive force, and the rotational acceleration of the motor cannot be smoothed.

On the other hand, in FIG. 21, the synthesized current vector of the motor is supplied to the logic pulse generating circuit 2 when a pulse having a relatively long period is repeatedly outputted four times and another pulse having a shorter period is repeatedly outputted twice. The positional relationship between (I) and the magnetic pole vector Φ of the permanent magnet rotor 27 is shown. Incidentally, in Fig. 21, indicated by the dotted line is the position of the zero cross point of the counter electromotive force subsequently detected in the same manner as in Fig. 20, which is selected by the selection signal output from the selection signal generation circuit 6. do. Since the pseudo output pulse t having a constant cycle is supplied to the logic pulse generating circuit 2 from the time of starting the motor to the fourth pulse, (a), (b), (c) and (d) of FIG. The period coincides with each of FIG. In this case, however, since the period of the fourth and sixth pseudo output pulses t is shorter than the previous four pulses, the permanent magnetic flux rotor 27 rotates to the position shown in Fig. 21E. Electrical switching is performed before. This state is shown in Fig. 21E. As is apparent from Fig. 21E, the permanent magnet rotor 27 is in a position delayed in the rotational direction as compared with the state shown in Fig. 20E. In addition, the permanent magnet rotor 27 is further delayed in the rotational direction by the sixth pseudo output pulse t having a short cycle. That is, it is located toward the position where the zero cross point of the counter electromotive force is detected. As a result, the counter electromotive force detection circuit 1 can detect the zero cross point of each counter electromotive force until the next pseudo output pulse t is supplied. This state is shown in FIG. 21 (f). After the counter electromotive force detection circuit 1 detects the zero cross points of the counter electromotive forces a, b, and c, the mode is understood as a normal position detection mode, so that the energizing switching of the stator windings of the motor is sequentially performed. The rotation of the electric motor is thereby smoothly accelerated.

In the pulse generation circuit shown in FIG. 17, the clock frequency of the signal input to the second counter 42 is twice the clock frequency of the signal input to the first counter 41, but this may be an integer multiple. The pulse generating circuit shown in Fig. 17 is based on the circuit shown in Fig. 6 so that pseudo output pulses t having different periods are repeatedly supplied to the logic pulse generating circuit 2 when the motor is started. Although it is arrange | positioned, it may be arrange | positioned based on the circuit shown in FIG.

In addition, the counter electromotive force detection circuit 1 shown in FIG. 1 uses three resistors connected in common in order to detect the potential of the neutral point 0 of the stator winding, but for this purpose, the signal line is separated from the neutral point of the stator winding of the motor. Of course, it can be used directly withdrawal. Further, in the above embodiment of the present invention described above, the motor is limited to a three-phase motor having a stator winding of Y (star) connection, but this is not limited to this, and it is also possible to use an electric motor of any phase. In addition, the non-commutator DC motor according to the present invention can be applied to a motor having a stator winding of a delta connection.

Claims (57)

A plurality of stator windings (11, 12, 13), pulse generating means (3) for generating one or more pulse signal strings having different periods at startup to sequentially switch the energized state of the stator windings; Logic pulse generating means (2) for generating the plurality of phase pulse signals in response to a pulse signal string output from the means, and position signal forming means (4) for forming a position signal in response to a pulse signal output from the logic pulse generating means (4) And a power supply means (5) for supplying electric power to the stator winding in response to the position signal. And a pulse having a period of I / N times (N is an integer) of the period after being output by a predetermined coefficient. A plurality of stator windings 11, 12, 13, back electromotive force detection means 1 for obtaining a pulse signal sequence in response to back electromotive force induced in the stator winding selected by the plurality of phase selection signals, and a delay pulse for delaying the pulse signal sequence A pulse generating means (3) for outputting a signal, a selection signal generating means (6) for outputting said plurality of phase selection signals in response to said delay pulse signal, and generating said pulse signals in response to said pulse signal strings; Logic pulse generating means (2), position signal forming means (4) for forming a position signal in response to a pulse signal output from said logic pulse generating means, and electric power for supplying electric power to said stator winding in response to said position signal. In the non-commutator DC motor having a supply circuit (5), the position signal forming means (4) is a pulse signal of the counter electromotive force detecting means (1) or the logic pulse generating means (2). In response to the inclination waveform signal generating means (100) and the signal forming means (101) (102) for forming a plurality of position signals in response to the pulse signal output from the logic pulse generating means ( A non-commutator DC motor comprising 103, 104, 105, and 106. A plurality of stator windings 11, 12, 13, back electromotive force detection means 1 for obtaining a pulse signal sequence in response to back electromotive force induced in the stator winding selected by the plurality of phase selection signals, and a delay pulse for delaying the pulse signal sequence A pulse generating means (3) for outputting a signal, a selection signal generating means (6) for outputting said plurality of phase selection signals in response to said delay pulse signal, and generating said plurality of phase pulse signals in response to said pulse signal strings; Logic pulse generating means (2), position signal forming means (4) for forming a position signal in response to a pulse signal output from said logic pulse generating means, and supplying electric power to said stator winding in response to said position signal; In a non-commutator DC motor having a power supply circuit (5), the pulse generating means (3) is connected to the counter electromotive force detecting means (1) in order to generate the delay pulse signal. And delay the pulse signal string outputted from the output signal, and the pulse generating means 3 maintains a delay time proportional to the period of the pulse signal string output from the counter electromotive force detecting means 1. And a means (42) for changing a delay time of said delay pulse signal in response to a cycle variation of a column. 4. The pulse generating means (3) according to claim 3, wherein the pulse generating means (3) outputs a delayed pulse signal delayed by a time equal to I / N times (N is an integer) of the period of the pulse signal string output from the counter electromotive force detecting means (1). A non-commutator DC motor, characterized in that. 4. The pulse generating means (3) according to claim 3, characterized in that the pulse generating means (3) outputs a delayed pulse signal delayed by a half of the period of the pulse signal string output from the counter electromotive force detecting means (1). Rectifier DC motors. A plurality of stator windings 11, 12, 13, back electromotive force detection means 1 for obtaining a pulse signal sequence in response to back electromotive force induced in the stator winding selected by the plurality of phase selection signals, and a delay pulse for delaying the pulse signal sequence Pulse generating means (3) for outputting a signal, selection signal generating means (6) for outputting said plurality of phase selection signals in response to said delay pulse signal, and generating said plurality of phase pulse signals in response to said pulse signal strings; Logic pulse generating means 2, position signal forming means 4 for forming a position signal in response to a pulse signal output from said logic pulse generating means, and electric power for supplying power to the stator winding in response to the position signal. In a non-commutator DC motor having a supply circuit (5), the pulse generating means (3) counts the period of the pulse signal string output from the counter electromotive force detecting means (1). A first counter means 41, a transfer means 43 for transmitting the count value of the first counter means 41 to the second counter means 42, and a proportional to the period of the pulse signal string from the transferred count value. And a second counter means (42) for outputting a delay pulse signal delayed by time, and a clock pulse generating means (44) for inputting a clock signal to the first and second counter means. . The non-commutator DC motor according to claim 6, wherein the clock signal frequency input to the second counter means is different from the clock frequency input to the first counter means. The non-commutator DC motor according to claim 6, wherein the clock signal frequency input to the second counter means (42) is an integer multiple of the clock frequency input to the first counter means (41). The non-commutator DC motor according to claim 6, wherein the clock signal frequency input to the second counter means (42) is twice the clock signal frequency input to the first counter means (41). The method according to claim 6, wherein the transmission means (43) transmits a value of I / N times (N is an integer) of the count value of the first counter means (41) to the second counter means (42). Rectifier DC motors. The non-commutator DC motor according to claim 6, wherein the transmission means (43) transmits a value of 1/2 times the count value of the first counter means (41) to the second counter means (42). A plurality of stator windings 11, 12, 13, back electromotive force detecting means 1 for generating a pulse signal string in response to back electromotive force induced in the stator winding selected by the plurality of phase selection signals, and a period of the pulse signal string is predetermined When the pulse signal string is delayed, the delay pulse signal delaying the pulse signal string is output to the logic pulse generating means 2, and when the period of the pulse signal string exceeds the predetermined range, the pseudo output pulse signal is output to the logic pulse generating means 2. Pulse generating means (3) for outputting to the < RTI ID = 0.0 >), < / RTI > logic pulse generating means (2) for generating a plurality of phase pulse signals in response to the pulse signal sequence and the pseudo output pulse signal, Selection signal generation means 6 for outputting a selection signal and position signal formation means for forming a plurality of position signals in response to a pulse signal output from said logic pulse generation means ( 4) and a power supply means (5) for supplying electric power to said stator winding in response to said position signal. 13. The gradient signal generating means (100) according to claim 12, wherein said position signal forming means (4) generates gradient waveforms in response to a pulse signal of said back electromotive force detecting means (1) or said logic pulse generating means (2). And signal forming means (101), (102), (103), (104), (105), (106) for forming a plurality of position signals in response to the pulse signal output from the logic pulse generating means (2). Non-commutator DC motor, characterized in that it comprises a). The non-commutator according to claim 12, wherein the pulse generating means (3) outputs a delay pulse signal delayed by a time proportional to the period of the pulse signal string output by the counter electromotive force detecting means (1). DC motor. The pulse generating means (3) according to claim 12, wherein the pulse generating means (3) is configured to delay the delayed pulse signal by delaying the period of the period of the pulse signal string output by the counter electromotive force detecting means (1) by N / N times (N is an integer). A non-commutator DC motor, characterized in that output. 13. The pulse generating means (3) according to claim 12, characterized in that the pulse generating means (3) outputs a delayed pulse signal delayed by a half of a period of the period of the pulse signal string output by the counter electromotive force detecting means (1). Rectifier dc motor. 13. The pulse generating means (3) according to claim 12, wherein said pulse generating means (3) comprises a first counter means (41) for counting a period of said pulse signal string output from said counter electromotive force detecting means (1), and a count value of said one count means; A transmission means 43 for transmitting to the second counter means 42, a second counter means 42 for outputting a delay pulse signal delayed by a time proportional to the period of the pulse signal string from the transmitted count value, and the first counter means 42; And a clock signal generating means (44) for inputting a clock signal to the second counter means. 18. The non-commutator DC motor according to claim 17, wherein the clock signal frequency input to the second counter means (42) is different from the clock frequency input to the first counter means (41). 18. The non-commutator DC motor according to claim 17, wherein the clock signal frequency input to the second counter means (42) is an integer multiple of the clock signal frequency input to the first counter means (41). 18. The non-commutator DC motor according to claim 17, wherein the clock signal frequency input to said second counter means (42) is twice the clock signal frequency input to said first counter means (41). 18. The non-commutator DC motor according to claim 17, characterized in that the initial value transmitted to the second counter means (42) is different in response to the count values of the transmission means (43) and the first counter means (41). . 18. The method of claim 17, wherein the transmitting means (43) transmits a value of 1 / N times (N is an integer) of the count value of the first counter means (41) to the second counter means (42). Rectifier dc motors. 18. The non-commutator direct current according to claim 17, wherein the transmission means (43) transmits a value of 1/2 times the count value of the first counter means (41) to the second counter means (42). Electric motor. A plurality of stator windings 11, 12, 13, back electromotive force detection means 1 for obtaining a pulse signal string in response to back electromotive force induced in the stator winding selected by the plurality of phase selection signals, and a period of the pulse signal string are predetermined. Outputs a delayed pulse signal delaying the pulse signal string when in the range, and generates a delayed pulse signal and a pseudo output pulse signal having a delay amount different from the delayed pulse signal when the period of the pulse signal string exceeds a predetermined range. Pulse generating means (3), selection signal generating means (6) for outputting said plurality of phase selection signals in response to said delay pulse signal, and generating a plurality of phase pulse signals in response to said pulse signal sequence and said pseudo output pulse signal; Logic pulse generating means (2) and position signal formation for forming a plurality of position signals in response to a pulse signal output from said logic pulse generating means Means (4) and power supply means (5) for supplying power to the stator windings in response to the position signal. 25. The signal generator according to claim 24, wherein said position signal forming means (4) comprises: an inclined waveform signal generating means for generating an inclined waveform signal in response to a pulse signal of said back electromotive force detecting means (1) or said logic pulse generating means (2); 100 and signal forming means 101, 102, 103, 104, 105, 106 for forming a plurality of position signals in response to the pulse signal output from the logic pulse generating means. Rectifierless DC motor, characterized in that it comprises a. The pulse generating means (3) according to claim 24, wherein the pulse generating means (3) is delayed by a time proportional to the period of the pulse signal string when the period of the pulse signal string output from the counter electromotive force detecting means (1) is within a predetermined range. A rectifier DC motor, characterized in that for outputting a delay pulse signal. The pulse generating unit (3) according to claim 24, wherein the pulse generating unit (3) has a period of 1 / N times when the period of the pulse signal string output from the counter electromotive force detecting unit (1) is within a predetermined range. A non-commutator DC motor, characterized in that for outputting a delay pulse signal delayed by an integer). The pulse generating unit (3) according to claim 24, wherein the pulse generating unit (3) has a period of 1/2 times as long as the period of the pulse signal string output from the counter electromotive force detecting unit (1) is within a predetermined range. A non-commutator DC motor, characterized in that for outputting a delay pulse signal delayed by. The pulse generating means (3) according to claim 24, wherein the pulse generating means (3) is shorter than when the period is within a predetermined range when the period of the pulse signal string output from the counter electromotive force detecting means (1) exceeds a predetermined range. A rectifier-free DC motor, characterized in that for generating a delay pulse of the delay amount. The pulse generating means (3) according to claim 24, wherein the pulse generating means (3) comprises: a first counter means (41) for counting a period of the pulse signal string output from the counter electromotive force detecting means (1), and a count value of the first counter means; A transmission means 43 for transmitting to the second counter means 42, the second counter means 42 for outputting a delay pulse signal delayed by a time proportional to the period of the pulse signal string from the transmitted count value, and And a clock pulse generating means (44) for inputting a clock signal to the first and second counter means. 31. The non-commutator DC motor according to claim 30, wherein the clock signal frequency input to the second counter means (42) is different from the clock frequency input to the first counter means (41). 32. The clock signal frequency input to the second counter means 42 is a clock signal input to the first counter means when the count value of the first counter means 41 is within a predetermined range. A non-commutator DC motor, characterized in that it is an integer multiple of the frequency. 32. The clock signal frequency input to the second counter means 42 is a clock signal input to the first counter means when the count value of the first counter means 41 is within a predetermined range. A non-commutator DC motor, characterized in that twice the frequency. 31. The clock signal frequency input to the second counter means 42 is higher than when the count value is within a predetermined range when the count value of the first counter means 41 exceeds a predetermined range. A non-commutator DC motor, characterized in that large. 31. The clock signal frequency input to the second counter means 42, when the count value of the first counter means 41 exceeds a predetermined range, when the count value is within a predetermined range. A non-commutator DC motor, characterized in that the integer multiple of. The frequency of the clock signal input to the second counter means 42 is such that the count value is within a predetermined range when the count value of the first counter means 41 exceeds a predetermined range. A rectifier-free DC motor characterized by doubled the time. 31. The non-commutator DC motor according to claim 30, wherein the transmission means (43) differs from an initial value transmitted to the second counter means in response to a count value of the first counter means. 31. The transmission means (43) according to claim 30, wherein the transmission means (43) is 1 / N times the count value of the first counter means (41) when the count value of the first counter means (41) is within a predetermined range. Constant value) is transmitted to the second counter means (42). 31. The transmission means (43) according to claim 30, wherein the transmission means (43) has a value that is 1/2 of the count value of the first counter means (41) when the count value of the first counter means (41) is within a predetermined range. The non-commutator DC motor, characterized in that for transmitting to the second counter means (42). 31. The transmission means 43 according to claim 30, wherein the transmission means 43 initializes a value smaller than a value input when the count value is within a predetermined range when the count value of the first counter means 41 exceeds a predetermined range. The non-commutator direct current motor, characterized in that for transmitting to the second counter means (42). 31. The transmission means (43) according to claim 30, wherein the transmission means (43) is 1 / N times the value transmitted when the count value is within a predetermined range when the count value of the first counter means (41) exceeds a predetermined range. And a value of (N is an integer) as an initial value, to the second counter means (42). 31. The transmission means (43) according to claim 30, wherein the transmission means (43) is 1/2 times the value transmitted when the count value is within a predetermined range when the count value of the first counter means (41) exceeds a predetermined range. A non-commutator direct current motor, characterized in that for transmitting the value of as an initial value to the second counter means (42). 31. The method according to claim 30, wherein said transmission means (43) transmits a predetermined value to said second counter means (42) when the count value of said first counter means (41) exceeds a predetermined range. Rectifier dc motors. A plurality of stator windings 11, 12, 13, back electromotive force detecting means 1 for obtaining a pulse signal string in response to back electromotive force induced in the stator winding selected by the plurality of phase selection signals, and a period of the pulse signal string are predetermined. Outputs a delayed pulse signal delaying the pulse signal sequence when within the range; generates a pseudo output pulse signal when the period of the pulse signal sequence exceeds a predetermined range; and when the pseudo output signal continues for a predetermined number or more. A pulse generating means (3) for generating one or more different generation intervals, a selection signal generating means (6) for outputting said plurality of phase selection signals in response to said delay pulse signal, and said pseudo output signal and said pulse signal string A logic pulse generating means (2) for generating a plurality of phase pulse signals in response to the output, and a position signal in response to a pulse signal from said logic pulse generating means A non-direct current commutator motor, characterized in that comprising a position signal forming means (4), a power supply unit 5 in response to the position signal, supplies electric power to the stator windings to form. 45. The inclination waveform signal generating means according to claim 44, wherein said position signal forming means (4) generates an inclined waveform signal in response to a pulse signal of said back electromotive force detecting means (1) or said logic pulse generating means (2). (100) and signal forming means (101), (102), (103), (104), (105), (106) for forming a plurality of position signals in response to the pulse signal from the logic pulse generating means. Non-commutator DC motor, characterized in that provided with. The pulse generating means (3) according to claim 44, wherein the pulse generating means (3) is delayed by a time proportional to the period of the pulse signal string when the period of the pulse signal string output from the counter electromotive force detecting means (1) is within a predetermined range. A rectifier DC motor, characterized in that for outputting a delay pulse. The pulse generating means (3) according to claim 44, wherein when the period of the pulse signal string output from the counter electromotive force detecting means (1) is within a predetermined range, 1 / N times the period of the pulse signal string (N A non-commutator DC motor, characterized in that for outputting a delay pulse delayed by an integer). The pulse generating means (3) according to claim 44, wherein the pulse generating means (3) has a time that is 1/2 times the period of the pulse signal string when the period of the pulse signal string output from the counter electromotive force detecting means (1) is within a predetermined range. A rectifier-free DC motor, characterized in that for outputting a delayed pulse delayed by. The pulse generating means (3) according to claim 44, wherein the pulse generating means (3) generates a pseudo output signal of a predetermined period by a predetermined coefficient when the period of the pulse signal string output from the counter electromotive force detecting means (1) exceeds a predetermined range. And then outputting a pseudo output signal of a shorter period than the said cycle continuously. The pulse generating means (3) according to claim 44, wherein the pulse generating means (3) outputs a pseudo output signal of a predetermined period when the period of the pulse signal string output from the counter electromotive force detecting means (1) exceeds a predetermined range. And a rectifier output pulse having a period of 1 / N times the constant period (N is an integer) continuously. The pulse generating means (3) according to claim 44, wherein said pulse generating means (3) comprises: a first counter means (41) for counting a period of said pulse signal string output from said back electromotive force detecting means (1), and said first counter means (41); A transmission unit 43 for transmitting a count value of? To the second counter means 42; a second counter means 42 for outputting a delay pulse signal delayed by a time proportional to a period of the pulse signal sequence from the transmitted count value; And a clock pulse generating means (44) for inputting a clock signal to the first and second counter means. 52. The non-commutator DC motor according to claim 51, wherein the clock signal frequency input to the second counter means (42) is different from the clock signal frequency input to the first counter means (41). The non-commutator DC motor according to claim 51, wherein the clock signal frequency input to said second counter means (42) is an integer multiple of the clock signal frequency input to said first counter means (41). A non-commutator DC motor according to claim 51, wherein the clock signal frequency input to said second counter means (42) is twice the clock signal frequency input to said first counter means (41). 52. The non-commutator DC motor according to claim 51, wherein said transmission means (43) differs from an initial value transmitted to said second counter means (42) in response to a count of said first counter means (41). . The transmission means (43) according to claim 51, wherein the transmission means (43) transmits a value of 1 / N times (N is an integer) to the second counter means (42) of the count value of the first counter means (41). A rectifier-free DC motor characterized by. 52. The non-commutator direct current according to claim 51, wherein said transmission means (43) transmits a value of 1/2 times the count value of said first counter means (41) to said second counter means (42). Electric motor.