JP2910229B2 - Commutatorless DC motor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a commutatorless DC motor, and more particularly, to a commutatorless motor which does not require a position detecting element such as a Hall element for detecting a rotational position of a permanent magnet rotor. The present invention relates to a child DC motor.

2. Description of the Related Art A commutatorless DC motor has no mechanical contact compared to a DC motor with a brush, so it has a long life and little electrical noise.In recent years, industrial equipment and video / Widely applied to audio equipment.

Conventionally, most of the non-commutator DC motors of this type use a rotor position detecting element (for example, a Hall element) corresponding to a brush for switching an energized phase of a stator winding. However, the position detecting element itself is not at all inexpensive, and further, due to the complexity of adjusting the mounting position of the element and the increase in the number of wirings, there is a disadvantage that the cost of the non-commutator DC motor is significantly increased compared to the DC motor with a brush. .

In addition, since a position detecting element must be mounted inside the electric motor, structural restrictions often occur. In recent years, electric motors used have become smaller and thinner with the downsizing of devices, and there is no room for mounting a position detecting element such as a Hall element.

Therefore, some commutatorless DC motors without a position detecting element such as a Hall element have been proposed.

For example, there is a so-called half-wave drive type non-commutator DC motor that supplies a current to a stator winding in only one direction, as disclosed in Japanese Patent Application Laid-Open No. 55-160980. This means that at start-up, only a particular stator winding phase is energized by a starting circuit to pre-position the rotor, and then induced in two of the three-phase stator windings at rest. The detected back electromotive force is detected, and the detected signal is subjected to arithmetic processing to determine the next energized phase, and the current is sequentially supplied to the stator winding in only one direction.

Further, there is a so-called full-wave drive type non-commutator DC motor for supplying a current to a stator winding in both directions, as disclosed in, for example, Japanese Patent Application Laid-Open No. 62-260586. This is because when the motor is started, the current flowing through the stator winding is forcibly switched and driven by the starting pulse output from the starting pulse generating circuit, and the rotation of the rotor increases, and the back electromotive force is applied to the stator winding. When induced, the zero cross point of the back electromotive force is detected, and the output signal is delayed by a fixed time in a mono-multi to determine the energization timing.

Hereinafter, the driving waveform of the conventional example will be described with reference to FIGS. 2 and 3. FIG.

FIG. 2 is a circuit configuration diagram showing an embodiment of a power supply means constituting a non-commutator DC motor, and FIG. 3 is a signal waveform diagram of each part in a conventional example.

In FIG. 2, 27 is a permanent magnet rotor, 11, 12, and 13 are stator windings, and 21, 22, 23, 24, 25, and 26 are driving transistors, and these transistors are turned on and off. A current is supplied to the stator windings 11, 12, and 13. Of which 21,2
2, 23 are PNP transistors, and 24, 25, 26 are NPN transistors. 20 is a power supply. Generally, the drive of a commutatorless DC motor is performed by driving a six-phase pulse signal obtained in accordance with the rotational position of the permanent magnet rotor 27 with drive transistors 21, 26,
This is performed by applying to each base of 22, 24, 23, and 25. The waveforms of the six-phase pulse signals are shown in FIGS. However, the direction of the signal applied to the base of each transistor is applied in the direction in which current flows out to the PNP transistors 21, 22, and 23, and in the direction in which current flows in the NPN transistors 24, 25, and 26. First, the transistors 21 and 25 conduct and the stator windings 11 and 25
Current flows through 12. Next, the transistors 21 and 26 become conductive, and current flows through the stator windings 11 and 13. Such a phase switching operation is sequentially performed to rotate the permanent magnet rotor 27. At this time, currents shown in FIG. 3, j, k, and l are applied to the stator windings 11, 12, and 13 in both directions. Further, when the permanent magnet rotor 27 is rotating, the voltages (back electromotive force) shown in FIGS. 3a, 3b, and 3c are induced at the terminals of the stator windings 11, 12, and 13. The six-phase pulse signals d, e, f, g, h, and i correspond to the rotational position signals of the permanent magnet rotor 27, and the waveforms of the back electromotive forces a, b, and c have the phases shown in FIG. It should be noted that the phases are different by 30 degrees in electrical angle. For example, in Japanese Patent Application Laid-Open No. 62-260586, the zero-cross point of the back electromotive force induced in the stator winding is detected, and the output signal is delayed by a certain time by using a mono-multi to determine the energization timing. doing. In addition, since the six-phase rotational position signals d, e, f, g, h, and i have a rectangular waveform, the current waveform flowing through the stator winding also has a rectangular waveform with a conduction width of approximately 120 degrees (electrical angle). The current flowing through the stator winding is rapidly turned on and off.

Problems to be Solved by the Invention A commutatorless DC motor without a position detecting element basically utilizes a back electromotive force induced in a stator winding to rotate the stator winding in a phase required for phase switching. Creating a position signal.
However, since the rotor is stationary at the time of starting, no back electromotive force is generated in each stator winding. Therefore, in the commutatorless DC motor shown in the above-mentioned prior art, a special starting circuit is provided for starting.
In JP-A-160980, the initial position of the rotor is determined in advance by energizing only a specific stator winding. However, even if only one phase of the stator winding is energized to determine the initial position, the position of the rotor becomes oscillating and does not stand still, resulting in a long start-up time.

In JP-A-62-260586, the stator windings are forcibly switched sequentially by an output pulse generated by a starting circuit. However, even if the stator windings are forcibly switched one after another, the rotation of the rotor also becomes vibratory. Therefore, even if the detection circuit can successfully detect the zero cross point of the back electromotive force,
It is difficult to properly switch from the start mode in which the stator windings are forcibly switched and driven sequentially to the normal position effect mode in which the zero cross point of the back electromotive force is detected. That is, the timing of switching from the start mode to the normal position detection mode is difficult, and as a result, the start time of the motor is lengthened. Generally, these commutatorless DC motors without the rotor position detecting element do not generate back electromotive force in each stator winding because the rotor is stationary at the time of startup. For this reason, there is a problem that the initial energizing phase is not determined, and the startability is remarkably inferior to a motor having a position detecting element.

Furthermore, these commutatorless DC motors without position detecting elements are considered to be a kind of synchronous motor because phase switching is forcibly performed at the time of startup, and the phase switching frequency suitable for startup is determined by the magnitude of the load applied to the motor. It varies greatly due to the inertia of the pod rotor. In some cases, the zero cross point of the back electromotive force induced in the stator winding cannot be detected forever, and the zero cross point of the back electromotive force is detected from the start mode in which the stator windings are sequentially switched and driven. However, there is a problem that it is difficult to shift to the normal position detection mode.

Furthermore, the former non-commutator DC motor shown in the prior art is a half-wave drive system in which current is supplied to only one direction of the stator winding, so that the drive circuit can be easily configured, but the fixed circuit is fixed. As compared with a full-wave drive type motor in which the current flowing in the child winding flows in both directions, there is a problem that the utilization ratio of the stator winding is low, the efficiency is low, and the generated torque is small.

Also, in the latter non-commutator DC motor shown in the prior art, the pulse generated at the zero cross point of the back electromotive force induced in the stator winding is energized by delaying the pulse by a mono-multi for a fixed time. This is a method of determining the phase, and its delay time is constant irrespective of the rotation speed of the electric motor. Therefore, there is a problem that it is not suitable for applications requiring a change in the rotation speed and has poor applicability.

Further, in the commutatorless DC motors shown in both prior arts, the drive current flowing through the stator winding
It becomes a rectangular wave of 0 degree (electrical angle). Therefore, a filter including a relatively large capacitor is actually required for the current-carrying terminal of the stator winding in order to reduce a spike-like voltage accompanying the switching. In addition, since the current flowing through the stator winding is rapidly turned on and off, there is a disadvantage that vibration and noise are easily generated during rotation, and the tendency is more remarkable as the motor is used at higher speeds. There is.

In view of the above problems, the present invention provides a non-commutator DC motor that does not require a rotor position detection element and that can obtain good startup characteristics without providing a special startup circuit. It is intended to be.

A further object of the present invention is to provide a full-wave drive type non-commutator DC motor configured to flow a current flowing through a stator winding in both directions.

Still another object of the present invention is to provide a commutatorless DC motor capable of arbitrarily changing the rotation speed of the motor.

Further, the present invention provides a non-commutator DC motor which does not need a filter circuit including a large capacitor as required for the non-commutator DC motor shown in the prior art, and has very little vibration and noise even at high speed rotation. It is intended to be.

Means for Solving the Problems In order to achieve the above object, the present invention detects a zero cross point of a back electromotive force generated in each of a plurality of phase stator windings according to a selection signal output from a selection signal generating means. Back electromotive force detection means for generating a pulse signal train, and the pulse signal train is inputted, and the cycle of the pulse signal train is counted, and when the cycle is below a predetermined value, it is proportional to the counted cycle or A delay pulse obtained by delaying the pulse signal train by a substantially proportional time is output to the selection signal generation means, and when the period of the pulse signal train exceeds a predetermined value, the delay pulse is output to the selection signal generation means. Pulse generating means for outputting to the logic pulse generating means a pseudo output pulse in which pulses of two types of cycles alternately appear for a predetermined time, and output from the back electromotive force detecting means. Logic pulse generating means for dividing the input pulse signal train or the pseudo output pulse output from the pulse generating means to generate a multi-phase pulse signal having the same frequency as the counter electromotive force of the stator winding; The detection timing of the zero-cross point of the back electromotive force and the stator winding to be detected are determined based on the plurality of pulse signals output by the logic pulse generation means and the delay pulse output from the pulse generation means. Selection signal generation means for outputting a selection signal to be output, position signal synthesis means for synthesizing a position signal synchronized with the pulse signal output from the logical pulse generation means, and power to the stator winding based on the position signal. Power supply means for supplying.

The pulse generation means includes a clock pulse generation circuit and a counter for counting clock pulses output from the clock pulse generation circuit, and counts a period of the pulse signal train output from the back electromotive force detection means. When the cycle exceeds a predetermined value, a pulse longer than a cycle determined based on the count value of the counter and a pulse shorter than the cycle are alternately generated for a predetermined time. I have.

Operation According to the present invention, the zero cross point of the back electromotive force induced in the stator winding is shaped and converted into a pulse signal train by the configuration described above. Since the period of the pulse signal train is counted and the rotational position signal is created according to the period, the energizing phase of the stator winding to be energized next changes even if the rotational speed of the motor changes. There is no. Moreover, since a selection circuit is added to convert only the back electromotive force of the next phase to be detected from the energized state of the stator winding to a pulse signal train, the phase due to erroneous detection of the zero cross point of the back electromotive force is Stable driving can always be obtained without erroneous switching.

Therefore, it can be easily applied to applications where the rotation speed needs to be changed, and the drive is performed when the rotation speed is changed as seen in the conventional non-commutator DC motor that does not require the rotor position detecting element. Is not unstable.

In addition, the present invention can easily output a pseudo output pulse at the time of starting without providing a special starting circuit for starting, and the pseudo output pulse forcibly sequentially turns the stator windings. Switching. When the back electromotive force detection means detects the zero cross point of the back electromotive force, the normal position detection is performed by detecting the zero cross point of the back electromotive force from the start mode in which the stator windings are forcibly sequentially switched and driven. The mode can be quickly shifted to, and a starting characteristic comparable to a conventional motor with a position detecting element can be obtained.

In addition, since the present invention detects only the zero-cross point of the back electromotive force induced in the stator winding, the current flowing through the stator winding in both directions is not affected by the voltage drop due to the driving current. It is possible to adopt a configuration of a full-wave drive type electric motor that can flow through the motor. Therefore, a non-commutator DC motor with higher efficiency and higher torque than a half-wave drive motor can be provided.

In addition, since the phase switching of the current applied to each phase of the stator winding is performed extremely smoothly, a relatively large capacitor for reducing a spike-like voltage associated with the phase switching as seen in the conventional example. It is not necessary to connect the filter circuit including to the current-carrying terminal of the stator winding.

Further, since the phase switching is performed smoothly without the current flowing through the stator winding being turned on / off sharply as in the conventional example, it is possible to drive the electric motor with very little vibration and noise.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a commutatorless DC motor according to one embodiment of the present invention. In FIG. 1, 1
Is a back electromotive force detecting means to which the back electromotive force induced in the three-phase stator windings 11, 12, 13 and the selection signal output from the selection signal generating means 6 are input. The back electromotive force detecting means 1 detects a zero-cross point of the three-phase back electromotive force in accordance with the selection signal output from the selection signal generating means 6 and converts it into a pulse train m. This pulse train indicates a zero-cross point of the three-phase back electromotive force. The pulse train m output from the back electromotive force detecting means 1 is input to the logical pulse generating means 2 and the pulse generating means 3. The logic pulse generating means 2 divides the frequency of the pulse train m output from the back electromotive force detecting means 1 and outputs six-phase pulses having the same frequency as the back electromotive force induced in the stator windings 11, 12, and 13. The pulse generator 3 first counts the period m of the input pulse train. Then, the output pulse is delayed by approximately half the counted cycle and output to the selection signal generating means 6 as a delayed pulse z.
When the counted cycle exceeds a predetermined value, a pseudo output pulse t is output to the logic pulse generating means 2. The six-phase pulse signal generated by the logical pulse generating means 2 is input to the position signal synthesizing means 4 and converted into a rotation position signal of the permanent magnet rotor 27 based on the six-phase pulse signal. This rotation position signal is input to the stator winding power supply means 5. The stator winding power supply means 5 sequentially supplies a drive current to each of the stator windings 11, 12, 13 in both directions according to the rotational position signal output from the position signal synthesizing means 4.

The operation of the commutatorless DC motor of the present invention will be described in detail based on the embodiment configured as described above.

FIG. 4 is a signal waveform diagram of each part of one embodiment of the power supply means 5 constituting the non-commutator DC motor of the present invention.

In FIG. 4, a, b, and c are stator windings 11, 12, 1 respectively.
3 is a back electromotive force waveform induced in FIG. d, e, f, g, h, and i are six-phase signals synthesized by the position signal synthesizing means 4 and correspond to six-phase rotational position signals obtained according to the rotational position of the permanent magnet rotor 27. This is a trapezoidal signal waveform, unlike the rectangular signal waveforms shown in FIGS. 3d, e, f, g, h, and i of the conventional example.

The six-phase rotational position signals shown in FIGS. 4d to 4i are input to the respective bases of the driving transistors 21, 26, 22, 24, 23 and 25, respectively. However, the direction of the signal applied to the base of each transistor is applied in the direction in which current flows out to the PNP transistors 21, 22, and 23, and in the direction in which current flows in the NPN transistors 24, 25, and 26. Each transistor amplifies the applied base current and a current proportional to each base current flows to each collector. As a result, the currents shown in FIG. 4, j, k, and l are applied to the stator windings 11, 12, and 13 in both directions. Such a phase switching operation is sequentially performed to rotate the permanent magnet rotor 27.

The operation of each unit of the embodiment of the present invention that performs such signal processing will be further described with reference to the drawings.

FIG. 5 is a circuit diagram of the back electromotive force detecting means 1 in one embodiment of the present invention shown in FIG.

In FIG. 5, reference numerals 14, 15, and 16 denote resistors, one of which is connected to each terminal of the stator windings 11, 12, and 13, and the other of which is commonly connected. 31, 32 and 33 are comparison circuits, whose input terminals (+) are connected to the terminals of the stator windings 11, 12, and 13, respectively, and whose input terminals (-) are commonly connected to resistors 14, 15, and 16. Points are connected. 34, 35 and 36 are inverter circuits, each of which is a comparator.
31, 32, and 33 outputs are connected. 71,72,73,74,75,7
6 is a switch, of which one of the switches 71, 73, 75 is connected to each output of the inverter circuits 36, 34, 35, respectively, and one of the switches 72, 74, 76 is connected to each output of the comparison circuits 32, 33, 31. Each is connected. The other of the switches 71, 72, 73, 74, 75, 76 is commonly connected, and serves as an output terminal of the back electromotive force detection means 1.

The operation of the back electromotive force detecting means 1 shown in FIG.
This will be described with reference to the drawings.

The resistors 14, 15, 16 shown in FIG.
Since they are connected to the resistors 2, 13, the same potential as the neutral point o of the stator windings 11, 12, 13 is obtained at the common connection point of the resistors 14, 15, 16. Therefore, it is not necessary for the motor to draw a signal line from the neutral point of the stator winding. The back electromotive forces induced in the stator windings 11, 12, and 13 are shown in FIGS.
The signal waveforms shown in b and c are input to the input terminals (+) of the comparators 31, 32 and 33 in FIG. The neutral point potential of the stator winding obtained at the common connection point is input. Therefore, at each output terminal of the comparators 31, 32, and 33, a pulse obtained by shaping the back electromotive force a, b, and c as shown in FIGS. The pulse edges of the pulse waveforms u, v, w coincide with the zero cross points of the back electromotive forces a, b, c, respectively. Fig. 6 t1, t2, t3, t4, t5, t6
Is a six-phase signal output from the selection signal generation means 6 to the back electromotive force detection means 1, and its rising edge has back electromotive forces a,
The timing of the zero cross point of b and c and the selection signal waveform delayed by 30 degrees in electrical angle are shown. The switches 71, 72, 73, 74, 75 and 76 are switched on by the signal "H" and switched off by the signal "L" by these selection signals. As a result, the waveform shown in FIG. 6m is obtained from the common connection point of the switches 71, 72, 73, 74, 75 and 76, and the zero-cross points of the three-phase back electromotive forces a, b and c and the rising edge of the pulse Is output. That is, a pulse is output at each zero cross point of the back electromotive forces a, b, and c, and 6
A pulse train m for each time (every 60 electrical degrees) is output.

Next, the operation of the pulse generating means 3 in one embodiment of the present invention will be described in detail.

FIG. 7 is a circuit configuration diagram of the pulse generating means 3 in one embodiment of the present invention shown in FIG. 1, FIG. 8 is a signal waveform diagram of each part at the time of steady rotation of the motor, and FIG. It is a signal waveform diagram.

In FIG. 7, 41 is the first counting means, and 42 is the second counting means.
Is a clock pulse generating circuit.
The clock pulse generation circuit 44 has two types of clock pulses c.
k, 2ck are generated, the clock pulse of ck is input to the first counting means 41, and the clock pulse of 2ck (the clock frequency is twice ck) is input to the second counting means 42. The first counting means 41 outputs the most significant bit output d2 and the middle bit output d1. Bit output d
1, d2 are input to the data selector 45. The second count means 42 outputs a zero flag z when the count value becomes zero. The data selector 45 selects one of the two types of bit outputs d1 and d2 according to the input selection signal c3 and outputs the selected bit output as a pulse t. Reference numeral 43 denotes a transfer circuit to which a pulse train m output from the back electromotive force detection means 1 and a pulse t output from the data selector 45 are input, and a first counting means 41 receives a reset pulse r for resetting its count value, The second counting means 42 outputs a load pulse s for loading the count value of the first counting means 41. Reference numeral 46 denotes third counting means for counting the number of pulses t output from the data selector 45. Reference numeral 47 denotes an AND circuit. When two types of bit outputs c2 and c3 of the third counting means 46 are input and both the bits c2 and c3 are in the "H" state, the AND circuit 47 outputs the "H" signal QC. Output. The pulse QC is a reset pulse of the third counting means 46,
Of the counting means 46 is reset. The second
The zero flag z output from the counting means 42 corresponds to the delay pulse z input to the selection signal generating means 6, and the pulse t output from the data selector 45 corresponds to the pseudo output pulse t input to the logical pulse generating means 3. I do.

The operation of the pulse generating means 3 shown in FIG. 7 will be described first with reference to FIG. 8 when the motor is rotating normally.

The first counting means 41 counts up the clock pulse ck until the reset pulse r output from the transfer circuit 43 is input. Since the reset pulse r has the same cycle as the pulse train m output from the back electromotive force generating means 1, the count value of the first counting means 41 is determined by counting the cycle of the pulse train m output from the back electromotive force detecting means 1. Become. FIG. 8p shows the count value in an analog manner. When the motor is rotating normally, the cycle of the reset pulse r is sufficiently short, and the two bit outputs d of the first counting means 41 are set.
1 and d2 never go to the “H” state. Note that the two levels d1 and d2 indicated by the dotted lines in FIG. 8p indicate the count values of the first counter means 41 in which the bit outputs d1 and d2 each become the "H" state. Therefore, the pseudo output pulse t is not output from the data selector 45 as shown at t in FIG. The second counting means 42 receives the first counting means 41 at the timing of the load pulse s output from the transfer circuit 43.
Is transferred as an initial value. The second counting means 42 counts down the count value p obtained by counting the cycle of the pulse train m with a 2ck clock, so that the load pulse s
The count value becomes zero at exactly the middle point of the pulse train (or the rising edge of the pulse m). Fig. 8 q
Is shown in analog form. Since the second counting means 42 is configured to output a zero flag when the count value is zero, the second counting means 42 outputs a pulse z as shown in FIG. 8z. The rising edge of the pulse train m output from the back electromotive force detecting means 1 is a three-phase stator winding.
Since it indicates the zero cross point of the back electromotive forces a, b, and c induced in 11, 12, and 13, the pulse interval is equivalent to 60 electrical degrees. Therefore, the rising edge of z shown in FIG. 8 is delayed by exactly 30 electrical degrees from the zero-cross point of the back electromotive forces a, b, and c. Is output to In addition,
The phase relationship between the load pulse s and the reset pulse r is as shown in FIG. 8, and the reason why the reset pulse r is delayed from the load pulse s is that the count value of the first count means 41 is This is to ensure the transfer.
Although the pulse widths of the pulses s and r are shown large for the sake of convenience in the figure, they are assumed to be sufficiently narrower than the pulse period.

Next, the operation at the time of starting the electric motor will be described with reference to FIG. The first counting means 41 counts up the clock pulse ck until the reset pulse r output from the transfer circuit 43 is input. However, since the rotor is stationary, the back electromotive force generating means 1 does not output the pulse train m. Accordingly, the count value of the first counting means 41 monotonically increases as shown in FIG. 9p, and when the count value reaches a predetermined value (shown by a dotted line in FIG. 9p), the first count value Bit outputs d1 and d2 are output from the means 41, and t is output to the transfer means 43 via the data selector 45. The transfer means 43 receives the pulse t and outputs a reset pulse r and a load pulse s. The second counting means 42 counts down after the initial value is loaded by the load pulse s. When the count value of the second counting means 42 becomes zero, the zero flag z is output as a delay pulse. When the motor is started, the pulse train m is not output from the back electromotive force detection means 1, so that the pulse t is continuously output from the data selector 45. Initially, the data selector 45 is the first
The bit output d2 of the counting means 41 is selected as the pulse t, and the number of pulses is counted by the third counting means 46. Now, assuming that the third counting means 46 is constituted by a 3-bit counter, the counting state is shown in FIGS. 9 c1, c2 and c3. Third counting means
46 sequentially counts the pulse t, and the output of c2 and c3 is "H"
When the state (pulse t is counted six times) is reached, the output qc of the AND circuit 47 becomes the "H" state. Then, qc is input to the third counting means 46 to reset the count value. Or later,
The above operation is repeated until the motor rotates and the pulse m is output from the back electromotive force detection means 1. However, the third
The output c3 of the counting means 46 is also used as a selection signal of the data selector 45, and as shown in FIG. Then, the data selector 45 selects the bit output d1 of the first counting means 41 as the pulse t. Since d1 is an intermediate bit of the first counting means 41, as shown in FIG. 9p, the count value of the first counting means is shorter than the time when the data selector 45 has selected d2. The second counting means 42 is loaded. Since the second counting means 42 counts down after the initial value is loaded by the load pulse s, the count value q of the second counting means 42 becomes zero in a shorter time, and the delay pulse z having a short cycle becomes shorter. Is output. As a result, four relatively long-period pulses z and two shorter-period pulses z
The pulse z is output repeatedly. Fig. 9 shows the situation.
Shown in q and z.

As apparent from the above description, the pulse m is not output from the back electromotive force detecting means 1 at the time of starting the motor,
Instead, the output t of the data selector 45 is input to the transfer circuit 43 as a pseudo output pulse serving as a substitute.

Thereafter, a delay pulse z as shown in FIG. 9z is output from the second counting means 42 in the same operation as in the steady state of FIG. The delay pulse z obtained by the pulse generator 3 is applied to the selection signal generator 6, and the pseudo output pulse t is applied to the logic pulse generator 6.

FIG. 10 is a circuit configuration diagram of another embodiment of the pulse generating means 3 in one embodiment of the present invention shown in FIG. 1, FIG. 12 is a signal waveform diagram of each part during steady rotation of the motor, and FIG. FIG. 4 is a signal waveform diagram of each part at the time of startup.

Components having the same functions as those in FIG. 7 are denoted by the same reference numerals, and redundant description will be omitted.

In FIG. 10, 41 is the first counting means, and 42 is the second counting means.
The first counting means 41 is composed of an 8-bit digital counter, and the second counting means 42 is composed of a 7-bit digital counter. The same clock ck is input to the first counting means 41 and the second counting means 42, respectively. The first counting means 41 counts up the clock ck, and the second counting means 42 counts down the clock ck. Reference numeral 48 denotes a switch transfer circuit composed of seven switches. The switch transfer circuit is connected to the contact for a short time only by the load pulse s of the transfer means 43, and the bits (excluding the least significant bit) of the count value of the first count means 41 In the example of Figure 10, it is 7
Are transferred to the second counting means 42.

The operation of the pulse generating means shown in FIG. 10 will be described first with reference to FIG. 11 when the permanent magnet rotor 27 is rotating normally.

The count value p of the first counting means 41 is transferred to the second counting means 42 at the timing of the load pulse s output from the transferring means 43. However, since only the least significant bit of the first counting means 41 is discarded and transferred to the second counting means 42, as shown in FIG. 11q, the initial value of the second counting means 42 is The count value p of the counting means 41 of 1
Will be given as the initial value. Second
The counting means 42 counts down p / 2 corresponding to half of the count value obtained by counting the period of the pulse train s by the clock ck, so that the count value becomes zero at exactly the middle point of the pulse train s. Accordingly, the second counting means 42 outputs a delay pulse z as shown in FIG. Therefore, the rising edge of z shown in FIG.
This means that the signal is delayed by exactly 30 electrical degrees from the zero-cross point of c.

Next, the operation at the time of starting the electric motor will be described with reference to FIG. Since the back electromotive force detecting means 1 does not output the pulse train m at the time of starting, the first counting means 41 keeps counting up the clock pulse ck. Therefore,
The count value of the first count means 41 monotonically increases as shown in FIG. 12p, and when the count value reaches a predetermined value (shown by a dotted line in FIG. 12p), the first count means 41 Bit outputs d1 and d2 are output from 41, and t is output to the transfer means 43 via the data selector 45. The transfer means 43 outputs the signal t
In response, the reset pulse r and the load pulse s are output. When the transfer means 43 receives the signal t, the value of p / 2 (upper 7 bits) which is half of the count value of the first count means 41 is transferred to the second count means 42 as an initial value as it is. , Is counted down. When the count value of the second counting means 42 becomes zero, the zero flag z is output as a delay pulse. Although the frequency of the clock supplied to the first and second counting means is different in the embodiment of FIG. 7, the embodiment of FIG. 10 has the advantage that only one kind of clock is required.

FIG. 13 is a circuit configuration diagram of the logic pulse generating means 2 in one embodiment of the present invention shown in FIG. 1, and a signal waveform diagram of each part thereof is shown in FIG.

In FIG. 13, reference numeral 82 denotes a two-input OR circuit to which a pulse train m of the back electromotive force detecting means 1 and a pseudo output pulse t of the pulse generating means 3 are inputted. 81 is a 6-phase ring counter,
The output of the OR circuit 81 is input, and the sixteenth output terminal
It outputs six-phase pulse signals of p1, p2, p3, p4, p5, and p6 shown in the figure. The pulse width of these pulse signals is 60 degrees in electrical angle. These six-phase pulse signals p1 to p6 are output to the position signal synthesizing means 4 and the selection signal generating means 6 in FIG.

FIG. 15 is a circuit configuration diagram of the selection signal generating means 6 in one embodiment of the present invention shown in FIG. 1, and a signal waveform diagram of each part thereof is also shown in FIG.

In FIG. 15, reference numerals 91, 92, 93, 94, 95, and 96 denote D flip-flops. A delay pulse z output from the pulse generation means 3 is input to each clock terminal C, and a logical pulse is input to each D input terminal. The six-phase pulse signals p1 to p6 output by the generation means 2 are input. As a result, from the Q output terminals of the D flip-flop, the six-phase pulse signals p1 to
The six-phase signals t1 to t6 are output by delaying p6 by the pulse width of the delay pulse z. The situation is shown in FIGS. These six-phase pulse signals t1 to t6 become the six-phase selection signals shown in FIG. 6, and have a pulse width of 60 degrees in electrical angle and are output to the back electromotive force detecting means 1.

FIG. 16 is a circuit configuration diagram of the position signal synthesizing means 4 in one embodiment of the present invention shown in FIG. 1, and FIG. 17 shows a signal waveform diagram of each part.

In FIG. 16, reference numeral 50 denotes a reset switch for discharging the electric charge stored in the charging / discharging capacitor 51, and reference numeral 51 denotes a charging / discharging capacitor for generating a sawtooth wave according to the output of the logic pulse generating means 2. , 52 is a charge / discharge capacitor
A constant current source circuit for supplying a charging current to 51, and a buffer amplifier 54 having an input connected to the capacitor 51. The capacitor 51, the switch 50, the constant current source circuit 52, and the buffer amplifier 54 constitute the sawtooth wave generating means 100. Reference numeral 55 denotes a buffer amplifier, whose input is connected to a reference voltage source 53. Reference numeral 56 denotes an inverting amplifier to which the outputs of the buffer amplifier 54 and the buffer amplifier 55 are connected. Outputs of the buffer amplifier 54, the buffer amplifier 55, and the inverting amplifier 56 are connected to signal combining means 101, 102, 103, 104, 105, and 106, respectively. Since the signal synthesizing units 101, 102, 103, 104, 105, and 106 have the same configuration, only the configuration of the signal synthesizing unit 101 is shown. In the signal synthesizing means 101, switches 61, 62 and 63 are switches, one of which is connected to the buffer amplifiers 54 and 55 and the inverting amplifier 56, respectively, and the other of the switches 61, 62 and 63 is commonly connected and connected to the resistor 64. . The voltage signal obtained by the resistor 64 is converted into a current signal by the current conversion circuit 65,
This is the output of the signal combining means 101.

Next, the operation of the position signal synthesizing means 4 shown in FIG. 16 will be described with reference to signal waveform charts of respective parts in FIG.

When the switch 50 of the sawtooth wave generating means 100 is open, a constant current is supplied to the capacitor 51 by the constant current circuit 52, and when the switch 50 is closed, the electric charge stored in the capacitor 51 is discharged instantaneously. . However, switch 50
Is configured to close for a short time at the rising edge of the pulse m output from the back electromotive force detection means 1,
The electric charge stored in the capacitor 51 is instantaneously discharged at the rising edge of the pulse m, and a sawtooth wave having the same phase as the pulse m as shown in FIG. FIG. 17 sf shows the waveform of the reference voltage source 53, the magnitude of which is set equal to the peak value of the sawtooth wave st. 17th
FIG. Stb is a waveform showing the output of the inverting amplifier 56. The inverting amplifier 56 has the output st of the buffer amplifier 54 and the
Since the output sf is input, st is connected with reference to sf.
Thus, a signal obtained by inverting st is obtained as shown in FIG. The switches 61, 62, 63 constituting the signal synthesizing means 101 are switched on by a signal "H" and switched off by a signal "L" according to the pulse signals p1, p2, p3 output from the logical pulse generating means 2. Therefore, the outputs of the buffer amplifiers 54 and 55 and the inverting amplifier 56 are combined by the signal combining means 101. Note that, when p1, p2, and p3 are all “L”, the switches 61, 62, and 63 are all turned off, and the potential of the resistor 64 becomes equal to the ground potential. The combined voltage value obtained in the resistor 64 in this way is
Is converted into a current value (current sink) by the output terminal d.
Outputs the rotational position signal waveform shown in FIG. 17d.

Hereinafter, similarly, the signal synthesizing means 102, 103, 104, 105, 106
Pulse signals (p2, p3, p4), (p3, p
4, p5), (p4, p5, p6), (p5, p6, p1), and (p6, p1, p2) output rotational position signals e, f, g, h, i. However,
Each output e, g, i of the signal synthesizing means 102, 104, 106 is an output of the current source type, and each output f, h of the signal synthesizing means 103, 105 is an output of the current sink type same as the output d of the signal synthesizing means 101. The signals shown in FIGS. 17D to 17I become the rotational position signals of the permanent magnet rotor 27 and are input to the power supply means 5 shown in FIG.

As described above, in one embodiment of the pulse generating means 3 constituting the present invention at the time of starting the motor, the pseudo output pulse t output at the time of starting the motor has four relatively long pulses and a shorter period than that. Two pulses are repeatedly output.

FIG. 18 and FIG. 19 are conceptual diagrams showing a method of starting the electric motor according to one embodiment of the pulse generating means 3 shown in FIG.

FIG. 18 shows the combined current vector of the motor and the permanent magnet rotor 27 when the pseudo output pulse t having a constant period is tentatively supplied to the logical pulse generating means 2 when the motor is started.
(A vector Φ indicating the position of the N pole of the permanent magnet rotor 27 in FIG. 2).
The position indicated by the dotted line in FIG. 18 indicates the zero-cross point detection position to be detected next to the back electromotive force, which is selected by the selection signal output from the selection signal generating means 6.
That is, the back electromotive force detecting means 1 detects the zero cross point of the back electromotive force when the magnetic pole vector Φ of the permanent magnet rotor 27 passes through the dotted line shown in FIG. 18th
As is apparent from the figure, the detection position of the zero-cross point of the back electromotive force also changes stepwise by 60 degrees according to the output of the selection signal generating means 6. However, at this time, the magnetic pole vector Φ of the permanent magnet rotor 27 is already at a position beyond the detection position of the zero cross point of the back electromotive force, and the back electromotive force detection means 1 cannot detect the zero cross point forever. Therefore, it is difficult to shift to the normal position detection mode in which the zero cross point of the back electromotive force is detected, and the motor is not accelerated.

FIG. 19 shows the pulse generator 3 when starting the motor.
The current vector of the electric motor when four relatively long pulses t outputted from the motor and two pulses t having a relatively short period are supplied to the logical pulse generating means 2 and the permanent magnet rotor 27 This shows the positional relationship of the magnetic pole vector Φ. The position indicated by the dotted line in FIG. 19 is selected by the selection signal of the selection signal generating means 6 as in FIG.
It shows the detection position of the zero cross point of the back electromotive force. Since a pseudo output pulse t having a constant period is supplied to the logic pulse generating means 2 from the start of the activation to the fourth pulse, FIGS. 19 (a), (b), (c) and (d) show the 18th pulse. It matches each of the figures. However, since the periods of the fifth and sixth pseudo output pulses t are shorter than the first four pulses,
The energized phase is switched until the permanent magnet rotor 27 rotates to the position shown in FIG. 18 (e). This is shown in FIG. 19 (e). As is clear from FIG. 19 (e), the position of the permanent magnet rotor 27 is at a position delayed with respect to the rotation direction as compared with FIG. 18 (e). Further, the sixth short-period pseudo-output pulse t causes the permanent magnet rotor 27 to be located at a position further delayed with respect to the rotational direction, that is, before the zero-cross point detection position of the back electromotive force. Therefore, the back electromotive force detection means 1 can detect the zero cross point of the back electromotive force before the next pseudo output pulse t is supplied. This is shown in FIG. 19 (f). After the back electromotive force detecting means 1 detects the zero cross point of the back electromotive force, the mode shifts to the normal position detection mode, in which phase switching is sequentially performed and the motor is accelerated.

As is clear from the above description, in the non-commutator DC motor of the present invention, the back electromotive force detecting means 1 includes the stator windings 11, 12, 13
Out of the back electromotive forces a, b, c induced in the
Only the zero-cross points of the one-phase back electromotive force are sequentially shaped and converted into a pulse signal train m according to ~ t6. At the time of steady rotation of the motor, the logic pulse generating means 2 receives the converted pulse m and generates six-phase pulse signals p1 to p6. However, since the pulse train m is not output from the back electromotive force generating means 1 when the motor is started, the logical pulse generating means 2 receives the pseudo output pulse t output from the pulse generating means 3 instead of the pulse train m, and similarly outputs 6-phase pulse signal p1 ~
I have created p6. The six-phase pulse signals p1 to p6 are input to the position signal synthesizing means 4, and are converted into rotational position signals as shown in FIGS. Then, finally, the power supply means 5 determines the stator windings 11, 12,.
A drive current as shown in FIG. 4, j, k, and l is sequentially supplied to both directions in 13 and the permanent magnet rotor 27 is rotated.

Therefore, the commutatorless DC motor of the present invention constitutes a full-wave drive type motor that does not require a position detecting element such as a Hall element and provides good starting characteristics without providing a special starting circuit. be able to.

In the embodiment of FIG. 7 regarding the pulse generating means according to the present invention, the clock frequency input to the second counting means has been described as being twice the clock frequency input to the first counting means. It may be double. In the embodiment of FIG. 13 for the pulse generating means according to the present invention, the value transferred as the initial value to the second counting means at the time of steady rotation was selected to be 1/2, but it was set to one half of an integer. May be.

In addition, the back electromotive force detecting means 1 according to the present invention uses three commonly connected resistors to detect the neutral point potential o of the stator winding as shown in FIG. However, it is needless to say that a signal line can be directly drawn from the neutral point of the stator winding of the electric motor and used. Further, in the embodiment, the stator winding is limited to the three-phase motor having the Y connection, but the number of phases is not limited to three and may be any number. Further, the non-commutator DC motor of the present invention can be applied to a motor in which the stator windings are Δ-connected.

Effect of the Invention Since the non-commutator DC motor of the present invention detects only the zero cross point of the back electromotive force induced in the stator winding by the back electromotive force detecting means, the rotor position detecting element such as a Hall element is used. However, it is possible to easily configure a full-wave drive type motor that supplies a current flowing through the stator winding in both directions. Therefore, the utilization rate of the stator winding is higher than that of the half-wave drive system that supplies current only in one direction of the stator winding,
An electric motor with high efficiency and high generated torque can be provided.

Further, since a rotor position detecting element such as a conventional non-commutator DC motor is not required, the complexity of adjusting the mounting position of the element and the number of wires are reduced, and the cost is greatly reduced.

Furthermore, since it is not necessary to mount a rotor position detecting element inside the motor, the motor can be made ultra-small and ultra-thin without any structural restrictions.

Also, in the non-commutator DC motor of the present invention, at the time of startup, even if the output pulse is not output from the back electromotive force detection means, the pulses of two types of cycles are alternately output from the pulse generation means for a predetermined time each. The driving is performed by forcibly switching the current-carrying phase of the stator winding. After the rotor starts rotating and detects the zero-cross point of the back electromotive force induced in the stator winding, it is possible to quickly shift to the normal position detection mode, thereby shortening the startup time of the motor. Thus, without providing a special starting circuit, good starting characteristics can be obtained which are comparable to those of a conventional motor having a position detecting element.

Furthermore, the non-commutator DC motor of the present invention has a selection circuit added so as to convert only the back electromotive force of the next phase to be detected from the energized state of the stator winding into a pulse signal train. There is no malfunction of phase switching due to erroneous detection of the zero crossing point of the electromotive force, and stable driving can always be obtained.

Furthermore, in the non-commutator DC motor of the present invention, the phase switching of the current supplied to each stator winding is performed extremely smoothly, so that the current flowing through the stator winding is not rapidly turned on / off. It is not necessary to connect a filter circuit including a relatively large capacitor to the current-carrying terminal of the stator winding to reduce the spike-like voltage caused by switching, and the commutator has very little vibration and noise even at high speed rotation. It is possible to provide a DC motor.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a non-commutator DC motor of the present invention, and FIG. 2 is a circuit showing an embodiment of an electric motor and an electric power supply means constituting the motor in one embodiment of the present invention. FIG. 3 is a signal waveform diagram of each part of the power supply means in the conventional example, FIG. 4 is a signal waveform diagram of each part of the power supply means in one embodiment of the present invention, and FIG. 5 is an embodiment of the present invention. FIG. 6 is a circuit configuration diagram showing one embodiment of the back electromotive force detecting means, FIG. 6 is a signal waveform diagram of each part thereof, and FIG. 7 is a circuit showing one embodiment of the pulse generating means constituting one embodiment of the present invention. FIG. 8 is a signal waveform diagram of each part at the time of steady rotation, FIG. 9 is a signal waveform diagram of each part at the time of startup, and FIG. 10 is another example of the pulse generating means constituting one embodiment of the present invention. FIG. 11 is a circuit configuration diagram, FIG. 11 is a signal waveform diagram of each part in the steady rotation, and FIG. Signal waveforms diagram during, the
FIG. 13 is a circuit diagram showing one embodiment of a logic pulse generating means constituting one embodiment of the present invention. FIG. 14 is a logic pulse generating means constituting one embodiment of the present invention and one embodiment of the present invention. FIG. 15 is a signal waveform diagram for explaining the operation of one embodiment of the selection signal generating means constituting FIG. 15, FIG. 15 is a circuit configuration diagram showing one embodiment of the selection signal generating means constituting one embodiment of the present invention, and FIG. FIG. 17 is a circuit diagram showing one embodiment of the position signal synthesizing means constituting one embodiment of the present invention, FIG. 17 is a signal waveform diagram for explaining the operation thereof, and FIGS. 18 and 19 are one embodiment of the present invention. FIG. 4 is a vector diagram showing a starting method of the electric motor according to an example. 1 ... back electromotive force detection means, 2 ... logic pulse generation means,
3 ... pulse generating means, 4 ... position signal synthesizing means, 5 ...
... power supply means, 6 ... selection signal generation means, 11, 12, 13 ...
... stator winding, 41 ... first counting means, 42 ... second
Counting means.

Claims (2)

(57) [Claims] 1. A back electromotive force detecting means for detecting a zero cross point of a back electromotive force generated in each of a plurality of phases of stator windings according to a selection signal output from a selection signal generating means, and generating a pulse signal train. , The pulse signal train is input,
The cycle of the pulse signal train is counted, and when the cycle is equal to or less than a predetermined value, a delay pulse obtained by delaying the pulse signal train by a time proportional to or substantially proportional to the counted cycle is supplied to the selection signal generating means. When the period of the pulse signal train exceeds a predetermined value, a delayed pulse is output to the selection signal generation means, and a pseudo output pulse in which two types of pulses alternately appear for a predetermined time each is a logical pulse. A pulse generating means for outputting to the generating means, and a pulse signal train output from the back electromotive force detecting means or a pseudo output pulse output from the pulse generating means being frequency-divided and equal to the counter electromotive force of the stator winding. Logic pulse generating means for generating a pulse signal of a plurality of phases of frequency; a plurality of pulse signals output by the logic pulse generating means; and a plurality of pulse signals output from the pulse generating means. Selection signal generating means for outputting a selection signal for determining the detection timing of the zero cross point of the back electromotive force and the stator winding to be detected based on the delay pulse, and output from the logic pulse generating means. A non-rectifier DC motor, comprising: a position signal synthesizing unit that synthesizes a position signal synchronized with a pulse signal; and a power supply unit that supplies power to a stator winding based on the position signal. 2. The pulse generator according to claim 1, further comprising a clock pulse generator, a counter for counting clock pulses output from said clock pulse generator, and a period of said pulse signal train output from said back electromotive force detector. Counting, and when the cycle exceeds a predetermined value, alternately generating a pulse having a cycle longer than the cycle determined based on the count value of the counter and a pulse shorter than the cycle for a predetermined time, respectively. The commutator-less DC motor according to claim 1, wherein: