JP2751579B2 - Commutatorless DC motor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a commutatorless DC motor, and more specifically, eliminates the need for a rotor position detecting element such as a Hall element for detecting the rotational position of a permanent magnet rotor. The present invention relates to a commutatorless DC motor.

2. Description of the Related Art A commutatorless DC motor has no mechanical contact compared to a DC motor with a brush, so it has a long life and little electrical noise.In recent years, industrial equipment and video / Widely applied to audio equipment.

Conventionally, most of the non-commutator DC motors of this type use a rotor position detecting element (for example, a Hall element) corresponding to a brush for switching an energized phase of a stator winding. However, the rotor position detection element itself is by no means inexpensive, and furthermore the complexity of adjusting the mounting position of the element,
Due to the increase in the number of wires, the commutatorless DC motor has a disadvantage that the cost is significantly increased as compared with the brushed DC motor.

In addition, since a rotor position detecting element must be mounted inside the motor, structural restrictions often occur. 2. Description of the Related Art In recent years, electric motors used for miniaturization of devices have been reduced in size and thickness, and there is no longer enough room for mounting position detecting elements such as Hall elements.

Therefore, some commutatorless DC motors without a rotor position detecting element such as a Hall element have been proposed.

One of them is a so-called half-wave drive type non-commutator DC motor which supplies a current to a stator winding only in one direction as disclosed in Japanese Patent Application Laid-Open No. 55-160980. This means that the rotor is positioned in advance by energizing only a specific stator winding phase by a self-starting circuit at the time of startup, and then to two of the three stator windings which are inactive among the three stator windings. The next energized phase is determined by detecting the induced back electromotive force, and the current is sequentially supplied to the stator winding only in one direction.

Further, there is a so-called full-wave drive type non-commutator DC motor for supplying a current to a stator winding in both directions as disclosed in, for example, JP-A-62-260586. This is because when the motor is started, the current flowing through the stator winding is forcibly switched and driven by the starting pulse output from the starting pulse generating circuit, and the rotation of the rotor increases, and the back electromotive force is applied to the stator winding. When induced, a zero-cross point of the back electromotive force is detected, and the output signal is delayed by a certain time in mono-multi to determine the energization timing. Less than,
The driving waveform will be described with reference to FIG. 2 and FIG.

FIG. 2 is a circuit diagram showing one embodiment of a stator winding power supply means constituting a non-commutator DC motor, and FIG. 3 is a signal waveform diagram of each part in a conventional example.

In FIG. 2, 27 is a permanent magnet rotor, 11, 12, and 13 are stator windings, and 21, 22, 23, 24, 25, and 26 are driving transistors, which are turned on and off by the stator. A current is supplied to the windings 11, 12, and 13. 21,22,23 of which are PNP
The transistors 24, 25 and 26 are NPN transistors. 20 is a power supply. In general, driving of the commutatorless motor is performed by applying a six-phase pulse signal obtained according to the rotational position of the rotor 27 to each base of the driving transistors 21, 26, 22, 24, 23, and 25. The waveforms of the six-phase pulse signals are shown in FIGS. However, the direction of the signal applied to the base of each transistor is applied in the direction in which current flows out to the PNP transistors 21, 22, and 23, and in the direction in which current flows in the NPN transistors 2425 and 26. First, transistors 21, 26
And the current flows through the stator windings 11 and 12. Next, the transistors 21 and 26 become conductive, and current flows through the stator windings 11 and 13. Such a phase switching operation is sequentially performed to rotate the permanent magnet rotor 27. At this time, currents shown in FIG. 3, j, k, and l are applied to the stator windings 11, 12, and 13 in both directions. When the rotor 27 is rotating, the stator windings 11, 12, 13
The voltages (back electromotive force) shown in FIGS. The six-phase pulse signals shown in FIGS. 7A to 7D correspond to the position signals of the rotor 27, and have a phase relationship with the waveforms of the back electromotive forces a, b, and c as shown in FIG. Note that the phases differ by 30 degrees. Therefore, in the prior art as disclosed in, for example, JP-A-62-260586, a zero-cross point of the back electromotive force induced in the stator winding is detected, and the output signal is delayed by a certain time by using a mono-multi. To determine the timing of energization. Therefore, the current flowing through the stator winding has a conduction width of approximately 120
The current becomes a rectangular wave having a degree (electric angle), and the current flowing through the stator winding is rapidly turned on and off.

Problems to be Solved by the Invention A commutatorless DC motor without a rotor position detecting element basically uses a back electromotive force induced in a stator winding to obtain a position required for phase switching of the stator winding. Creating a signal. Therefore, at the time of startup, since no back electromotive force is generated in each stator winding, the initial energized phase of the stator winding is not determined. Therefore, a special starting circuit is provided for starting in the commutatorless DC motors shown in these prior arts.
In the above-mentioned Japanese Patent Application Laid-Open No. 55-160980, the initial position of the rotor is determined in advance by energizing only a specific stator winding. However, to determine the initial position,
Even if only the phase is energized, the position of the rotor becomes oscillating and does not stand still, resulting in a long start-up time.

Further, in the above-mentioned Japanese Patent Application Laid-Open No. 62-260586, the stator winding is forcibly switched sequentially by an output pulse output from the starting circuit. However, even if the stator windings are forcibly switched one after another, the rotation of the rotor also becomes vibratory. Therefore, even if the detection circuit can successfully detect the zero-cross point of the back electromotive force, the normal position detection mode in which the zero-cross point of the back electromotive force is detected from the start mode in which the stator winding is forcibly switched and driven sequentially. It is difficult to switch properly. That is, the timing of switching from the start mode to the normal position detection mode is difficult, and as a result, the start time of the motor is lengthened.

Generally, these commutatorless DC motors without a rotor position detecting element do not generate back electromotive force in each stator winding because the rotor is stationary at the time of startup. For this reason, there is a problem that the initial energizing phase is not determined, and the startability is remarkably inferior to a motor having a position detecting element.

Further, in the former non-commutator DC motor shown in the prior art, a half-wave drive system in which current is supplied to only one direction of the stator winding is used, so that the drive circuit can be easily configured, but the stator is Compared to a full-wave drive type motor configured to flow current in the windings in both directions, there is a problem in that the utilization ratio of the stator windings is low, efficiency is low, and the generated torque is small.

Further, in the latter non-commutator DC motor shown in the prior art, the pulse generated at the zero cross point of the back electromotive force induced in the stator winding is mono-multi-delayed by a predetermined time to make the energized phase. Since the delay time is constant irrespective of the rotation speed of the electric motor, it is not suitable for applications requiring a change in the rotation speed, and has a problem of poor applicability.

Further, in the non-commutator DC motor shown in the prior art, the drive current flowing through the stator winding has a rectangular waveform having a conduction width of approximately 120 degrees (electrical angle). Therefore, a filter including a relatively large capacitor is actually required for the current-carrying terminal of the stator winding in order to reduce the spike-like voltage accompanying the switching. Also, the current flowing through the stator windings
Since it is turned off, it has a drawback that vibration and noise are apt to be generated during rotation, and moreover, there is a problem that the tendency is more remarkable as the motor is used at higher speed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a commutatorless DC motor that does not require a rotor position detecting element and that can obtain good start-up characteristics without providing a special starter circuit.

Still another object of the present invention is to provide a full-wave drive type non-commutator DC motor that does not require a rotor position detecting element and is configured to allow current flowing through a stator winding to flow in both directions.

Still another object of the present invention is to provide a commutatorless DC motor capable of arbitrarily changing the rotation speed of the motor.

Further, the present invention provides a non-commutator DC motor which does not require a filter circuit including a large capacitor as required for the non-commutator DC motor shown in the prior art, and has very little vibration and noise even at high speed rotation. It is intended to provide.

Means for Solving the Problems In order to achieve the above object, the present invention responded to counter-electromotive force generated in a stator winding of a plurality of phases and the stator winding selected by a selection signal of a plurality of phases. Back electromotive force detecting means for generating a pulse signal train, and counting the period of the pulse signal train when the pulse signal train is input, and when the cycle is within a predetermined range, a time proportional or substantially proportional to the counted cycle. A pulse delay unit that outputs a delayed pulse obtained by delaying the pulse signal train only, and outputs a pseudo output pulse to a logical pulse generation unit when the period exceeds a predetermined range; and a counter electromotive force detection unit. Logic pulse generating means for generating a multi-phase pulse signal corresponding to the pulse signal train;
Selection signal generating means for outputting the plurality of phase selection signals in response to the delay pulse of the pulse delay means; position signal synthesizing means for synthesizing a rotational position signal of the rotor from an output signal of the logical pulse generating means; And a stator winding power supply unit for energizing the stator winding according to the position signal.

According to the present invention, the zero cross point of the back electromotive force induced in the stator winding is pulse-shaped and converted into a pulse signal train, and a rotor position signal is created based on the pulse signal train. Therefore, even if the rotation speed of the electric motor is changed, the energization phase of the stator winding to be energized next does not change. In addition, since a selection circuit is added so as to convert only the back electromotive force of the phase to be detected next from the energized state of the stator winding into a pulse signal train, phase switching due to erroneous detection of the zero cross point of the back electromotive force is performed. , And stable driving can always be obtained without malfunction.

Therefore, it can be easily applied to applications where the rotation speed needs to be changed, and the drive is performed when the rotation speed is changed as seen in the conventional non-commutator DC motor that does not require the rotor position detecting element. Is not unstable.

In addition, the present invention can easily output a pseudo output pulse at the time of starting without providing a special starting circuit for starting, and the pseudo output pulse forcibly sequentially turns the stator windings. Switching. When the back electromotive force detection means detects the zero cross point of the back electromotive force, the normal position detection mode is performed by detecting the zero cross point of the back electromotive force from the start mode in which the stator windings are forcibly sequentially switched and driven. , And a starting characteristic comparable to that of a conventional motor with a position detecting element can be obtained.

Further, since the present invention detects only the zero-cross point of the back electromotive force induced in the stator winding, the current flowing through the stator winding can flow in both directions without being affected by the voltage due to the drive current. A configuration of a wave-driven electric motor can be adopted.

In addition, since the phase switching of the current applied to each phase of the stator winding is performed extremely smoothly, a relatively large capacitor for reducing a spike-like voltage associated with the phase switching as seen in the conventional example. It is not necessary to connect the filter circuit including to the current-carrying terminal of the stator winding.

Further, since the current flowing through the stator winding is not rapidly turned on and off as in the conventional example and the phase switching is performed smoothly, the motor can be driven with very little vibration and noise.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a commutatorless DC motor according to one embodiment of the present invention. In FIG. 1, 1
Is a back electromotive force detecting means to which the back electromotive force induced in the three-phase stator windings 11, 12, 13 and the selection signal output from the selection signal generating means 6 are input. The back electromotive force detecting means 1 detects a zero-cross point of the three-phase back electromotive force in accordance with the selection signal output from the selection signal generating means 6 and converts it into a pulse train m. This pulse train m indicates a zero-cross point of the three-phase back electromotive force. The pulse train m output from the back electromotive force detection means 1 is input to the logic pulse generation means 2 and the pulse delay means 3. The logic pulse generating means 2 divides the frequency of the pulse train m output from the back electromotive force detecting means 1 and outputs six-phase pulses having the same frequency as the back electromotive force induced in the stator windings 11, 12, and 13. Pulse delay means 3
First counts the period m of the input pulse train. Then, the output pulse is delayed by about half of the counted cycle and output to the selection signal generating means 6 as a delayed pulse.
When the counted cycle exceeds a predetermined range, a pseudo output pulse is output to the logic pulse generating means 2. The six-phase pulse signal generated by the logical pulse generating means 2 is input to the position signal generating means 4 and the rotor is driven based on the six-phase pulse signal.
It is converted into 27 rotational position signals. This rotation position signal is input to the stator winding power supply means 5. The stator winding power supply means 5 sequentially supplies a drive current to each of the stator windings 11, 12, and 13 in both directions in accordance with the rotor position signal output from the position signal generation means 4.

The operation of the commutatorless DC motor of the present invention will be described in detail based on the embodiment configured as described above.

FIG. 4 is a signal waveform diagram of each part of one embodiment of the stator winding power supply means 5 constituting the non-commutator DC motor of the present invention.

In FIG. 4, a, b, and c are stator windings 11, 12, 1 respectively.
3 is a back electromotive force waveform induced in FIG. 6D to 6I show six-phase signals synthesized by the position signal generating means 4 and correspond to six-phase position signals obtained according to the rotational position of the rotor 27. This is a trapezoidal signal waveform unlike the rectangular signal waveforms shown in FIGS. 3d to i of the conventional example. Note that a method of obtaining the trapezoidal signal waveform is described in FIGS.
This will be described in detail in the position signal generating means described with reference to the drawing.

The six-phase position signals shown in FIGS. 4d to 4i are input to the respective bases of the driving transistors 21, 26, 22, 24, 23 and 25 shown in FIG. However, the direction of the signal applied to the base of each transistor is in the direction in which current flows out to the PNP transistors 21, 22, and 23, and in the direction in which current flows in to the NPN transistors 24, 25, and 26. Then, each transistor amplifies the added base current and a current proportional to each base current flows to each collector. As a result stator winding 1
The electric currents shown in FIGS. 4, j, k, and l are applied to 1, 12, and 13 in both directions. Such a phase switching operation is sequentially performed to rotate the permanent magnet rotor 27.

The operation of each unit of the embodiment of the present invention that performs such signal processing will be further described with reference to the drawings.

FIG. 5 is a circuit diagram of the back electromotive force detecting means 1 in one embodiment of the present invention shown in FIG.

5, 14, 15 and 16 are resistors, one of which is a stator winding 1
The terminals 1, 12, and 13 are connected to each other, and the other is commonly connected. 31, 32 and 33 are comparison circuits, whose input terminals (+) are connected to the terminals of the stator windings 11, 12, and 13, respectively, and whose input terminals (-) are commonly connected to resistors 14, 15, and 16. Points are connected. 34, 35 and 36 are inverter circuits,
Outputs 1, 32 and 33 are connected. 71,72,73,74,75,76
Is a switch, and one of the switches 71, 73, 75 is connected to the inverter circuits 36, 34, 35, respectively, and the switches 72, 74,
One of 76 is connected to the comparison circuits 32, 33, 31 respectively. The other of the switches 71, 72, 73, 74, 75, 76 is commonly connected, and serves as an output terminal of the back electromotive force detection means 1.

The operation of the back electromotive force detecting means shown in FIG. 5 will be described with reference to FIG.

Resistors 14, 15, and 16 in FIG. 5 are stator windings 11, 12, and 13, respectively.
Therefore, the same potential as the neutral point o of the stator windings 11, 12, and 13 is obtained at the common connection point of the resistors 14, 15, and 16. Therefore, it is not necessary for the motor to draw a signal line from the neutral point of the stator winding. Stator winding
The back electromotive forces induced in 11, 12, and 13 are shown in Figs. 6a, b, and c, respectively.
Are input to the input terminals (+) of the comparators 31, 32, and 33 in FIG. 5, and the input terminal (-) is connected to the common connection point of the resistors 14, 15, and 16. The neutral point potential of the obtained stator winding is input. Therefore the comparator
Pulses obtained by shaping the back electromotive force a, b, c as shown in FIG. 6 are obtained at the output terminals 31, 32, 33. The pulse edges of the pulse waveforms u, v, w coincide with the zero cross points of the back electromotive forces a, b, c, respectively. In FIG. 6, t1, t2, t3, t4, t5, and t6 are six-phase signals output from the selection signal generating means 6 to the back electromotive force detecting means 1, and the rising edges thereof are the back electromotive forces a, b, and c.
5 shows the timing of the zero crossing point and the selection signal waveform delayed by 30 degrees in electrical angle. The switches 71, 72, 73, 74, 75 and 76 are turned on / off by these selection signals (signal "H").
Switch on, switch off with signal “L”).

As a result, the waveform shown in FIG. 6m is obtained from the common connection point of the switches 71, 72, 73, 74, 75 and 76, and the three-phase back electromotive force a, b,
A pulse train m in which the zero-cross point of c coincides with the rising edge of the pulse is output. That is, back electromotive force a, b, c
A pulse is output at each zero crossing point of
Pulse train m 6 times (per 60 electrical degrees) per cycle
Is output.

Next, the operation of the pulse delay unit 3 in one embodiment of the present invention will be described in detail.

FIG. 7 is a circuit configuration diagram of the pulse delay means 3 in one embodiment of the present invention shown in FIG. 1, FIG. 8 (A) is a signal waveform diagram of each part during steady rotation of the electric motor, and FIG. 8 (B) is It is a signal waveform diagram of each part at the time of starting of an electric motor.

In FIG. 7, 41 is the first counting means, and 42 is the second counting means.
Is a clock pulse generating means.
The first counting means 41 outputs a carry flag t when the counted value exceeds a predetermined value.
42 outputs a zero flag z when the count value becomes zero. The clock pulse generating means 44 generates two types of clock pulses ck and 2ck.
The clock pulse of 2ck (the clock frequency is twice ck) is input to the second counting means 42. Reference numeral 43 denotes a transfer unit to which the pulse train m output from the back electromotive force detection unit 1 and the carry flag t output from the first counting unit 41 are input, and a reset pulse r for resetting the counted value is input to the first counting unit 41. And a load pulse s for loading the count value of the first counting means 41 to the second counting means 42. Note that the signal z forms a delay pulse and the signal t forms a pseudo output pulse.

Regarding the operation of the pulse delay means 3 shown in FIG.
This will be described with reference to FIG. The first counting means 41 counts up the clock pulse ck until the reset pulse r output from the transfer means 43 is input. Since the reset pulse r has the same cycle as the pulse train m output from the back electromotive force generating means 1, the count value of the first counting means 41 is determined by counting the cycle of the pulse train m output from the back electromotive force detecting means 1. Become. FIG. 8A shows the count value in an analog manner. The count value p of the first counting means 41 is transferred to the second counting means 42 as an initial value at the timing of the load pulse s output from the transferring means 43. The second counting means 42 counts down the count value p obtained by counting the period of the pulse train m with a 2ck clock, so that the load pulse s (or the rising edge of the pulse m)
The count value becomes zero just at the midpoint of the pulse train of (1). This is analogously shown in qa of FIG. 8 (A). Since the second counting means 42 is configured to output a zero flag when the count value is zero, the second counting means 42 outputs a delay pulse z as shown by z in FIG. 8 (A). I do. The pulse train m is a pulse output from the back electromotive force detecting means 1. The rising edge of the pulse train m indicates the zero cross point of the back electromotive forces a, b, and c induced in the three-phase stator windings 11, 12, and 13. Therefore, the interval between the pulse trains s output at the rising edge of the pulse train m is equivalent to 60 electrical degrees. Therefore, the rising edge of z shown in FIG. 8 (A) is delayed by exactly 30 electrical degrees from the zero cross point of the back electromotive forces a, b, and c, and is output to the selection signal generating means 6 as a delayed pulse. Is done. Note that the load pulse s
The phase relationship between the reset pulse r and the reset pulse r is as shown in FIG. Reset pulse r to load pulse s
The reason for the further delay is to ensure that the count value of the first counting means 41 is transferred to the second counting means 42. In the figure, the pulse widths of the pulses s and r are shown large for convenience, but are assumed to be sufficiently narrower than the pulse period.

Next, the operation at the time of starting the motor will be described with reference to FIG. 8 (B). The first counting unit 41 counts up the clock pulse ck until the reset pulse r output from the transfer unit 43 is input. However, since the rotor is stationary, the back electromotive force generating means 1 generates the pulse train m
Is not output. Accordingly, the count value of the first counting means 41 monotonically increases as shown by p in FIG. 8B, and when the counted value reaches a predetermined value, the first counting means 41 increases.
Outputs the carry lab t to the transfer means 43. The transfer means 43 receives the signal t and outputs a reset pulse r and a load pulse s. The second counting means 42 counts down after the initial value is loaded by the load pulse s. When the count value of the second counting means 42 becomes zero, the zero flag z is output to the selection signal generating means 6 as a delay pulse. The carry flag t is output to the logic pulse generating means 2 as a pseudo output pulse. When the motor is started, the pulse train m is not output from the back electromotive force detecting means 1, so that the pseudo output pulse t becomes a pseudo signal for sequentially performing the phase switching operation of the stator winding. The rotor 27 starts rotating. Now, as indicated by the dotted line in qa in FIG. 8B, when the transfer means 43 receives the signal t, the count value of the first count means 41 is directly used as the initial value by the second count means 42. Shall be forwarded. In such a configuration, as is apparent from the dotted waveform of qa in FIG. 8B, the second counting means 42 is down-counted and the first counting means 42 does not reach the zero before the counted value reaches zero. A case occurs where the count value of the counting means 41 is further transferred. In that case, the count value of the second counting means 42 does not become zero and the delay pulse z is not output. Therefore, the pulse x as shown by z in FIG. 8B is not generated. As a result, even if the phase switching of the stator winding is forcibly performed by the pseudo output pulse t,
Next, the selection signal of the phase in which the zero crossing point of the back electromotive force is to be detected is not output from the selection signal generating means 6, and the motor is not accelerated properly.

Therefore, when the transfer means 43 receives the signal t as shown by the solid line waveform indicated by qa in FIG.
Instead of transferring the count value of 41 to the second counting means as it is, a predetermined value smaller than the count value of the first counting means 41 is transferred to the second counting means. Then, the count value of the first count means 41 is not further transferred before the count value of the second count means 42 reaches zero as described above, and the second count means 42
Is always zero and the delay pulse z is output. Thereafter, a delay pulse z as shown by z in FIG. 8 (B) is output from the second counting means 42 by the same operation as in the steady state, and the delay pulse z is applied to the selection signal generating means 6 to reduce the power. The supply means 5 sequentially switches the current-carrying phases of the three-phase stator windings 11, 12, and 13. And the motor is accelerated,
Good starting characteristics are obtained.

FIG. 9 is a circuit diagram of a main part of another embodiment of the pulse delay means 3 in one embodiment of the present invention shown in FIG. 1, FIG. 10 (A) is a signal waveform diagram of each part during steady rotation of the electric motor, FIG. 10 (B) is a signal waveform diagram of each part when the motor is started.

Components having the same functions as those in FIG. 5 are denoted by the same reference numerals, and redundant description will be omitted.

In FIG. 9, 41 is the first counting means, and 42 is the second counting means.
The first counting means is composed of an 8-bit digital counter, and the second counting means is composed of a 5-bit digital counter. The same clock ck is input to the first counting means 41 and the second counting means 42, respectively. The first counting means 41 counts up the clock ck, and the second counting means 42 counts down the clock ck. Reference numeral 45 denotes a switch transfer circuit composed of seven switches, and a load pulse s of the transfer means 43 shown in FIG.
Thus, the bit is connected to the contact for a short time, and the bits (5 bits in the example of FIG. 9) except the least significant bit of the count value of the first counting means 41 are transferred to the second counting means 42. When the carry flag t is output from the first counting means 41 whose count value has overflowed, the switch transfer circuit 45 is connected to the contact a for a short time, and All bits of the counting means 42 are set to "1".

The operation of the pulse delay means shown in FIG. 9 will be described first with reference to FIG. 10 (A) when the permanent magnet rotor 27 is rotating normally.

The count value p of the first counting means 41 is transferred to the second counting means 42 at the timing of the load pulse s output from the transferring means 43. However, since only the least significant bit of the first counting means 41 is discarded and transferred to the second counting means 42, as shown in FIG.
As the initial value of 42, a value that is 1/2 of the count value p of the first counting means 41 is given as the initial value. The second counting means 42 counts down p / 2 corresponding to a half of the count value obtained by counting the period of the pulse train s by the clock ck, so that the count value becomes zero at the intermediate point of the pulse train s. . Therefore, the second counting means 42 outputs a delay pulse z as shown in FIG. 10 (A). Therefore, the rising edge of z shown in FIG.
That is, it is delayed by just 30 electrical degrees from the zero-cross point of a, b, and c.

Next, the operation at the time of starting the motor will be described with reference to FIG. 10 (B). Since the back electromotive force detecting means 1 does not output the pulse train m at the time of starting, the first counting means
41 continues counting up the clock pulse ck. Therefore, the count value of the first counting means 41 is as shown in FIG.
When the count value overflows, the carry flag t is output from the first counting means 41 and input to the transfer means 43 and the switch transfer circuit 45 as shown by p in FIG. The transfer means 43 receives the signal t and outputs a reset pulse r and a load pulse s. The second count means 42 is loaded with the initial value by the load pulse s,
Now, as indicated by a dotted line in qa of FIG. 10 (B), a 7-bit counter is prepared as the second counting means, and when the transfer means 43 receives the signal t, the first counting means 41 counts. It is assumed that the value of p / 2 which is half of the numerical value (upper 7 bits) is transferred as it is to the second counting means 42 as an initial value. In such a configuration, as is apparent from the dotted waveform of qa in FIG. 10 (B), at the time of startup, the second counting means 42 is down-counted and the count value does not reach zero before starting. A case occurs where the count value of the first counting means 41 is further transferred. In this case, the count value of the second counting means 42 does not become zero and the delay pulse z is not output. Therefore, the pulse x as shown by z in FIG. 11 (B) does not occur. As a result, the phase switching of the stator winding is not performed well, and the acceleration of the motor is not performed well.

Therefore, when the transfer means 43 receives the signal t at the time of startup, as shown by the solid line waveform indicated by qa in FIG. 11 (B), the value of p / 2 which is half the count value of the first count means 41 ( In this case, instead of transferring the upper 7 bits excluding the least significant 1 bit) to the second counting means 42 as it is, by connecting the switch transfer circuit 45 to the contact b for a short time during the transfer, the first P / which is half of the count value of the counting means 41
A predetermined value smaller than the value of 2 (in this case, all bits are 5 bits of “1”) is transferred to the second counting means 42. Then, the second counting means 42 as described above
The count value of the first count means 41 is not further transferred before the count value of the second count means 41 reaches zero, and the count value of the second count means 42 always becomes zero, and the delay pulse z is output. Hereinafter, the second counting means 42 operates in the same manner as in the steady state.
Outputs a delay pulse z as shown by z in FIG. 11 (B). The delay pulse z is applied to the selection signal generating means 6, and the power supply means 5 causes the three-phase stator windings 11, 12,. The switching of the thirteen energizing phases is performed sequentially. Then, the motor is accelerated, and good starting characteristics are obtained.

Although the frequency of the clock supplied to the first and second counting means is different in the embodiment shown in FIG.
The embodiment shown has the advantage that only one type of clock is required.

FIG. 11 is a circuit diagram of another embodiment of the pulse delay means 3 in one embodiment of the present invention shown in FIG. 1, and FIG. 12 (A).
Is a signal waveform diagram of each part at the time of steady rotation of the rotor, and FIG.
FIG. 2B is a signal waveform diagram of each part when the motor is started.

The components having the same functions as those in FIGS. 7 and 9 are denoted by the same reference numerals, and redundant description will be omitted.

In FIG. 11, reference numeral 61 denotes first up / down counting means, and 62 denotes second up / down counting means. First
The up / down counting means 61 and the second up / down counting means 62 have an up count input CU and a down count input CD, respectively. Also, the first up / down counting means 61 and the second up / down counting means 62 output carry flags ta and tb, respectively, when the count value overflows, and count down to zero. When the zero flag za, zb respectively
Is output. An OR circuit 65 receives two signals of carry flags ta and tb and outputs a pulse t. Reference numeral 63 denotes a clock switching circuit, which is two kinds of clock pulses ck and 2ck (the clock frequency is ck
Is supplied to the up-count input CU or the down-count input CD in accordance with the pulse m output from the back electromotive force detecting means 1 and the flag t output from the OR circuit 65. An OR circuit 64 is a zero flag za, output by each of the first and second up / down counting means 61 and 62.
zb outputs the delayed pulse z input.

The operation of the pulse delay circuit shown in FIG. 11 will be described first with reference to FIG. 12 (A) when the permanent magnet rotor 27 is rotating normally.

First, it is assumed that the switch of the clock switching circuit 63 is located at the contact side shown in FIG. Then, the clock ck is supplied to the up-count input CU of the first up-down counting means 61, and the pulse m is supplied to the clock switching circuit.
First up / down counting means 61 until input to 63
Performs an up-count operation. Next, when the pulse m is input to the clock switching circuit 63, the switch of the clock switching circuit 63 is switched to the contact b side, and the first up / down counting means 61 switches to the down counting operation. At this time, the clock 2ck is input to the down count input of the first up / down count means 61. Accordingly, the count value obtained by counting up the cycle of the pulse train m is down-counted by the clock of 2ck, so that the count value becomes zero at exactly the middle point of the pulse train m. This is shown in FIG. 12 pa.
As a result, the first up / down counting means 61 outputs a zero flag za as shown in FIG. Similarly, the second up / down counting means 62 repeats the up / down counting operation as indicated by pb in FIG.
It outputs a zero flag as indicated by zb in FIG. Since the zero flags za and zb are generated alternately, a signal z as shown in FIG. 12 (A) is output from the OR circuit 64, and the pulse delay means shown in FIG. ,
The delay pulse z delayed by exactly 30 electrical degrees from the zero cross point of c is output.

Next, the operation at the time of starting the motor will be described with reference to FIG. 13 (B).

First, it is assumed that the switch of the clock switching circuit 63 is located at the contact a side shown in FIG. The first up / down counting means 61 counts up the clock pulse ck until the pulse m output from the back electromotive force generating means 1 is input. However, since the rotor is stationary, the back electromotive force generating means 1 does not output the pulse train m. Therefore,
The count value of the first up / down counting means 61 monotonically increases as indicated by pa in FIG. 12 (B), and when the count value overflows, the first up / down counting means 61.
From 61, carry flag ta is output to clock switching circuit 63. Then, the clock switching circuit 63 switches the switch of the clock switching circuit 63 to the contact b side as in the case of the normal rotation of the electric motor, and the first up / down counting means 61.
Is switched from an up-count operation to a down-count operation. Moreover, the clock supplied to the down-count input is
Since it is 2ck, the up-counted count value is down-counted by the 2ck clock, and the count value eventually becomes zero. This is shown in pa of FIG. 12 (B). As a result, the first up / down counting means 61 outputs a zero flag za as shown in FIG. 12 (B). Similarly, the second up / down counting means 62 repeats the up / down counting operation as indicated by pb in FIG. 12 (B) and outputs a zero flag as indicated by zb in FIG. 12 (B). Since za and zb occur alternately, the OR circuit 64 outputs a pulse signal z as shown in FIG. 12 (B). The pulse signal z shown in FIG. 12 (B) corresponds to a delay pulse, and the pulse signal t corresponds to a pseudo output pulse at the time of starting. Hereinafter, the delay pulse z
Is applied to the selection signal generating means 3, the pseudo output pulse t is applied to the logical pulse generating means 2, and the power supply means 5 sequentially switches the energized phases of the three-phase stator windings 11, 12, and 13. Will be Then, the motor is accelerated, and good starting characteristics are obtained.

7 and 9, the transfer means for transferring the count value of the first counting means to the second counting means is required. In the embodiment of FIG. 11, the transfer means is unnecessary and the clock is switched. There is an advantage that the circuit only needs to switch between the up-counting and down-counting operations.

FIG. 13 is a circuit configuration diagram of the logic pulse generating means 2 in one embodiment of the present invention shown in FIG. 1, and a signal waveform diagram of each part thereof is shown in FIG.

In FIG. 13, reference numeral 82 denotes a two-input OR circuit to which a pulse train m of the back electromotive force detecting means 1 and a pseudo output pulse t of the pulse delaying means 3 are inputted. Reference numeral 81 denotes a six-phase ring counter to which the output of the OR circuit 82 is input, and outputs six-phase pulse signals p1, p2, p3, p4, p5, and p6 shown in FIG. 14 to six output terminals. The pulse width of these pulse signals is 60 degrees in electrical angle. These six-phase pulse signals p1 to p6 are output to the position signal generator 4 and the selection signal generator 6 shown in FIG.

FIG. 15 is a circuit configuration diagram of the selection signal generating means 6 in one embodiment of the present invention shown in FIG. 1, and a signal waveform diagram of each part thereof is also shown in FIG.

In FIG. 15, reference numerals 91, 92, 93, 94, 95 and 96 denote D flip-flops, each of which has a clock terminal C to which a delayed pulse z output from the pulse delay means 3 is input, and a D pulse input terminal which generates a logical pulse. The six-phase pulse signals p1 to p6 output by the means 2 are input. As a result, the six-phase pulse signals p1 to p6 of the logic pulse generating means 2 are output from the Q output terminals of the D flip-flop.
Are respectively delayed by the pulse width of the delay pulse z to output six-phase signals t1 to t6. This is shown in FIG. These six-phase pulse signals t1 to t6 become the six-phase selection signals shown in FIG. 6, and have a pulse width of 60 degrees in electrical angle and are output to the back electromotive force detecting means 1.

FIG. 16 is a circuit diagram of the position signal generating means 4 in one embodiment of the present invention shown in FIG. 1, and FIG. 17 shows a signal waveform diagram of each part.

In FIG. 16, reference numeral 50 denotes a reset switch for discharging the charge stored in the charging / discharging capacitor 51, and reference numeral 51 denotes a charging / discharging capacitor for generating a saw-tooth wave corresponding to the output of the logic pulse generating means 2. , 52 is a charge / discharge capacitor
A constant current source line for supplying a charging current to 51, and 54 is a buffer up whose input is connected to the capacitor 51. The capacitor 51, the switch 50, the constant current source circuit 52, and the buffer amplifier 54 constitute the sawtooth wave generating means 100. 56 is an inverting amplifier to which the output of the buffer amplifier 54 is connected. Reference numeral 55 denotes a buffer amplifier to which an input is connected to a reference voltage source 53. Outputs of the buffer amplifier 54, the buffer amplifier 55, and the inverting amplifier 56 are output from the signal
4,105,106. The signal synthesizing means 101, 1
Since 02, 103, 104, 105, 106 have the same configuration,
Only the configuration of the signal combining means 101 is shown. In the signal synthesizing means 101, switches 57, 58 and 59 are switches, one of which is connected to the buffer amplifiers 54 and 55 and the inverting amplifier 56, respectively, and the other of the switches 57, 58 and 59 is commonly connected and connected to the resistor 61. I have. The voltage signal obtained by the resistor 61 is converted into a current signal by the current conversion circuit 62 and becomes an output of the signal synthesis means 101.

Next, the operation of the position signal generating means 4 shown in FIG. 16 will be described with reference to the signal waveform diagrams of each part in FIG.

When the switch 50 of the sawtooth wave generating means 100 is open, a constant current is supplied to the capacitor 51 by the constant current circuit 52, and when the switch 50 is closed, the electric charge stored in the capacitor 51 is instantaneously discharged. . However, since the switch 50 is configured to close for a short time at the rising edge of the pulse m output from the back electromotive force detection means 1, the charge stored in the capacitor 51 is instantaneously discharged at the rising edge of the pulse m, Seventeenth from the sawtooth wave generating means 100
A sawtooth wave having the same phase as the pulse m as shown in FIG. St is obtained. Reference numeral 56 denotes an inverting amplifier, to which the output st of the buffer amplifier 54 is connected, so that a signal obtained by inverting st as shown in FIG. 17 stb is obtained from the output of the inverting amplifier 56. FIG. 17 sf shows the waveform of the reference voltage source 53, the magnitude of which is set equal to the peach value of the sawtooth wave st. The switches 57, 58, 59 constituting the signal synthesizing means 101 are turned on / off (switched on by a signal "H" and switched on by a signal "L") according to the pulse signals p1, p2, p3 output from the logical pulse generating means 2. (OFF), the outputs of the buffer amplifiers 54 and 55 and the inverting amplifier 56 are combined by the signal combining means 101, and the position signal waveform shown in FIG. 17d is obtained from the output terminal d.

When the switches 57, 58 and 59 are all turned off, the potential of the resistor 61 becomes equal to the ground potential. The combined voltage value obtained in the resistor 61 in this way is
It is converted into a current value (current sink) by 62, and a rotation position signal waveform shown in FIG. 17 is output from the output terminal d.

Hereinafter, similarly, the signal synthesizing means 102, 103, 104, 105, 106
Pulse signals (p2, p3, p4), (p3, p
4, p5), (p4, p5, p6), (p5, p6, p1) and (p6, p1, p2) output position signals e, f, g, h, i. FIG. 17 d to i
Is a position signal of the rotor 27 and is input to the stator winding power supply means 5 in FIG.

As is clear from the above description, in the non-commutator motor of the present invention, the back electromotive force detecting means 1 detects the zero cross points of the back electromotive forces a, b, and c induced in the stator windings 11, 12, and 13. Detected and converted to a conversion pulse m, the logic pulse generating means 2 receives this conversion pulse m and generates six-phase pulse signals p1 to p6. The six-phase pulse signals p1 to p6 are input to the position signal synthesizing means 4 and are changed into rotor position signals as shown in FIGS. Finally, the electric power supply means 5 applies the stator windings 11, 12, 13 according to the rotor position signals di to i, as shown in FIGS.
A drive current as shown by k and l is sequentially supplied in both directions, and as a result, the permanent magnet rotor 27 is rotated. The converted pulse m of the back electromotive force detecting means 1 is delayed by the pulse delaying means 3 by an electrical angle of 30 degrees and converted into a delayed pulse z. The six-phase pulse signals p1 to p6 are six-phase selection signals t1 to t6 delayed by the selection signal generating means 6 by the pulse width of the delay pulse z.
And input to the back electromotive force detection means 1.

Therefore, the non-commutator motor of the present invention can constitute a full-wave drive type motor that allows current flowing in the stator winding to flow in both directions without providing a rotor position detecting element such as a Hall element.

In the pulse delay means according to the present invention, in the embodiment of FIG. 7, the clock frequency input to the second count means has been described as twice the clock frequency input to the first count means. It may be double.
In the pulse delay means according to the present invention, in the embodiment shown in FIG. 10, the value transferred as an initial value to the second count means at the time of steady rotation is selected to be one half, but is not a whole number. May be. In the pulse delay means according to the present invention, in one embodiment of FIG. 12, the clock frequency input to one of the up-count input terminal and the down-count input terminal is the clock frequency input to the other input terminal. Although described as being twice the frequency, it is needless to say that an integer multiple can be used.

The back electromotive force detecting means 1 according to the present invention uses three commonly connected resistors to detect the neutral point potential of the stator winding as shown in FIG. Needless to say, it is also possible to directly draw out the signal line from the neutral point of the stator winding of the motor and use it. Further, in the embodiment, the stator winding is limited to the three-phase motor having the Y connection, but the number of phases is not limited to three, and may be any number. Further, the commutatorless motor of the present invention can be applied to a motor in which the stator windings are connected by Δ.

Effect of the Invention Since the present invention is configured as described above,
The following effects are obtained.

Since the non-commutator DC motor of the present invention detects only the zero cross point of the back electromotive force induced in the stator winding by the back electromotive force detecting means, a rotor position detecting element such as a Hall element is not required. However, it is possible to easily configure a full-wave drive type motor that supplies current flowing through the stator windings in both directions.
Therefore, compared with the half-wave drive system in which current is supplied to only one direction of the stator winding, a motor having a higher utilization rate of the stator winding, high efficiency, and high torque can be provided.

Further, since a rotor position detecting element such as a conventional non-commutator motor is unnecessary, the complexity of adjusting the mounting position of the element and the number of wires are reduced, and the cost is greatly reduced.

Furthermore, since there is no need to mount a rotor position detecting element inside the motor, the motor can be made ultra-small and ultra-thin without any structural restrictions.

In addition, the commutatorless DC motor of the present invention, at the time of start-up, sequentially switches the current-carrying phases of the stator windings by a pseudo output pulse output from the delay pulse generating means, so that a good start-up without providing a special start-up circuit. Characteristics are obtained.

Further, the commutatorless DC motor of the present invention always counts the time between the zero-cross points of the back electromotive force induced in each stator winding, and based on the counted value, the stator winding to be energized next. When the rotational speed of the motor is changed, the energizing phase of the next stator winding to be energized does not change, and a stable drive is always obtained. Is also provided. In addition, since a selection circuit is added so as to convert only the back electromotive force of the phase to be detected next from the energized state of the stator winding into a pulse signal train, phase switching due to erroneous detection of the zero cross point of the back electromotive force is performed. , And stable driving can always be obtained. Therefore, the present invention can be applied to an application in which the number of rotations of the electric motor needs to be arbitrarily changed.

Furthermore, in the non-commutator DC motor of the present invention, the phase switching of the current supplied to each stator winding is performed extremely smoothly, so that the current flowing through the stator winding is not rapidly turned on / off. It is not necessary to connect a filter circuit including a relatively large capacitor to the current-carrying terminal of the stator winding to reduce spike-like voltage due to switching. An electric motor can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of one embodiment of a non-commutator DC motor of the present invention, and FIG. 2 is an embodiment of an electric motor and a stator winding power supply means constituting the motor in one embodiment of the present invention. FIG. 3 is a circuit configuration diagram showing an example, FIG. 3 is a signal waveform diagram of each part of a stator winding power supply unit in a conventional example, and FIG. 4 is a signal waveform diagram of each unit of a stator winding power supply unit in one embodiment of the present invention. FIG. 5 is a circuit diagram showing one embodiment of the back electromotive force detecting means constituting one embodiment of the present invention, FIG. 6 is a signal waveform diagram of each part of FIG. 5, and FIG. FIG. 8 (A) is a circuit configuration diagram showing an embodiment of a pulse delay means constituting the embodiment, FIG. 8 (A) is a signal waveform diagram of each part when steady rotation is performed in FIG. 7, and FIG. Signal waveform diagram,
FIG. 9 is a circuit diagram of a main part of another embodiment of the pulse delay means constituting one embodiment of the present invention. FIG. 10 (A) is a signal waveform diagram of each part in the case of steady rotation in FIG. FIG. 10 (B) is a signal waveform diagram at the time of startup, FIG. 11 is a circuit diagram showing another embodiment of the pulse delay means constituting one embodiment of the present invention, and FIG. 12 (A) is a circuit diagram of FIG. FIG. 11 is a signal waveform diagram of each part in the case of steady rotation, FIG. 13 is a circuit configuration diagram showing one embodiment of a logic pulse generating means constituting one embodiment of the present invention, and FIG. FIG. 14 is a signal waveform diagram for explaining the operation of one embodiment of the logic pulse generating means constituting one embodiment of the present invention and the selection signal generating means constituting one embodiment of the present invention. FIG. 15 is a circuit diagram showing one embodiment of the selection signal generating means constituting one embodiment of the present invention, and FIG. Circuit diagram showing an embodiment of a position signal generating means constituting an embodiment of a light, FIG. 17 is a signal waveform diagram illustrating the operation of FIG. 16. 1 ... back electromotive force detection means, 2 ... logic pulse generation means,
3 ... pulse delay means, 4 ... position signal generation means, 5 ...
... stator winding power supply means, 6 ... selection signal generation means,
11, 12, 13 ... stator windings, 41 ... first counting means,
42 second counting means, 61 first up / down counting means, 62 second up / down counting means.

Claims (18)

(57) [Claims] A plurality of stator windings; a back electromotive force detecting means for generating a pulse signal train in response to a back electromotive force generated in the stator winding selected by the plurality of phase selection signals; The pulse signal train is input, the cycle of the pulse signal train is counted, and when the cycle is within a predetermined range, a delay pulse obtained by delaying the pulse signal train by a time proportional or substantially proportional to the counted cycle. And a pulse delay unit for outputting a pseudo output pulse to the logic pulse generation unit when the period exceeds a predetermined range, and a multi-phase pulse signal corresponding to the pulse signal train of the back electromotive force detection unit is generated. Logic pulse generating means, a selection signal generating means for outputting the multi-phase selection signal in response to the delay pulse of the pulse delay means, and a rotation position of the rotor based on an output signal of the logic pulse generating means. A position signal synthesizing means for synthesizing a signal, no commutator DC motor, characterized in that it is configured to include a stator winding power supply means for energizing the stator windings in response to the rotational position signal. The pulse delay means counts the cycle of the pulse signal train output from the back electromotive force detecting means, and when the cycle is within a predetermined range, delays by a time equal to an integral number of the counted cycle. The non-commutator DC motor according to claim 1, wherein the motor is configured to output the delayed pulse. 3. The pulse delay means detects a cycle of a pulse signal train output from the back electromotive force detection means, and when the cycle is within a predetermined range, delays by a half of the counted cycle. The non-commutator DC motor according to claim 1, wherein the motor is configured to output the delayed pulse. 4. The pulse delay means includes: first count means for counting the period of a pulse signal train output from the back electromotive force detection means; and a count value of the first count means transferred to a second count means. Transfer means, a second count means for calculating and outputting a selection signal of a plurality of fixed windings from the transferred count value, and a clock generation means for inputting a clock to the first and second count means. The non-commutator DC motor according to claim 1, wherein the DC motor includes: 5. The non-rectifying device according to claim 4, wherein the transfer means changes the initial value transferred to the second counting means according to the count value of the first counting means. Child DC motor. 6. The transfer means transfers a value proportional to or substantially proportional to the count value of the first count means to the second count means when the count value of the first count means is within a predetermined range. The non-commutator DC motor according to claim 4, wherein a constant value is transferred when the value exceeds the limit. 7. The apparatus according to claim 4, wherein the transfer means is configured to transfer a value obtained by dividing the count value of the first counting means by an integer to the second counting means. No commutator DC motor. 8. The apparatus according to claim 4, wherein said transfer means transfers half the count value of said first count means to said second count means. No commutator DC motor. 9. The clock frequency input to the second counting means is different from the clock frequency input to the first counting means.
The commutatorless DC motor as described. 10. The non-rectifier direct current DC according to claim 4, wherein the clock frequency input to the second counting means is an integral multiple of the clock frequency input to the first counting means. Electric motor. 11. The non-rectifier DC according to claim 4, wherein the clock frequency input to the second counting means is twice the clock frequency input to the first counting means. Electric motor. 12. The non-rectifier DC motor according to claim 4, wherein the clock frequency inputted to the second counting means is made different according to the count value of the first counting means. . 13. A pulse delaying means for switching between an up-counting operation and a down-counting operation in accordance with a pulse train generated by a back electromotive force detecting means. When one is an up-counting operation, the other performs a down-counting operation. And second up / down counting means, and the first and second counting means.
2. A non-commutator DC motor according to claim 1, further comprising a clock generating means for inputting a clock to said up / down counting means. 14. The apparatus according to claim 1, wherein said first and second up / down counting means are configured to switch between an up-count operation and a down-count operation when the count value reaches a predetermined value. 13) The commutatorless DC motor described in the above. 15. The first and second up / down counting means are characterized in that a clock frequency input to one count input terminal is different from a clock frequency input to the other count input terminal. Claim (1
3) The commutatorless DC motor described in the above. 16. The first and second up / down counting means is characterized in that a clock frequency input to one count input terminal is an integral multiple of a clock frequency input to the other count input terminal. A commutatorless DC motor according to claim 13. 17. The first and second up / down counting means is characterized in that the clock frequency input to one count input terminal is twice the clock frequency input to the other count input terminal. A commutatorless DC motor according to claim 13. 18. A position signal generating means for generating a sawtooth wave in response to a pulse signal of a logic pulse generating means, and a plurality of phase position signals in response to a pulse signal of the logic pulse generating means. 2. The non-commutator DC motor according to claim 1, further comprising a signal synthesizing means for synthesizing.