JP2502781C - - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a commutatorless DC motor. More specifically, the rotation of the permanent magnet rotor
Irregularity that eliminates the need for a rotor position detection element such as a Hall element to detect the position
The present invention relates to a shunt DC motor, and more particularly to improvement of starting characteristics. 2. Description of the Related Art A commutatorless DC motor has no mechanical contacts compared to a brushed DC motor.
In recent years, industries that require high reliability have long life and low electrical noise.
Widely applied to audio and visual equipment. Conventionally, most of this type of commutator-less DC motors have a stator winding energized phase switch.
Use a rotor position detecting element equivalent to a brush, for example, a Hall element
doing. However, the rotor position detection element itself is by no means inexpensive,
In addition, due to the complexity of adjusting the mounting position of the element and the increase in the number of wires, a non-commutator DC motor
However, there is a disadvantage that the cost is greatly increased as compared with the brushed DC motor. Also, since the rotor position detecting element must be installed inside the motor,
Often construction constraints occur. In recent years, it is used with the miniaturization of equipment
The motor is also small and thin, and is suitable for mounting position detection elements such as Hall elements.
I can't afford it. Therefore, a commutatorless DC motor without a rotor position detecting element such as a Hall element at all.
There have been several proposals. One of them is fixed as disclosed in, for example, JP-A-55-160980.
A so-called half-wave drive type non-rectifier DC power supply that supplies current to the
There is a motive. This is done by energizing only the specific stator winding phase with the self-starting circuit to the starting temple.
The positioning of the trochanters is performed in advance, and then the two stationary stator windings of the three-phase stator windings.
By detecting the back electromotive force induced in the winding, the next energized phase is determined and the stator
The current is sequentially supplied to the winding only in one direction. Further, for example, a stator as disclosed in JP-A-62-260586 is disclosed.
There is a so-called full-wave drive type non-commutator DC motor that supplies a current to a winding in both directions. This is the starting pulse output from the starting pulse generation circuit when starting the motor.
The current flowing through the stator winding is forcibly switched and driven, and the rotation of the rotor rises.
When a back electromotive force is induced in the stator winding, the zero cross point of the back electromotive force is detected.
, The output signal is delayed by a certain time in a mono-multi
It is to decide the mining. Problems to be Solved by the Invention These commutatorless DC motors without a rotor position detecting element basically have a stator winding.
The back EMF induced in the wire is used to generate the position signal necessary for stator winding phase switching.
Has formed. Therefore, at start-up, a back electromotive force is generated in each stator winding.
The initial energized phase of the stator winding is not determined. The prior art described above
In the commutatorless DC motor shown in (1), a special starting circuit is provided for starting.
You. In the technique disclosed in Japanese Patent Application Laid-Open No. 55-160980, a specific stator winding
The initial position of the rotor is determined in advance by energizing only the rotor. However, determine the initial position
Therefore, even if only one phase of the stator winding is energized, the position of the rotor becomes oscillatory.
It does not stand still, resulting in longer startup times. Also, Japanese Patent Application Laid-Open No. 62-26058
In the technique disclosed in Japanese Patent Application Laid-Open No. 6-206, a stator winding is generated by an output pulse output from a starting circuit.
Are forcibly switched sequentially. However, the stator windings are forcibly switched sequentially
Even so, the rotation of the rotor becomes oscillatory. Therefore, the zero-cross
Start-up mode in which the stator windings are forcibly switched in sequence and driven even if the
In the normal position detection mode, where the zero cross point of the back electromotive force is detected from the
It is difficult to switch. That is, from the start mode to the regular position detection mode
Is difficult to switch to, and the starting time of the electric motor is prolonged. In general, these commutatorless DC motors without the rotor position detecting element have a
Since the rotor is stationary, no back electromotive force is generated in each stator winding. So
Because the initial energized phase is not determined, the startability is significantly higher than that of a motor with a position detection element.
There is a problem that it is inferior. In addition, a commutatorless DC motor disclosed in JP-A-55-160980 is disclosed.
However, since it is a half-wave drive system that supplies current only in one direction
Although the drive unit can be easily configured, the stator winding utilization is lower and the efficiency is lower than that of a full-wave drive type motor configured so that the current flowing through the stator winding flows in both directions.
And the generated torque is small. In addition, there is no need for a commutatorless DC motor disclosed in JP-A-62-260586.
The pulse generated at the zero-cross point of the back electromotive current induced in the stator winding.
This is a method to determine the current-carrying phase by delaying the current for a certain time.
It is necessary to change the rotation speed because the delay time is constant regardless of the rotation speed of the motor.
However, there is a problem that the method is not suitable for the intended use and has poor applicability. The present invention is a commutatorless DC motor that does not require a rotor
A commutatorless DC motor with good start-up characteristics
It is intended to provide. Furthermore, the present invention does not require a rotor position detecting element, and furthermore, an electric current flowing through the stator winding.
To provide a full-wave drive type non-commutator DC motor configured to flow current in both directions.
It is intended to be. Furthermore, the present invention provides a method of arbitrarily changing the number of revolutions of a motor.
It is an object of the present invention to provide a commutatorless DC motor capable of performing the following. Means for Solving the Problems In order to achieve the above object, the present invention provides a method in which each of a plurality of phases of a stator winding is generated.
Back electromotive force detecting means for pulse shaping the back electromotive force to obtain a pulse signal train;
When a signal sequence is input and the period of the signal sequence is counted and the period is within a predetermined range,
A delayed pulse delayed by one half of the counted cycle is output, and the cycle of the signal train is
When it exceeds a predetermined range, it is delayed by a time shorter than one half of the counted cycle.
Pulse delay means for outputting a delay pulse, and in response to an output signal of the pulse delay means
Logic pulse generating means for generating multiple phase switching pulses having the same frequency as the back electromotive electrode
And the output signal of the logic pulse generation means as the rotation position signal of the rotor,
And a stator winding power supply unit for sequentially energizing the stator winding. Operation The present invention has the above-described configuration, in which the back electromotive force induced in each stator winding is reduced.
The time between zero-cross points is always counted, and the next stator to be energized based on the count value
Since the winding phase is determined, the next phase will be applied even if the motor speed is changed.
The current-carrying phase of the power stator winding does not change, and stable driving is always obtained.
. Therefore, it can be easily applied to applications where the number of rotations needs to be changed.
As seen in conventional non-commutator DC motors that do not require a rotor position detection element,
When the rotational speed is changed, the driving does not become unstable. In addition, the present invention does not require a special start-up circuit for start-up.
In this case, the stator windings are forcibly switched sequentially by a pseudo output pulse. And
When the back electromotive force detection means detects the zero cross point of the back electromotive force, the stator winding is forced
Switch sequentially and detect the zero-cross point of the back electromotive force from the drive start mode.
Can be quickly switched to the normal position detection mode.
A starting characteristic comparable to that of a motor with a motor can be obtained. In addition, only the zero cross point of the back EMF induced in the stator winding is detected.
Flow through the stator windings without being affected by the voltage due to the drive current.
Of a full-wave drive type motor capable of flowing electric current in both directions. did
Therefore, compared to a half-wave drive type motor, a high efficiency, high torque non-commutator DC motor
Can be provided. Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a commutatorless DC motor according to an embodiment of the present invention.
FIG. In FIG. 1, reference numeral 1 denotes a back electromotive force detecting means, and three-phase stator windings 11,
The back electromotive force induced in 12, 13 is input. The back electromotive force detecting means 1 has three phases
The zero cross point of the electromotive force is detected and converted into a pulse train n. This pulse train n has three phases
2 shows the zero cross point of the back electromotive force. The pulse train n output from the back electromotive force detecting means 1 is
It is input to the pulse delay means 2. First, the pulse delay means 2
The cycle n is counted. Then, the input pulse is delayed by about half of the counted cycle.
Extend. Numeral 3 denotes a logic pulse generating means for generating a pulse z output from the pulse delaying means 2.
Six phases with the same frequency as the counter electromotive force induced in stator windings 11, 12, and 13 by frequency division
Output pulse. The six-phase pulse signal generated by the logic pulse generating means 3 is
It becomes a trochanter position signal and is input to the stator winding power supply means 4. Stator winding
The force supply means 4 is adapted to output each fixed position according to the rotor position signal output from the logic pulse generation means 3.
A drive current is sequentially supplied to the armature windings 11, 12, and 13 in both directions. The operation of the commutatorless DC motor of the present invention configured as described above will be described in detail.
I will tell. FIG. 2 shows an electric motor according to an embodiment of the present invention and a stator winding power supply constituting the electric motor.
FIG. 3 is a circuit configuration diagram showing an embodiment of the supply means 4, and FIG. 3 is a signal waveform diagram of each part thereof. In FIG. 2, 27 is a permanent magnet rotor, 11, 12, and 13 are stator windings,
1, 22, 23, 24, 25 and 26 are driving transistors and these transistors
The current is supplied to the stator windings 11, 12, and 13 by turning on and off the stator.
Among them, 21, 22, and 23 are PNP transistors, and 24, 25, and 26 are NPN transistors.
It is composed of a transistor. Reference numeral 20 denotes a power supply. Generally, a commutatorless DC motor
For driving, a six-phase pulse signal obtained according to the rotational position of the rotor 27 is used for driving.
This is performed by applying voltage to each base of the transistors 21, 26, 22, 22, 24, 23, and 25.
. The three-phase pulse signal waveforms are shown in FIGS. 3d, e, f, g, h and i. However, each
The directions of the signals applied to the bases of the transistors are PNP transistors 21 and 22.
, 23 in the direction in which current flows, and NPN transistors 24, 25, 26
The flow is added in the direction of inflow. First, the transistors 21 and 25 are turned on and the stator
A current flows through the windings 11 and 12. Next, the transistors 21 and 26 are turned on and the stator
A current flows through the windings 11 and 13. In this way, the phase switching operation is performed sequentially and the permanent magnet
The rotator 27 is rotated. At this time, the stator windings 11, 12, and 13 are shown in FIG.
, K, l are conducted in both directions. The state where the rotor 27 is rotating
Then, each terminal of the stator windings 11, 12, and 13 has a voltage (shown in FIGS. 3A, 3B, and 3C).
Back electromotive force) is induced. Fig. 3 Six-phase pallets indicated by d, e, f, g, h, and i
3 is a position signal of the rotor 27, and the waveforms of the back electromotive forces a, b, and c are shown in FIG.
Note that the phases are as shown, and the phases differ by 30 degrees in electrical angle
It is. Therefore, a rotor position detecting element such as a Hall element is provided as in the present invention.
In order to drive the motor without rotation, back electromotive forces a, b and c induced in the stator winding
A signal that detects the zero-cross point and delays the output pulse by 30 electrical degrees
Processing needs to be performed. The operation of each part of the embodiment of the present invention for performing such signal processing will be described further with reference to the drawings.
This will be described with reference to FIG. FIG. 1 is a circuit diagram of a back electromotive force detecting means 1 according to one embodiment of the present invention shown in FIG.
FIG. In FIG. 4, reference numerals 14, 15, and 16 denote resistors, one of which is a stator winding 11, 12, and 1.
3 are connected to each other, and the other is connected to each other. 31, 32, 33
Is a comparison circuit, whose input terminal (+) is connected to each terminal of the stator windings 11, 12, and 13.
And the common connection point of the resistors 14, 15, 16 is connected to the input terminal (-).
I have. Reference numerals 34, 35 and 36 denote AND circuits, which are comparators 31 and 32 and comparators, respectively.
The outputs of the comparators 32 and 33 and the comparators 33 and 31 are connected. 30 has 3 inputs
The outputs of the AND circuits 34, 35 and 36 are input to the OR circuit. 39 is a
Exclusive OR circuit, the output of OR circuit 30 is directly input to one input
The output signal of the OR circuit 30 is determined by the resistor 37 and the capacitor 38 at the other input.
A signal delayed by a certain time constant is input. The operation of the back electromotive force detecting means 1 shown in FIG. 4 will be described with reference to FIG. 4 are connected to the stator windings 11, 12, and 13, respectively.
Therefore, the stator windings 11, 12 are connected to the common connection point of the resistors 14, 15, 16.
, 13 have the same potential as the neutral point o. Therefore, specially for electric motors
There is no need to draw signal lines from the neutral point of the stator winding. Stator winding 11,
The back electromotive forces a, b, and c induced by the counters 12, 13 are calculated by the comparators 31, 32, 33 shown in FIG.
Is input to the input terminal (+), and the input terminal (-) is shared by the resistors 14, 15, and 16.
The neutral point potential of the stator winding obtained at the connection point is input. Therefore, compare
Back electromotive force as shown in FIG. 5 u, v, w
a, b, and c are waveform-shaped, and the zero-cross point of the back electromotive force a, b, and c and the pulse edge
A matching pulse waveform is obtained. M shown in FIG. 5 constitutes the back electromotive force detecting means 1.
The output waveform of the OR circuit 30 which is a zero-cross point of the three-phase back electromotive force a, b, c.
Outputs a pulse train in which the phases of the rising and falling edges of the pulse match
. FIG. 5 (n) is a waveform obtained by differentiating both edges of the output signal m of the OR circuit 30. Sand
The exclusive OR circuit 39, the resistor 37, and the capacitor 38 both generate pulses.
The exclusive OR circuit 39 has a three-phase differential circuit.
A pulse is output at each zero-cross point of the electromotive force a, b, c, and the back electromotive force a, b, c
A pulse train is output six times (every 60 electrical degrees) in one cycle. FIG.
The rising edge of the output of the pulse delay means 2
7 shows a pulse signal waveform delayed by 30 degrees in electrical angle after the detection of the imaging. Next, the operation of the pulse delay means 2 in one embodiment of the present invention will be described in detail.
You. FIG. 6 is a circuit configuration of the pulse delay means 2 in one embodiment of the present invention shown in FIG.
FIG. 7 (a) is a signal waveform diagram of each part of the electric motor during steady rotation, and FIG. 7 (b)
() Is a signal waveform diagram of each part when the motor is started. In FIG. 6, 41 is a first counting means, 42 is a second counting means,
Reference numeral 4 denotes a clock pulse generator. The first counting means 41 stores the count value.
When the predetermined value is exceeded, the carry flag t is output, and the second counting means 42 outputs the carry flag t.
Outputs a zero flag z when the count value of the zero becomes zero. Clock pulse generation means
44 generates two types of clock pulses ck and ck2, and generates a clock pulse c
k is the clock pulse ck2 (the clock frequency is c
(2 times k) is input to the second counting means 42. 43 is a transfer means,
The pulse train n output from the electromotive force detecting means 1 and the key output from the first counting means 41
And the first counting means 41 resets the counted value.
The reset pulse r to the second counting means 42 is supplied to the first counting means 41.
And outputs a load pulse s for loading the count value. Regarding the operation of the pulse delay circuit 2 shown in FIG.
The case of normal rotation will be described with reference to FIG. 1st counting hand
The stage 41 keeps the clock pulse until the reset pulse r output from the transfer means 43 is input.
Count up Rusck. The reset pulse r is output by the back electromotive force generating means 1.
Since the period is the same as that of the pulse train n, the count value of the first counting means 41
This means that the cycle of the pulse train n output from the power detection means 1 has been counted. How it looks
The count value is analogously indicated by p in FIG. 7 (a). Second counting means 42
The first counting operation is performed at the timing of the load pulse s output from the transfer means 43.
The count value p of the stage 41 is transferred as an initial value. The second counting means 42
Since the count value p obtained by counting the cycle of the loose train n is down-counted by the clock of ck2, the count value becomes zero at the middle point of the pulse train of the load pulse s (or n). So
Is analogously indicated by qa in FIG. 7 (a). Second counting means 4
2 is configured to output a zero flag when the count value is zero.
7 outputs a delay pulse z as shown by z in FIG. 7 (a).
The pulse train n is a pulse output from the back electromotive force detecting means 1 and is a three-phase stator winding 11,
Indicates the zero cross point of the back electromotive force a, b, c induced in 12, 13
Thus, the interval between the pulse trains n and s is equivalent to 60 electrical degrees. Therefore, the seventh
The rising edge of z shown in FIG. 7A is from the zero cross point of the back electromotive forces a, b, and c.
This is a delay of 30 degrees in electrical angle. Note that the load pulse s and the reset pulse
As shown in FIG. 7 (a), the reset pulse r is equal to the load pulse s.
But the count value of the first counting means 41 is changed to the second count value.
This is to ensure that the means 42 is transferred. In FIG. 7 (a), the pulses s and r
Although the pulse width is shown large for convenience, it is assumed that it is sufficiently narrower than the pulse period.
You. Next, the operation at the time of starting the motor will be described with reference to FIG. 7 (b). No.
The 1-counting means 41 receives the reset pulse r output from the transfer means 43.
The clock pulse ck is counted up until the clock pulse ck. However, the rotor 27 is stationary
Therefore, the back electromotive force generating means 1 does not output the pulse train n. Therefore, the first
The count value of the counting means 41 monotonically increases as indicated by p in FIG.
When the count value reaches a predetermined value, the carry flag t
Is output to the transfer means 43. The transfer means 43 receives the signal t and receives a reset pulse.
r and load pulse s are output. The second counting means 42 starts with a load pulse s.
After the period value is loaded, it is counted down. And the second counting means 42
Is zero, the zero flag z is output to the logic pulse generating means 3.
When the motor is started, the zero flag z is used to sequentially perform the phase switching operation of the stator winding.
And the permanent magnet rotor 27 starts rotating by the pseudo signal.
. Now, as shown by a dotted line in qa of FIG.
When the count value of the first counting means 41 is received, the second counting means 4
2 as an initial value. In such a configuration, FIG.
b) As is evident from the waveform of the dotted line indicated by qa in FIG.
Before the counted value reaches zero, the count of the first counting means 41 is counted.
Occasionally a number is transferred. In that case, the second counting means 42
The count value does not become zero and the delay pulse z is not output. Therefore, FIG.
No pulse x as shown in z is generated. As a result, the phase switching of the stator winding
The motor is not accelerated properly. Then, as shown by the solid line waveform indicated by qa in FIG.
When received, the count value of the first counting means 41 is used as it is by the second counting means.
42, a predetermined value smaller than the count value of the first counting means 41
Is transferred to the second counting means 42. Then the second counting hand as described above
Before the count value of the stage 42 reaches zero, the count value of the first counting means 41 further increases.
It is not transferred, and the count value of the second counting means 42 is always zero and the delay
Lus z is output. Hereinafter, the second counting means 42 performs the same operation as in the steady state.
Outputs a delay pulse z as shown by z in FIG. 7 (b),
In addition to the pulse generating means 3, the three-phase stator windings 11, 1
Switching of the energized phases 2 and 13 is performed sequentially. The motor is then accelerated and a good start
Dynamic characteristics are obtained. FIG. 8 shows another embodiment of the pulse delay means 2 in the embodiment of the present invention shown in FIG.
FIG. 9 (a) is a main part circuit configuration diagram of the example, and FIG.
FIG. 9 (b) is a signal waveform diagram of each part when the motor is started. 6 having the same functions as those in FIG.
Description is omitted. In FIG. 8, reference numeral 41 denotes a first counting means constituted by an 8-bit counter;
2 is a digital counter which is a second counting means composed of a 5-bit counter.
It is configured. The first counting means 41 and the second counting means 42 respectively
And the same clock ck is input. The first counting means 41 outputs the clock c
k, and the second counting means 42 counts down the clock ck.
To Reference numeral 45 denotes a switch transfer circuit composed of five switches.
Is connected to the left contact for a short time by the load pulse s, and 5 bits excluding the least significant bit of the counted value of the first counting means 41 are transferred to the second counting means 42.
. Also, the count value of the first counting means 41 overflows and the first count
When the carry flag t is output from the means 41, the short-time switch transfer circuit 4
5 is connected to the right contact and all bits of the second counting means 42 are set to "1".
Is set. The operation of the pulse delay circuit shown in FIG.
The case of turning will be described with reference to FIG. 9 (a). During steady rotation
It is assumed that the upper two bits of the first counting means 41 are "0". The second count means 42 has a timing of the load pulse s output from the transfer means 43.
The counting value p of the first counting means 41 is transferred by the counting. However, the second count
Only the least significant bit of the first counting means 41 is discarded and transferred to the
Therefore, as shown by pb in FIG. 9A, the initial value of the second counting
Is that the value of 1/2 of the count value p of the first counting means 41 is given as an initial value.
And The second counting means 42 calculates a half of the count value obtained by counting the period of the pulse train n.
Since p / 2 corresponding to the minute is counted down by the clock ck,
The count value becomes zero at the middle point of the row n. Therefore, the second counting means 42
9 outputs a delay pulse z as shown in FIG. Therefore, FIG.
The rising edge of the delay pulse z shown is from the zero cross point of the back electromotive forces a, b, and c.
That is, it is delayed by 30 degrees in electrical angle. Next, the operation at the time of starting the motor will be described with reference to FIG. 9 (b). Ki
During operation, the back electromotive force detection means 1 does not output the pulse train n.
Stage 41 continues to count up clock pulse ck. Therefore, the first power
The count value of the counting means 41 monotonically increases as shown by p in FIG.
When the numerical value overflows, the carry count t is output from the first counting means 41.
It is output and input to the transfer means 43 and the switch transfer circuit 45. The transfer means 43
Upon receiving the signal t, a reset pulse r and a load pulse s are output. Second cow
The loading means 42 is loaded with the initial value by the load pulse s.
As shown by a dotted line in qb, a 7-bit counter is prepared as the second counting means.
When the transfer means 43 receives the signal t, the value of p / 2 (upper 7 bits) which is half of the count value of the first count means 41 is initially sent to the second count means 42 as it is.
It shall be transferred as the term value. When configured as described above, FIG. 9 (b)
As can be seen from the waveform of the dotted line indicated by qb in FIG.
Stage 42 counts down to a first count before its count reaches zero.
A case occurs where the count value of the means 41 is further transferred. In that case, the second counsel
The count value of the reset means 42 does not become zero and the delay pulse z is not output. Therefore,
9 A pulse x as shown by z in FIG. 9B is not generated. As a result, the stator winding phase
Switching is not performed well, and acceleration of the motor is not performed well. Therefore, as shown by the solid line waveform indicated by qb in FIG.
Receives a signal t, p / 2 which is half of the count value of the first counting means 41
In this case, the upper 7 bits excluding the least significant 1 bit are used in the second counter.
Instead of transferring to the switch means 42, the switch transfer circuit 45
Is half of the count value of the first counting means 41 by connecting to the side contact.
A predetermined value smaller than the value of p / 2, in this case, 5 bits in which all bits are “1”
The data is transferred to the second counting means 42. Then, as described above, the second camera
Before the count value of the counting means 42 reaches zero, the count value of the first counting means 41
Is not transferred further, the count value of the second counting means 42 is always zero.
The delay pulse z is output. Hereinafter, the second counting means 4 operates in the same manner as in the steady state.
2 outputs a delay pulse z as shown by z in FIG.
Is applied to the logic pulse generating means 3 and the three-phase fixed
The energization phases of the stator windings 11, 12, and 13 are sequentially switched. And the motor is
Speed and good start-up performance. In the pulse delay means shown in FIG. 6, a clock supplied to the first and second count means is used.
Although the frequency of the clock is different, the pulse delay means shown in FIG.
There is an advantage that. FIG. 10 is a circuit diagram of another embodiment of the pulse delay means 2 of the present invention shown in FIG.
FIG. 11 (a) is a signal waveform diagram of each part of the rotor during steady rotation of the rotor, and FIG. 11 (
FIG. 4B is a signal waveform diagram of each part when the motor is started. Components having the same functions as those in FIGS. 6 and 8 are denoted by the same reference numerals, and duplicate description will be omitted. In FIG. 10, 61 is a first up / down counting means, and 62 is a second
It is a means for counting down. The first up / down counting means 61, the second
The up / down count means 62 has an up count input CU and a down count, respectively.
There is a unt input CD. The first up / down counting means 61 and the second
The up / down counting means 62 counts up and the counted value overflows.
In some cases, carry flags ta and tb are output, respectively, and counted down.
When the value becomes zero, zero flags za and zb are output, respectively. 6 is an OR circuit
, Two signals of carry flags ta and tb are input, and a signal t is output. 63
Is a clock switching circuit, which outputs two types of clock signals generated by the clock generating means 44.
Lus ck, ck2 (clock frequency is twice ck) as up-count input CU
Output from the back electromotive force detecting means 1
The switching is alternately performed according to the pulse n to be performed and the signal t output from the OR circuit 6. 64 is Oh
In the circuit, each of the first and second up / down counting means 61 and 62 outputs
And outputs a delayed pulse z. Regarding the operation of the pulse delay circuit shown in FIG.
The case of rotation will be described with reference to FIG. First, assume that the switch of the clock switching circuit 63 is at the position shown in FIG.
You. Then, the up count input CU of the first up / down count means 61 is
Until the clock ck is supplied and the pulse n is input to the clock switching circuit 63
The first up / down counting means 61 performs an up counting operation. Next pulse
first up / down counting means when n is input to the clock switching circuit 63
Reference numeral 61 switches to a down-count operation. In addition, the clock switching circuit 63
The clock supplied to the count input is ck2, and the clock frequency is CK.
Is input. Therefore, the period of the pulse train n is counted up.
The counted value is counted down by the clock of ck2.
The count value becomes zero at the point. This is shown in pa of FIG. 11 (a). As a result,
The up / down counting means 61 of 1 is a zero flag z as shown in FIG.
a is output. Similarly, the second up / down counting means 62 repeats the up / down counting operation as shown by pb in FIG.
Output a zero flag as shown. Since za and zb occur alternately, the OR circuit 6
4 outputs a signal z as shown in FIG. 11 (a) and the pulse delay shown in FIG.
The means is that the rising edge is just electric from the zero cross point of the back electromotive force a, b, c.
The delay signal z delayed by 30 degrees in the angle will be output. Next, the operation at the time of starting the motor will be described with reference to FIG. First, it is assumed that the switch 63 of the clock switching circuit was at the position shown in FIG.
I do. The first up / down counting means 61 outputs the power output from the back electromotive force generating means 1.
The clock pulse ck is counted up until the pulse n is input. But times
Since the trochanter is stationary, the back electromotive force generating means 1 does not output the pulse train n. But
Therefore, the count value of the first up / down counting means 61 is represented by pa in FIG. 11 (b).
As shown in the figure, the value increases monotonically, and when the count value overflows, the first upload is performed.
The carry flag ta is output from the count counter 61 to the clock switching circuit 63.
Is forced. Then, the clock switching circuit 63 performs the first
Of the up / down counting means 61 from the up / down counting operation.
Switch to the default operation. Moreover, the clock supplied to the down count input is CK2.
Since the clock frequency is twice as high as that of ck, the counted value counted up
The count is down-counted by the clock of K2, and the count value eventually becomes zero. The situation is the first
1 This is indicated by pa in FIG. As a result, the first up / down counting means 61
11 Outputs a zero flag za as shown in FIG. Similarly the second updow
The counting means 62 also counts up and down as indicated by pb in FIG. 11 (b).
The operation is repeated to output a zero flag as indicated by zb in FIG. 11 (b). z
Since a and zb are generated alternately, the OR circuit 64 outputs a signal as shown in FIG.
The signal z is output. The pulse signal z shown in FIG.
It corresponds to a similar signal. Hereinafter, the pulse signal z is applied to the ethical pulse generating means 3,
The current supply phases of the three-phase stator windings 11, 12, and 13 are sequentially switched by the power supply means 4.
Done. The motor is then accelerated and good starting characteristics are obtained. In the pulse delay means shown in FIG. 6 and FIG.
A transfer means for transferring the value to the second counting means is required, but the pulse delay means shown in FIG.
There is an advantage that only the switching of the down-counting operation needs to be performed. FIG. 12 is a circuit diagram of the logic pulse generating means 3 of the present invention shown in FIG.
The figure is a signal waveform diagram of each part. In FIG. 12, reference numeral 80 denotes a six-phase ring counter, t1, t2 shown in FIG.
, T3, t4, t5, and t6. The pulse signal
The loose width is 60 electrical degrees. 81, 82, 83, 84, 85 and 86 are OR times
On the road, the six-phase pulse signals t1, t2, t3, t4, t5, t of the ring counter 80
6 are input, and the six phases d, e, f, g, h, and i shown in FIGS.
Is output. The pulse width of these signals is 120 electrical degrees.
It is input to the stator winding power supply means 4 shown in FIG. As is clear from the above description, in the non-commutator motor of the present invention, first, the back electromotive force detection is performed.
The output means 1 is configured to reduce the back electromotive forces a, b, and c induced in the stator windings 11, 12, and 13 to zero.
A cross point is detected and converted to a conversion pulse n. The converted pulse n is a pulse delay
In stage 2, the signal is delayed by 30 degrees in electrical angle and converted into a delayed pulse z. Logic pulse emission
The generating means 3 receives the delay pulse z, and receives the six-phase rotational position signals d, e, f, g, and h.
, I. And finally, the power supply means 4 outputs the rotor position signals d, e, f
, G, h, i, the stator windings 11, 12, 13 are shown in FIGS.
Such a driving current is sequentially supplied in both directions, so that the permanent magnet rotor 27 is rotated.
. Therefore, the commutatorless motor of the present invention is a rotor position detecting element such as a Hall element.
A full-wave drive type motor that allows the current flowing through the stator windings to flow in both directions without providing
Can be configured. In the back electromotive force detecting means 1 according to the present invention, as shown in FIG.
In order to detect the neutral point potential 0 of the line, it is performed using three resistors connected in common.
However, it is also possible to use by directly drawing out the signal line from the neutral point of the stator winding of the motor
Needless to say, Further, in the embodiment of the present invention, the stator winding is Y-connected.
Although limited to a certain three-phase motor, the number of phases is not limited to three, and may be any number. Also book
The commutatorless motor of the present invention can also be applied to a motor in which the stator windings are connected by Δ.
It is. Advantageous Effects of the Invention The present invention is configured as described above.
It works. The commutatorless DC motor of the present invention has a counter electromotive force induced in the stator winding by the back electromotive force detecting means.
Since only the zero-cross point of the electromotive force is detected, rotor position detection such as a Hall element is detected.
Full-wave drive that supplies current flowing in the stator winding in both directions without the need for an output element
An electric motor of a dynamic system can be easily configured. Therefore, only one of the stator windings
The stator winding utilization rate is higher than that of the half-wave drive system that supplies
Luke's electric motor can be provided. Furthermore, since a rotor position detecting element such as a conventional non-commutator motor is unnecessary,
The cost is greatly reduced because the complexity of adjusting the mounting position of the
You. Furthermore, since there is no need to mount a rotor position detection element inside the motor, the motor
Can be made ultra-small and ultra-thin without any structural restrictions. Further, the commutatorless DC motor of the present invention has
Since the energized phases of the stator winding are sequentially switched by the output pseudo pulse, special
Good starting characteristics can be obtained without providing a starting circuit. Further, the commutatorless DC motor of the present invention has a counter electromotive force induced in each stator winding.
The time between zero-cross points is always counted, and the next stator to be energized based on the count value
Since the current-carrying phase of the windings is determined, even if the motor speed is changed,
The current phase of the stator winding to be energized does not change and stable drive is always obtained.
It also has the excellent effect of being Therefore, the rotation speed of the motor
It can be applied to applications that need to be changed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of one embodiment of a non-commutator DC motor of the present invention, and FIG. 2 is a motor and a stator winding constituting the motor in one embodiment of the present invention. FIG. 3 is a circuit configuration diagram showing one embodiment of the line power supply means, FIG. 3 is a signal waveform diagram of each part thereof, and FIG. 4 is a circuit configuration showing one embodiment of the back electromotive force detection means constituting one embodiment of the present invention. FIG. 5 is a signal waveform diagram for explaining the operation of one embodiment of the non-commutator DC motor of the present invention, and FIG. 6 is a circuit showing one embodiment of pulse delay means constituting one embodiment of the present invention. Configuration diagram, seventh
FIG. 7A is a signal waveform diagram of each part in the steady rotation, FIG. 7B is a signal waveform diagram of each part at the time of startup, and FIG. 8 is another embodiment of the pulse delay means constituting one embodiment of the present invention. 9 (a) is a signal waveform diagram of each part at the time of steady rotation, FIG. 9 (b) is a signal waveform diagram of each part at the time of startup, and FIG. 10 shows an embodiment of the present invention. FIG. 11 (a) is a circuit configuration diagram showing another embodiment of the pulse delay means which performs the operation, FIG. 11 (a) is a signal waveform diagram of each part in the steady rotation, FIG. FIG. 13 is a circuit diagram showing one embodiment of a logic pulse generating means constituting one embodiment of the present invention, and FIG. 13 is a signal waveform diagram of each part thereof. 1 ... back electromotive force detection means, 2 ... pulse delay means, 3 ... logic pulse generation means,
4 ... stator winding power supply means, 11, 12, 13 ... stator winding, 41 ... first counting means, 42 ... second counting means, 61 ... first up / down counting Means, 62... Second up / down counting means.

Claims (1)

Claims: (1) A plurality of stator windings, back electromotive force detecting means for obtaining a pulse signal train in response to a back electromotive force generated in the stator winding, and a period of the pulse signal train Generates a delay pulse delayed by one half of the period when the value is within a predetermined range, and delays the pulse by a time shorter than one half of the period when the period exceeds a predetermined range. Pulse delay means for generating a delayed pulse, logic pulse generation means for generating a pulse of a plurality of phases in response to an output signal of the pulse delay means, A non-rectifier comprising: a logic pulse generating means for generating a pulse; and a power supply means for supplying power to the stator winding in response to an output signal of the logic pulse generating means. DC motor. (2) The pulse delay unit includes a first counting unit that counts up a cycle of the pulse signal train by up-counting the input clock, and a pulse counting unit that counts a period of the pulse signal train when the count value of the first counting unit is within a predetermined range. A transfer means for transferring the count value, and transferring a value smaller than the count value when the count value exceeds a predetermined range; and a clock for transferring the transferred count value to the first count means. A second counting means for generating a delay pulse when the count value is reduced to zero at a double frequency, and a clock generating means for outputting a clock to the first and second counting means. The commutatorless DC motor according to claim 1, wherein the DC motor is configured. (3) The pulse delay unit includes a first counting unit that counts up a cycle of the pulse signal train by counting up an input clock; and a pulse counting unit that counts a period of the pulse signal train when a count value of the first counting unit is within a predetermined range. Transferring means for transferring a half value of the count value, and transferring a value smaller than half of the count value to a second counting means when the count value exceeds a predetermined range; A second counting means for generating a delay pulse when the counted value is down-counted at the same frequency as the clock input to the first counting means and the counted value becomes zero; 2. The non-rectifier DC motor according to claim 1, further comprising a clock generating means for outputting a clock to the second counting means.