JP2502780B2 - DC motor without commutator - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DC motor without commutator, and more particularly, to eliminate a rotor position detecting element such as a hall element for detecting a rotational position of a permanent magnet rotor. The present invention relates to a DC motor without commutator.

2. Description of the Related Art Non-rectifier DC motors have longer mechanical life and less electrical noise than DC motors with brushes, and at the same time have less electrical noise. Widely applied to audio equipment.

Conventionally, most of the commutatorless DC motors of this type use a rotor position detecting element (for example, a Hall element) corresponding to a brush in order to switch the conduction phase of the stator winding. However, the rotor position detection element itself is by no means inexpensive, and the complicated mounting position adjustment of the element,
The commutatorless DC motor due to the increase in the number of wires has a drawback that the cost is significantly higher than that of the brush DC motor.

Further, the rotor position detection element must be mounted inside the electric motor, so that structural restrictions often occur. In recent years, with the miniaturization of equipment, electric motors used have also become smaller and thinner, and there is no more room for mounting position detection elements such as Hall elements. Therefore, some commutatorless DC motors having no rotor position detecting element such as a hall element have been proposed. One of them is, for example, 3 as disclosed in Japanese Patent Laid-Open No. 55-160993.
In a three-phase non-rectifier DC motor, the back electromotive force induced in the two stationary stator windings is detected to determine the next energized phase, and the current is supplied only in one direction of the stator winding. There is a so-called half-wave drive type non-rectifier DC motor.

Further, as shown in, for example, Japanese Patent Laid-Open No. 62-260586, the zero-cross point of the back electromotive force induced in the stator winding is detected, and its output signal is delayed by a mono-multi for a fixed time to conduct electricity. There is a so-called full-wave drive type non-rectifier DC motor in which the timing is determined and the current is sequentially supplied to each stator winding in both directions.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention In the former commutatorless DC motor shown in the prior art, since the half-wave drive system that supplies the current only in one direction of the stator winding, the driving device is simple. On the other hand, compared to a full-wave drive type motor configured so that the current flowing in the stator windings flows in both directions, the stator winding utilization rate is low, the efficiency is poor, and the generated torque is small. There is a point.

Also, in the latter non-rectifier DC motor shown in the prior art, the pulse generated at the zero-cross point of the back electromotive force induced in the stator winding is delayed by mono-multi for a fixed time to conduct electricity. Is a method to determine the phase,
Since the delay time is constant irrespective of the rotation speed of the electric motor, there is a problem that it is not suitable for applications in which the rotation speed needs to be changed and the applicability is poor.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a full-wave drive type non-rectifier DC motor that does not require a rotor position detecting element and that is configured to allow a current flowing through a stator winding to flow in both directions. A further object of the present invention is to provide a commutatorless DC electric motor capable of arbitrarily changing the rotation speed of the electric motor.

Means for Solving the Problems In order to achieve the above object, the present invention provides a counter electromotive force detecting means for pulse-shaping a counter electromotive force generated in each of a plurality of phases of stator windings to obtain a pulse signal train, A pulse delay unit that delays and outputs a pulse for a predetermined time period that is proportional or approximately proportional to the cycle of the pulse signal train, and a phase switching pulse of a plurality of phases having the same frequency as the counter electromotive force in response to the output signal of the pulse delay unit. It is configured to include a logic pulse generating means to be generated and an output signal of the logic pulse generating means to be a rotational position signal of a rotor, and stator winding power supply means for sequentially energizing the stator winding by this signal. It

Effect of the Invention With the above-described configuration, the present invention constantly counts the time between the zero-cross points of the back electromotive force induced in each stator winding, and based on the count value, the stator winding to be energized next Since the energization phase is determined, the energization phase of the stator winding to be energized next does not change even if the rotation speed of the electric motor is changed, and stable drive can always be obtained. Therefore, it can be easily applied to applications that need to change the rotation speed, and when changing the rotation speed as seen in the conventional non-rectifier DC motor that does not require the rotor position detection element. The drive does not become unstable.

In addition, since only the zero-cross point of the back electromotive force induced in the stator winding is detected, a full-wave drive type electric motor that allows the current flowing in the stator winding to flow in both directions can be configured. . Therefore, it is possible to provide a high-efficiency, high-torque commutatorless DC motor as compared with a half-wave drive type motor.

Embodiment One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a commutatorless DC motor according to an embodiment of the present invention. In FIG. 1, 1
Is a back electromotive force detection means, and the back electromotive force induced in the three-phase stator windings 11, 12, and 13 is input. The counter electromotive force detecting means 1 detects the zero-cross point of the three-phase counter electromotive force and converts the pulse train. This pulse train shows the zero-cross point of the three-phase back electromotive force. The pulse train output by the counter electromotive force detection means 1 is input to the pulse delay means 2. The pulse delay means 2 first counts the cycle of the input pulse train. Then, the input pulse is delayed by about half the counted period. Three
Is a logic pulse generating means, which divides the pulse output from the pulse delay means 2 and outputs a 6-phase pulse having the same frequency as the counter electromotive force induced in the stator windings 11, 12, and 13. The 6-phase pulse signal generated by the logic pulse generating means 3 becomes a rotor position signal and is input to the stator winding power supply means 4. The stator winding power supply means 4 is the logic pulse generation means 3
Depending on the rotor position signal output by
A drive current is sequentially supplied to 2 and 13 in both directions.

The operation of the non-rectifier DC motor configured as above will be described in detail.

FIG. 2 is a circuit drawing showing one embodiment of the electric motor and the stator winding power supply means 4 constituting the electric motor in one embodiment of the present invention, and FIG. 3 is a signal waveform diagram of each part thereof.

In FIG. 2, 27 is a permanent magnet rotor, 11, 12 and 13 are stator windings, and 21, 22, 23, 24, 25 and 26 are driving transistors, which are fixed by turning these transistors ON and OFF. Supply current to the child windings 11, 12, and 13. Among them, the driving transistors 21, 22, 23 are PNP transistors, and 24, 25, 26 are NPN transistors. 20 is a power supply. Generally, when driving a non-rectifier DC motor, a 6-phase pulse signal obtained according to the rotational position of the rotor 27 is used to drive transistors 21, 26,
It is performed by applying it to each of 22, 24, 23, 25 bases. The 6-phase pulse signal waveforms are shown in FIGS. The signal waveforms of d to i in FIG. 3 are the waveforms of d to i shown in FIG. 2, respectively. However, the direction of the signal applied to the bases of the respective transistors is such that the current flows in the PNP transistors 21, 22, 23 and the current flows in the NPN transistors 24, 25, 26. First, the transistors 21 and 25 are turned on, and a current flows through the stator windings 11 and 12. Next, the transistors 21 and 26 become conductive, and a current flows through the stator windings 11 and 13.
Such a phase switching operation is sequentially performed to rotate the rotor 27. At that time, the stator windings 11, 12, 13 are shown in Fig. 3 j, k, l
The current indicated by is applied in both directions. Further, when the rotor 27 is rotating, the voltage (back electromotive force) shown in FIGS. 3A, 3B, 3C is induced at each terminal of the stator windings 11, 12, 13. Third
The 6-phase pulse signals shown in FIGS. D to i are position signals of the rotor 27, and have a phase relationship with the waveforms of the counter electromotive forces a, b, and c as shown in FIG. Note that the phases are different. Therefore, in order to drive the rotor without providing the rotor position detecting element such as the Hall element like the present invention, the zero-cross point of the back electromotive force a, b, c induced in the stator winding is detected. , It is necessary to perform signal processing that delays the output pulse by 30 degrees in electrical angle.

The operation of each unit of one embodiment of the present invention that performs such signal processing will be further described with reference to the drawings.

FIG. 4 is a circuit configuration diagram of the back electromotive force detection means 1 in the embodiment of the present invention shown in FIG.

In Fig. 4, 14, 15 and 16 are resistors and one is a stator winding 1
The terminals 1, 12 and 13 are connected to each other, and the other terminals are commonly connected. Reference numerals 31, 32 and 33 are comparator circuits, the stator windings 11, 12 and 13 are connected to the input terminal (+), and the resistors 14, 15 and 16 are commonly connected to the input terminal (-). The points are connected. 34, 35, 36 are AND circuits, and comparators 31, 32
And the outputs of the comparators 32 and 33 and the comparators 33 and 31 are connected. Reference numeral 30 is a three-input OR circuit to which the outputs of the AND circuits 34, 35, 36 are input.

39 is an exclusive OR circuit, in which the output of the OR circuit 30 is input to one input as it is and the output signal of the OR circuit 30 is delayed by the time constant determined by the resistor 37 and the capacitor 38 to the other input. To be done.

The operation of the back electromotive force detecting means 1 in FIG. 4 will be described with reference to FIG.

Resistors 14, 15, 16 in Fig. 4 are stator windings 11, 12, 13 respectively.
Therefore, the same potential as the neutral point o of the stator windings 11, 12, and 13 is obtained at the common connection point of the resistors 14, 15, and 16. Therefore, it is not necessary for the electric motor to draw the signal line from the neutral point of the stator winding. The back electromotive forces a, b, c induced in the stator windings 11, 12, 13 are input to the input terminals (+) of the comparators 31, 32, 33 in FIG. It is obtained at the common connection point of resistors 14, 15 and 16. The neutral point potential is input. Therefore, the comparator 31, 32, 33
At each output terminal of, the counter electromotive forces a, b, and c are shaped as shown in the waveforms u, v, and w in FIG. A pulse waveform is obtained. The signal waveforms a, b, c, u, v, w, m, n in FIG. 7 are waveforms at respective points shown in FIG. A waveform m shown in FIG. 7 is an output waveform of the OR circuit 30 which constitutes the counter electromotive force detecting means 1, and is a zero cross point of the three-phase counter electromotive forces a, b, and c and the phase of the rising and falling edges of the pulse. The pulse train with the same is output. The waveform m shown in FIG. 7 is the output signal m of the OR circuit 30.
Is a waveform obtained by differentiating both edges. That is, the exclusive OR circuit 39, the resistor 37, and the capacitor 38 form a pulse both-edge differentiating circuit. From the exclusive OR circuit 39, the zero-cross points of the three-phase back electromotive forces a, b, and c A pulse is output every time, and a pulse train is output six times (every 60 degrees in electrical angle) per cycle of the back electromotive forces a, b, and c.

A waveform z shown in FIG. 7 is an output of the pulse delay means 2 and shows a pulse signal waveform whose rising edge is delayed by 30 electrical degrees after detecting the timing of the rising edge of the waveform n.

Next, the operation of the pulse delay means 2 in the embodiment of the present invention will be described in detail.

FIG. 5 is a circuit configuration diagram of the pulse delay means 2 in the embodiment of the present invention shown in FIG. 1, and FIG. 6 is a signal waveform diagram of each part thereof.

In FIG. 5, 41 is the first counting means and 42 is the second counting means.
, And 44 is a clock pulse generating means.
The clock pulse generating means 44 has two types of clock pulses c
k, ck2 are generated, the clock pulse of ck is input to the first counting means 41, and the clock pulse of ck2 (twice the clock frequency ck) is input to the second counting means 42. 43 is a transfer means to which the pulse train n output from the counter electromotive force detection means 1 is input, the first counting means 41 is provided with a reset pulse r for resetting the count value, and the second counting means 42 is provided with a first pulse A load pulse s (which may be the same as the pulse train n output by the counter electromotive force detecting unit 1) for loading the count value of the counting unit 31 is output.

Next, the operation of the pulse delay circuit 2 shown in FIG. 5 will be described with reference to FIG. The first counting means 41 counts up the clock pulse ck until the reset pulse r output from the transfer means 43 is input. Reset pulse r
Has the same cycle as the pulse train n output by the counter electromotive force generating means 1, so the count value of the first counting means 41 means that the cycle of the pulse train n output by the counter electromotive force detecting means 1 is counted. This is shown in FIG. 6p, and the count value is shown in analog form. The transfer means 43 is provided in the second counting means 42.
The count value p of the first counting means 41 is transferred as an initial value at the timing of the load pulse s output by The second counting means 42 counts down the count value p obtained by counting the period of the pulse train n with the clock of ck2, so that the count value becomes zero at the midpoint of the load pulse s (or n). The situation is shown in analog form in FIG. 6 qa. Since the second counting means 42 is configured to output the zero flag when the count value is zero, the second counting means 42 outputs the delay pulse z as shown in FIG. The pulse train n is a pulse output from the counter electromotive force detecting means 1, and the counter electromotive force induced in the three-phase stator windings 11, 12, 13
Since it shows the zero-cross points of a, b, and c, the interval of the pulse train s corresponds to 60 electrical degrees. Therefore, the sixth
The rising edge of the waveform z shown in the figure is delayed from the zero-cross point of the back electromotive forces a, b, and c by exactly 30 electrical degrees. The load pulse s and the reset pulse r
The phase of the reset pulse is the load pulse s as shown in FIG.
The delay is further delayed so that the count value of the first counting means 41 can be reliably transferred to the second counting means 42. Further, although the pulse widths of the waveforms s and r are enlarged in FIG. 6 for convenience, it is assumed to be sufficiently narrower than the pulse period.

FIG. 8 is a circuit diagram of a main part of another embodiment of the pulse delay means 2 in the embodiment of the present invention shown in FIG. 1, and FIG. 9 is a signal waveform diagram of each part. It should be noted that components having the same functions as those in FIG. 5 are designated by the same reference numerals and duplicate description will be omitted.

In FIG. 8, 41 is the first counting means and 42 is the second counting means.
The counting means comprises a digital counter (in the figure, the first counting means is an 8-bit counter and the second counting means is a 7-bit counter). The same clock ck is input to the first counting means 41 and the second counting means 42, respectively. The first counting means 41 counts up the clock ck, and the second counting means 42 counts down the clock ck. Reference numeral 45 is a switch transfer circuit composed of seven switches, which is closed for a short time by the load pulse s of the transfer means 43, and excludes the least significant bit of the count value of the first counting means 41 (7 bits in FIG. 8). ) Is transferred to the second counting means 42.

Next, regarding the operation of the pulse delay circuit shown in FIG.
This will be described with reference to the drawings. The count value p of the first counting means 41 is transferred to the second counting means 42 at the timing of the load pulse s output from the transfer means 43. However, since only the least significant bit of the first counting means 41 is discarded and transferred to the second counting means 42, the initial value of the second counting means 42 as shown by the waveform qb in FIG. Means that a half of the count value p of the first counting means 41 is given as an initial value. The second counting means 42 is p / 2 corresponding to a half of the count value obtained by counting the period of the pulse train n.
Is counted down by the clock ck, the count value becomes zero at the intermediate point of the pulse train n. Therefore, the second counting means 42 outputs the delay pulse z as shown in FIG. Therefore, the rising edge of the waveform z shown in FIG. 9 is delayed by exactly 30 electrical degrees from the zero-cross point of the back electromotive forces a, b, and c.

In the embodiment of FIG. 5, the frequency of the clock supplied to the first and second counting means is different, but in the embodiment of FIG.
It has the advantage of using different types of clocks.

FIG. 10 is a circuit configuration diagram of another embodiment of the pulse delay means 2 in the embodiment of the present invention shown in FIG. 1, and FIG. 11 is a signal waveform diagram of each part thereof.

It should be noted that components having the same functions as those in FIG. 5 are designated by the same reference numerals and duplicate description will be omitted.

In FIG. 10, 61 is a first up / down counting means, and 62 is a second up / down counting means. First
The up-down count means 61 and the second up-down count means 62 each have an up-count input CU and a down-count input CD. Reference numeral 63 denotes a clock switching circuit, which is two kinds of clock pulses c generated by the clock generating means 44.
Whether k or ck2 (clock frequency is twice ck) is supplied to the up-count input CU or the down-count input CD is switched according to the pulse n output from the counter electromotive force detecting means 1. Reference numeral 64 denotes an OR circuit, which receives the zero flags za and zb output from the first and second up / down counting means 61 and 62, and outputs the delay pulse z.

The operation of the pulse delay means shown in FIG. 10 will be described with reference to FIG. First, it is assumed that the switch of the clock switching circuit 63 is in the position shown in FIG. Then, the clock ck is supplied to the up-count input CU of the first up-down count means 61, and the first n is output until the pulse n output from the counter electromotive force detection means 1 is input to the clock switching circuit 63.
The up / down counting means 61 performs up counting operation. Next, when the pulse n is input to the clock switching circuit 63, the first up / down counting means 61 switches to the down counting operation. Moreover, the clock supplied to the down count input by the clock switching circuit 63 is ck2.
(2 · ck). Therefore, since the count value obtained by up-counting the period of the pulse train n is down-counted by the clock of ck2, the count value becomes zero at the midpoint of the pulse train n. This is shown in Fig. 11 pa. As a result, the first up / down counting means 61 outputs the zero flag za as shown in FIG. Similarly, the second up / down counting means 62 also repeats the up / down counting operation as shown in FIG. 11pb and outputs a zero flag as shown in FIG. 11zb. Since za and zb are alternately generated, a signal z as shown in FIG. 11 is output from the OR circuit 64, and the pulse delay means shown in FIG. 10 has a rising edge whose zero-cross point is the counter electromotive force a, b, c. Therefore, the delay signal z delayed by 30 electrical degrees is output.

In the embodiment shown in FIGS. 5 and 8, transfer means for transferring the count value of the first counting means to the second counting means is required, but in the embodiment shown in FIG. There is an advantage that the switching circuit only needs to switch between up-counting and down-counting operations.

FIG. 12 is a circuit configuration diagram of the logic pulse generating means 3 in the embodiment of the present invention shown in FIG. 1, and FIG. 13 is a signal waveform diagram of each part thereof.

In FIG. 12, reference numeral 80 denotes a 6-phase ring counter, which outputs a 6-phase pulse signal of t1, t2, t3, t4, t5, t6 shown in FIG. The pulse width of these pulse signals is 60 degrees in electrical angle. 81,82,83,84,85,86 are OR circuits, and ring counter 8
The 6-phase pulse signals t1, t2, t3, t4, t5, t6 of 0 are input, and the 6-phase position signals of d, e, f, g, h, i shown in FIGS. 7 and 13 are input. Is output. The pulse width of these signals is 12 electrical degrees.
It is 0 degrees. The 6-phase pulse signals d to i become position signals of the rotor 27 and are input to the stator winding power supply means 4 of FIG.

As is clear from the above description, in the non-rectifier motor of the present embodiment, the counter electromotive force detecting means 1 is the zero-cross point of the counter electromotive forces a, b, c induced in the stator windings 11, 12, 13. Is detected and converted into a converted pulse n, and the converted pulse n is delayed by an electrical angle of 30 degrees in the pulse delay means 2 to obtain a delayed pulse z.
Is converted to. The logic pulse generating means 3 receives the delayed pulse z and produces the six-phase rotational position signals d to i. Finally, the power supply means 4 sequentially supplies the stator windings 11, 12, 13 with drive currents as shown in FIG. 3, j, k, l in both directions in accordance with the rotor position signals d to i. As a result, the rotor 27 is rotated.

Therefore, the commutatorless motor of the present invention can be configured as a full-wave drive type motor capable of flowing the current flowing through the stator winding in both directions without providing a rotor position detecting element such as a hall element.

The counter electromotive force detecting means 1 according to the present invention uses three commonly connected resistors to detect the neutral point potential o of the stator winding, as shown in FIG. It goes without saying that it is also possible to directly use the signal line from the neutral point of the stator winding of the electric motor. Further, in the embodiment of the present invention, the stator winding is limited to a three-phase electric motor having a Y connection, but the number of phases is not limited to three and any number of phases may be used. Further, the commutatorless motor of the present invention can also be applied to a motor in which the stator winding is Δ-connected.

Also, in this embodiment, the pulse delay means is
Although the configuration has been described in which the period is delayed, it is needless to say that the effect of the present embodiment can be obtained for a 1 / N (N is an integer) period, and the clock frequency input to the second counting means is the first frequency. The frequency is not limited to twice the frequency of the clock input to the counting means, and may be an integral multiple.

Further, in the present embodiment, the transfer means is configured so that a half of the count value of the first count means is transferred to the second count means. N may be configured as an integer).

Further, the first and second up / down counting means are configured such that the clock frequency input to one count input terminal is not limited to twice the clock frequency input to the other count input terminal but is an integral multiple. Good.

EFFECTS OF THE INVENTION Since the present invention is configured as described above,
The following effects are obtained.

Since the non-rectifier DC motor of the present invention detects only the zero-cross point of the back electromotive force induced in the stator winding by the back electromotive force detection means, a rotor position detection element such as a hall element is unnecessary. However, the full-wave drive type electric motor that supplies the current flowing in the stator winding in both directions can be easily configured. Therefore, the utilization rate of the stator winding is higher than that of the half-wave drive method that supplies current only in one direction of the stator winding,
It is possible to supply an electric motor with high efficiency and high generated torque.

Further, since a rotor position detecting element like the conventional non-commutator motor is not required, the complexity of adjusting the mounting position of the element and the number of wirings are reduced, so that the cost is significantly reduced.

Furthermore, since it is not necessary to mount a rotor position detecting element inside the electric motor, the electric motor is not restricted in structure and can be made extremely small and thin.

Further, the non-rectifier DC motor of the present invention constantly counts the time between zero cross points of the back electromotive force induced in each stator winding, and based on the count value, the stator winding to be energized next. Since the energization phase of the wire is determined, the energization phase of the next stator winding to be energized does not change even when the number of rotations of the motor is changed, and stable driving can be always obtained. It also has the effect. Therefore, the present invention can be applied to applications where it is necessary to arbitrarily change the rotation speed of the electric motor.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a non-rectifier DC motor of the present invention, and FIG. 2 is an implementation of an electric motor and a stator winding power supply means constituting the motor in an embodiment of the present invention. FIG. 3 is a circuit configuration diagram showing an example, FIG. 3 is a signal waveform diagram of each part shown in FIG. 1 and FIG. 2, and FIG. 4 is a circuit showing one embodiment of a back electromotive force detecting means constituting one embodiment of the present invention. FIG. 5 is a circuit diagram showing an embodiment of the pulse delay means constituting the present invention, FIG. 6 is a signal waveform diagram of each part in FIG. 5, and FIG. 7 is a commutatorless DC motor of the present invention. 8 is a signal waveform diagram for explaining the operation of one embodiment of the present invention, FIG. 8 is a circuit configuration diagram showing another embodiment of the pulse delay means constituting the present invention, FIG. 9 is a signal waveform diagram of each part thereof, and FIG. Is a circuit configuration diagram showing another embodiment of the pulse delay means constituting the present invention, FIG. 11 is a signal waveform diagram of each part thereof, and FIG. 12 is Circuit diagram showing an embodiment of a logical pulse generating means constituting the present invention, FIG. 13 is a signal waveforms diagram of Figure 12. 1 ... Back electromotive force detection means, 2 ... Pulse delay output, 3 ...
... Logic pulse generating means, 4 ... stator winding power supply means, 11, 12, 13 ... stator winding, 41 ... first counting means, 42 ... second counting means.

 ─────────────────────────────────────────────────── --- Continuation of the front page (56) Reference JP-A-54-146944 (JP, A) JP-A-58-29380 (JP, A) JP-A-62-260586 (JP, A) JP-A-63- 11085 (JP, A) JP-A 1-122387 (JP, A) JP-A 1-234090 (JP, A)

Claims (13)

(57) [Claims] 1. A multi-phase stator winding, a counter electromotive force detecting means for obtaining a pulse signal train in response to a counter electromotive force generated in the stator winding, and a proportional or substantially proportional cycle of the pulse signal train. Pulse delay means for generating a delay pulse delayed by a proportional time, logic pulse generating means for generating a plurality of phase pulses in response to the delay pulse, and the fixed in response to an output signal of the logic pulse generating means. A non-rectifier DC motor, comprising an electron supply means for supplying electric power to a child winding. 2. The non-rectifier according to claim 1, wherein the pulse delay means is configured to output a delayed pulse delayed by a time that is an integral fraction of the period of the pulse signal train. DC motor. 3. The pulse delay means is 2 times the cycle of the pulse signal train.
The non-rectifier DC motor according to claim (1), which is configured to output a delay pulse delayed by a fraction of a time. 4. The pulse delay means includes a first count means for counting the period of the pulse signal train, a transfer means for transferring the count value of the first count means to the second count means, and a transferred means. Second counting means for outputting a delayed pulse delayed from the count value by a time proportional or substantially proportional to the cycle of the pulse signal train; and clock generating means for inputting a clock to the first and second counting means. The commutatorless DC motor according to claim 1, wherein the DC motor is a commutator. 5. The clock frequency input to the second counting means is different from the clock frequency input to the first counting means.
DC motor without commutator described. 6. The non-commutator DC according to claim 4, wherein the clock frequency input to the second counting means is an integral multiple of the clock frequency input to the first counting means. Electric motor. 7. The non-rectifier DC according to claim 4, wherein the clock frequency input to the second counting means is twice the clock frequency input to the first counting means. Electric motor. 8. The transfer means is configured to transfer to the second count means an integer fraction of the count value of the first count means. DC motor without commutator. 9. The transfer means is configured to transfer a half of the count value of the first counting means to the second counting means. DC motor without commutator. 10. The pulse delay means switches between an up-counting operation and a down-counting operation in response to a pulse generated by a back electromotive force detecting means, and when one is an up-counting operation, the other is a down-counting operation. The non-rectifier according to claim 1, further comprising a second up / down counting means and a clock generating means for inputting a clock to the first and second up / down counting means. DC motor. 11. The first and second up / down counting means each have an up-count input terminal and a down-count input terminal, and a clock frequency input to the up-count input terminal is input to the down-count input terminal. 11. The non-rectifier DC motor according to claim 10, wherein different clock frequencies are set. 12. The first and second up / down counting means each have an up-count input terminal and a down-count input terminal, and a clock frequency input to one count input terminal is input to the other count input terminal. 11. The non-rectifier DC motor according to claim 10, wherein the input clock frequency is an integral multiple. 13. The first and second up / down counting means each have an up-count input terminal and a down-count input terminal, and a clock frequency input to one count input terminal is input to the other count input terminal. 11. The non-rectifier DC motor according to claim 10, wherein the input clock frequency is doubled.