KR940009105B1 - Method and apparatus for memory access on multiprocessor system - Google Patents

Abstract

The device uses an access arbitration logic (20) for time-sharing access and parallel access of global memories (14,15). The local memories (12-2,13-2) for each processor are each composed of DRAM. The device contains a DRAM control module (6,7) for an access and a refresh control of the local memories (12-2,13-2) and the global memories (14,15), a H/P control module (2) and a P/P control module (5) for communication between processors to conduct a memory access based on a predefined protocol.

Description

Memory Access Control Devices and Methods in Multiprocessor Systems

1 is a block diagram of a memory access controller of a conventional multiprocessor system.

2 is a block diagram of a memory access controller of a multiprocessor system of the present invention.

3 is a buffer control logic diagram by memory arbitration means in the apparatus of the present invention.

4 is a flowchart showing an access control method of the present invention.

* Explanation of symbols for main parts of the drawings

1: host computer 3, 4: processor

6,7: DRAM controller 14,15: Global memory

20: access arbitration

The present invention relates to a memory access device of a multiprocessor system in which two processors are capable of simultaneously accessing global memory or time sharing access.

As shown in FIG. 1, a conventional multiprocessor memory access device includes a processor (101, 102) for performing data processing with a dedicated program while performing communication with the host computer (100), and each processor (101). The local memory 103, 104, which is a dedicated memory of the 102, and the global memory unit 109, which is a shared memory, are composed of an EPROM 105, 107 in which a boot program is stored. And SRAMs 106 and 108 in which executable programs and data are stored, and the global memory unit 109 includes two independent global memories (DRAM 110 and 111) and a processor (101, 102). 111 is composed of an access arbitration unit 112 (Arbitration Logic) to arbitrate when accessing the operation thereof is as follows.

The program to be executed in the processor 101, 102 is downloaded from the host computer 100 to the SRAM 106, 108 by the boot program of the EPROM 105, 107, and the processor 101, 102 is each dedicated. The program is performed with a program. First, when the task of the first module is completed from the processor 101 to the execution program of the SRAM 106, the result is transmitted to the processor 102 and the next task is performed. When the task of the processor 101 is finished, the next task is executed by the execution program of the SRAM 108 with the received information, and the result is transmitted to the host computer 100. At this time, the processor 102 waits for the operation of the processor 101 to end, and when the operation is completed, receives the information and proceeds to the next operation.

On the other hand, the data necessary to perform the work between the tasks of the processor 101, 102 as described above is stored in the DRAMs 110 and 111 of the global memory unit 109, and the data necessary to perform the work in each of the DRAMs 110 and 111. Are respectively input to the opposite DRAMs, whereby access of the memory 110, 111 causes a data collision in the access arbitration unit 12 responsible for arbitrating access of the DRAM 110, 111 to each processor 101, 102. Excluded.

However, the memory access device of such a conventional multiprocessor system cannot access global memory in time-sharing at the same time as each processor performs independent tasks. The longer the time, the more inefficient, the data processing speed is reduced, the global memory is composed of DRAM and the local memory is composed of SRAM, there is a problem that the cost associated with operating the system increases.

According to the present invention, access arbitration logic is configured to simultaneously access global memory in each processor in a time-division manner, and a working memory of a local memory is configured as DRAM using one DRAM controller per processor. By performing the memory access according to protocol, time division and parallel data processing are possible, and the data processing efficiency and speed can be improved accordingly, and the working memory of local memory and global memory is composed of DRAM. It is an object of the present invention to provide a memory access control apparatus and a control method thereof that can reduce the system operating cost, and will be described below with reference to the configuration of the present invention with reference to FIG.

That is, the memory access control apparatus of the multiprocessor system of the present invention includes a host computer 1, an H / P control unit 2 that is in charge of communication control between the processors 3, 4, and each processor 3; 4) and a DRAM controller 6 for access and refresh control of the local DRAMs 12-2 and 13-2 and the global memories 14 and 15; 7), address drivers 8 and 9 for supplying the addresses of the processors 3 and 4 to the local EPROMs 12-3 and 13-3 and the SRAMs 12-4 and 13-4, and access arbitration. The tri-state multiplexers 10 and 11 supplying one of the DRAM control signals of the processors 3 and 4 to the global memories 14 and 15 according to the control of the unit 20, and each of the processors 3 and 4, respectively. Local memory (12, 13) in which data for dedicated program processing is stored / decoded, global memory (14, 15) consisting of DRAM, and global memory (14, 15) desired by each processor (3, 4). Access Two-way buffers 16, 17, 18, and 19 that are capable of switching, and an access arbitration unit 20 that arbitrates access to time-divisionally or global memory 14, 15 by each processor 3, 4; It consists of

On the other hand, the H / P controller 2 is a dual port memory (2-1) (DPRAM) for temporarily storing and controlling the data to communicate, and the status controller (2-2) for controlling the state of each processor and , The DPRAM controller 2-3 for generating a control signal for accessing the DPRAM 2-1, the unidirectional buffers 2-4 and 2-5 for address path control between the host and the processor, and data path control. It consists of a two-way buffer (2-6) for. The P / P controller 5 comprises a dual port memory 5-2 in which data between processors is stored / decoded, and a status controller 5-1 for controlling the state of data communication control.

The local memory 12 of the processor 3 includes a unidirectional buffer 12-1 for driving the DRAM control signal, a DRAM 12-2 which is a dedicated working memory of the processor 3, and an initial booting of the system. EPROM 12-3, which downloads and stores programs to be initialized and executed in each module, and stores them in the SRAM 12-4 or jumps to service routines when interrupted, and initially from the host computer. An SRAM 12-4 which stores a program to receive a program and performs a necessary task, and a bidirectional buffer 12-5 for driving data of the DRAM 12-2 and the EPROM 12-3.

The local memory 13 of the processor 4 includes a unidirectional buffer 13-1 for driving the DRAM control signal, a DRAM 13-2 which is a dedicated working memory of the processor 4, and an initial booting of the system. EPROM 13-3, in which a program for downloading and storing a program to be initialized and executed at each time is downloaded and stored in the SRAM 13-4, or jumpable as an interrupt service routine, and a program from a host computer initially. And an SRAM 13-4 in which a program is stored so as to perform a necessary task, and a bidirectional buffer 13-5 for driving data of the DRAM 13-2 and the EPROM 13-3.

The memory access operation by the apparatus of the present invention configured as described above is described with reference to FIGS. 2 to 4. First, data processing operations of each of the processors 3 and 4 and the local memory 12 and 13, and second, each processor 3. 4) data processing operation between the global memory (4, 5), third, communication operation between the host computer 1 and each processor (3, 4), fourth, communication operation between the processor (3, 4) By:

First, the data processing operation between the processors 3 and 4 and the local memory 12 and 13 will be described. The boot program exists in the EPROMs 12-3 and 13-3. This operation is executed to initialize each processing module, and downloads an execution program from the host computer 1 and stores it in the SRAMs 12-4 and 12-5.

In addition, EPROMs 12-3 and 13-3 have interrupt service routines for handling interrupts when they occur, and are configured to jump to the program areas to be executed in SRAMs 12-4 and 13-4 when programs are executed. It is.

Execution programs are stored in the SRAMs 12-4 and 13-4. These programs are received from the host computer 1 and each processor 3 and 4 performs a desired task. To secure.

The DRAMs 12-2 and 13-2 are used as working memories of an execution program and are subjected to data read / write and refresh control by the DRAM controllers 6 and 7 which are controlled by the processors 3 and 4, and have high-speed access. The method can be used to run quickly.

On the other hand, the address driver 8, 9 (unidirectional buffer) is always in an enabled state, and drives the addresses PE1 (A) and PE2 (A) output from the processors 3 and 4 to drive the EPROMs 12-3 and 13. -3) and addresses (buffered addresses) (PE1 (BA), PE2 (BA)) of the SRAMs 12-4 and 13-4.

Unidirectional buffers 12-1 and 13-1 are enabled only when processor 3 and 4 accesses local DRAMs 12-2 and 13-2 to strobe the DRAMs 12-2 and 13-2. The signals and addresses are driven and supplied to the DRAMs 12-2 and 13-2 as drive signals PE (LMA) and PE2 (LMA).

When refreshing the DRAMs 12-2 and 13-2 simultaneously with the buffers 10 and 11 for driving the strobe signals and the addresses GM0 (A) and GM1 (A) of the global DRAMs 14 and 15. Enabled to allow simultaneous refreshing by the DRAM controllers 6 and 7 of each processor 3 and 4.

The interactive buffers 12-5 and 13-5 are only enabled when accessing the EPROMs 12-3 and 13-3 or DRAMs 12-2 and 13-2 and read / write of the processors 3 and 4. Depending on the state, the direction is determined to transfer data (PE1 (LD), PE2 (LD)) and avoid collisions with other data buses.

In this way, each of the processors 3 and 4 accesses the local memory 12 and 13 through the data PE1 (D) and PE2 (D) and the addresses PE1 (A) and PE2 (A).

The following describes data processing operations between the global memories 14 and 15 and the processors 3 and 4.

First, each processor 3, 4 defines a global memory status control register in DPRAM 5-2 so that each processor 3, 4 decodes the set state of the register so that the global memory 14, 15) determine the access method.

When one processor (3, 4) accesses one global memory (14, 15), select the global memory to access and set it in the memory flag, and access is set by setting the start flag (ON) at the start of access. When the access is completed, the start flag is reset (OFF) so that each of the processors 3 and 4 accesses the global memories 14 and 15 simultaneously or in time division.

That is, the process shown in the access control method of FIG. 4 is performed by accessing the global memories 14 and 15 so that each processor 3 and 4 refers to the memory flag in the status registers of the other processors to which the processor is accessing. If the global memory to be accessed and the global memory being accessed by the other processor are different from each other, the parallel processing is possible by setting the memory flag and start flag and then reading / writing the global memory. If the global memory to be accessed is the same, time slot access is performed by setting the memory flag and the start flag after performing the global memory access after waiting until it is turned off by referring to the start flag again.

On the other hand, the access arbitration unit 20 is a tri-state multiplexer 10 so that each processor (3, 4) can normally access the global memory (14, 15) in accordance with the global memory status control register value of the DPRAM (5-2). 11, bidirectional buffers 12-5, 13-5, (16, 17, 18, 19), and unidirectional buffers 12-1, 13-1.

As shown in Fig. 3, the control logic outputs of the tri-state multiplexers 10 and 11 for driving the strobe signals and the address signals to be input to the respective DRAMs 14 and 15 are the DRAM controllers of the processors 3 and 4, respectively. The tri-state multiplexers 10 and 11 are controlled to select and output only one of the signals generated from (6, 7), and the memory to be accessed among the two-way buffers 16, 17, 18, and 19 for the data drive. Enable only the desired buffers to turn on the data bus with the controller, and control the local DRAMs 12-2 and 13-2 and the global memories 14 and 15 to be simultaneously accessed (refreshed) at the time of refresh Enables input of signals to enable unidirectional buffers 12-1 and 13-1 and multiplexers 10 and 11. In this case, the DRAM controllers 6 and 7 generate control and strobe signals and addresses necessary for accessing the local DRAMs 12-2 and 13-2 or the global memories 14 and 15. -2, 13-2, 14, 15 generate the refresh control signals to operate in the refresh mode.

Communication between the host computer 1 and the processor 3, the host computer 1, the processor 2, and each of the processors 3 and 4 is performed using DPRAM according to a predefined communication protocol.

That is, the DPRAM 2-1 is address-mapped to the local memory 12 and 13 of each processor to communicate by accessing this part. The communication protocol is based on the lower 4 bits of the host instruction. If the lower 4 bit value is "1", the program or data of the host computer 1 is transmitted to each processor (3, 4). If "2", the program or data of each processor (3, 4) is transmitted. Received by the host computer 1, if "3", initialize each processor (3, 4), if "4", execute the program of each processor (3, 4), "5" The host computer 1 receives the stack pointer of each of the processors 3 and 4, and the host computer 1 transmits the stack pointer to each of the processors 3 and 4, if it is “6”. Is stored in the stack of each processor (3, 4). If "8", the memory of each processor (3, 4) is diagnosed. , If "9", the control register of each processor (3, 4) is processed to read and write this value in the DPRAM (2-1), the host computer (1) ) And communication between the processors 3 and 4.

In addition, the processor performs communication between the processors with the lower 4 bits of the instruction. In the case of “1X”, the host computer 1 communicates with the processor 3, and in the case of “2X”, the host computer 1 communicates with the processor. Communication with the processor 4, in the case of “3X”, is established by communication between the processors 3 and 4.

Communication control between the host computer 1 and each of the processors 3 and 4 and the processors 3 and 4 in accordance with the communication protocol depends on the address mapping of the DPRAM 2-1 as described above. Communication is performed by recording and decrypting control command data from 1) or in response to addresses from the processors 3 and 4.

It drives the data through the buffer 2-6, drives the addresses through the buffers 2-4 and 2-5, controls the control state by the status control unit 2-2, and the DPRAM control unit 2-3. Is performed through enable control of the DPRAM 2-1.

As described above, according to the present invention, when a plurality of processors access a shared memory to perform a task, when the workload is concentrated on a specific processor, the workload can be efficiently distributed, and the local memory and the global memory are DRAM. By configuring the controller to control the DRAM of each processor, it is possible to control the DRAM conveniently and efficiently, and it is effective to determine the memory of the system at a low price.

Claims (3)

H / P control unit 2 in charge of the communication control between the host computer 1 and each processor (3, 4), and P / P control unit in charge of the communication control between each processor (3, 4) 5) and the address of the processor 3, 4 and the DRAM controllers 6 and 7 for accessing and refreshing the local DRAMs 12-2 and 13-2 and the global memories 14 and 15. The address drivers 8 and 9 supplied to the EPROMs 12-3 and 13-3 and the SRAMs 12-4 and 13-4 and the processors 3 and 4 under the control of the access arbitration unit 20. A tri-state multiplexer 10, 11 for supplying one of the DRAM control signals to the global memories 14, 15, and a local memory in which data for dedicated program processing of each processor 3, 4 is stored / decoded ( 12, 13, global memory 14, 15 consisting of DRAM, and bidirectional buffers 16, 17, 18, 19 that are switched so that each processor 3, 4 can access the desired global memory 14, 15. ) And each processor (3, 4 A memory access control apparatus of a multiprocessor system, comprising an access arbitration unit (20) for arbitrarily accessing or time-division accessing the global memory (14, 15). 2. The apparatus of claim 1, wherein the local memory (12, 13) comprises DRAMs (12-2, 13-2) as working memory of each processor. If each processor (3, 4) refers to the memory flag in the status register of another processor, the processor accesses and searches the global memory, and if the search results indicate that the global memory currently being accessed and the other processor are accessing the memory different from each other, After setting the memory flag and the start flag, read / write the global memory. If the global memory to be accessed is the same, refer to the start flag again and wait until this value is turned off. Then, set the memory flag and the start flag. A method of controlling memory access in a multiprocessor system, characterized by performing global memory access.